* [PATCH v2 0/5] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A
@ 2025-09-14 15:57 Xilin Wu
2025-09-14 15:57 ` [PATCH v2 1/5] dt-bindings: arm: qcom: Add " Xilin Wu
` (4 more replies)
0 siblings, 5 replies; 25+ messages in thread
From: Xilin Wu @ 2025-09-14 15:57 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong,
Viken Dadhaniya, Ram Kumar Dwivedi, Xilin Wu, Krzysztof Kozlowski
Radxa Dragon Q6A (https://docs.radxa.com/en/dragon/q6a) is a single board
computer, based on the Qualcomm QCS6490 platform.
The board ships with a modified version of the Qualcomm Linux boot
firmware, which is stored on the onboard SPI NOR flash. This allows
booting standard EFI-based bootloaders from SD/eMMC/USB/UFS/NVMe. It
supports replaceable UFS 3.1/eMMC modules for easy user upgrades.
The board schematic is available at [1].
Features enabled and working:
- Three USB-A 2.0 ports
- RTL8111K Ethernet connected to PCIe0
- eMMC module
- SD card
- M.2 M-Key 2230 PCIe 3.0 x2
- Headphone jack
- Onboard thermal sensors
- QSPI controller for updating boot firmware
- ADSP remoteproc (Type-C and charging features disabled in firmware)
- CDSP remoteproc (for AI applications using QNN)
- Venus video encode and decode accelerator
Features available with additional DT overlays:
- CSI cameras
- DSI display
Features that require unmet patch dependencies:
- USB-A 3.0 port
- UFS 3.1 module
- HDMI 2.0 port including audio
- Configurable I2C/SPI/UART from 40-Pin GPIO
ALSA UCM and Audioreach topology patches are available at [2] and [3].
[1]: https://docs.radxa.com/en/dragon/q6a/download
[2]: https://github.com/alsa-project/alsa-ucm-conf/pull/601
[3]: https://github.com/linux-msm/audioreach-topology/pull/24
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
Changes in v2:
- Move codec before cpu in sound node to get sorted.
- Drop patch dependencies in cover letter
- Separate the changes that have unmet dependencies, and mark them as DNM
- Link to v1: https://lore.kernel.org/r/20250912-radxa-dragon-q6a-v1-0-8ccdbf9cd19b@radxa.com
---
Xilin Wu (5):
dt-bindings: arm: qcom: Add Radxa Dragon Q6A
arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A
[DNM] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs
[DNM] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller
[DNM] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 1208 ++++++++++++++++++++
3 files changed, 1210 insertions(+)
---
base-commit: 590b221ed4256fd6c34d3dea77aa5bd6e741bbc1
change-id: 20250912-radxa-dragon-q6a-eedcdeaf3e66
Best regards,
--
Xilin Wu <sophon@radxa.com>
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v2 1/5] dt-bindings: arm: qcom: Add Radxa Dragon Q6A 2025-09-14 15:57 [PATCH v2 0/5] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A Xilin Wu @ 2025-09-14 15:57 ` Xilin Wu 2025-09-14 15:57 ` [PATCH v2 2/5] arm64: dts: qcom: qcs6490: Introduce " Xilin Wu ` (3 subsequent siblings) 4 siblings, 0 replies; 25+ messages in thread From: Xilin Wu @ 2025-09-14 15:57 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi, Xilin Wu, Krzysztof Kozlowski Radxa Dragon Q6A is a single board computer, based on the Qualcomm QCS6490 platform. Document the top-level compatible for this board. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xilin Wu <sophon@radxa.com> --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 0a3222d6f3686f1647b9e2ea192c175b0b96d48a..a7469a51adf0d6ebc1bf25acce8f125a844dcdbf 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -339,6 +339,7 @@ properties: - fairphone,fp5 - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 + - radxa,dragon-q6a - shift,otter - const: qcom,qcm6490 -- 2.51.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 2/5] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A 2025-09-14 15:57 [PATCH v2 0/5] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A Xilin Wu 2025-09-14 15:57 ` [PATCH v2 1/5] dt-bindings: arm: qcom: Add " Xilin Wu @ 2025-09-14 15:57 ` Xilin Wu 2025-09-14 17:39 ` Krzysztof Kozlowski 2025-09-14 15:57 ` [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs Xilin Wu ` (2 subsequent siblings) 4 siblings, 1 reply; 25+ messages in thread From: Xilin Wu @ 2025-09-14 15:57 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi, Xilin Wu, Krzysztof Kozlowski Radxa Dragon Q6A is a single board computer, based on the Qualcomm QCS6490 platform. Features enabled and working: - Three USB-A 2.0 ports - RTL8111K Ethernet connected to PCIe0 - eMMC module - SD card - M.2 M-Key 2230 PCIe 3.0 x2 - Headphone jack - Onboard thermal sensors - QSPI controller for updating boot firmware - ADSP remoteproc (Type-C and charging features disabled in firmware) - CDSP remoteproc (for AI applications using QNN) - Venus video encode and decode accelerator Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xilin Wu <sophon@radxa.com> --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 961 +++++++++++++++++++++ 2 files changed, 962 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5b52f9e4e5f31ac5a398d0762337a0a31af1f4dd..3a246adb0c435d7b08dda404ed2bcb2a9c8c48b0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -120,6 +120,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts new file mode 100644 index 0000000000000000000000000000000000000000..85465702279efb7ab324baea0663bdbdbd5fb5ac --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -0,0 +1,961 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sc7280.dtsi" +#include "pm7250b.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ +#include "qcs6490-audioreach.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &mpss_mem; +/delete-node/ &remoteproc_mpss; +/delete-node/ &remoteproc_wpss; +/delete-node/ &rmtfs_mem; +/delete-node/ &video_mem; +/delete-node/ &wifi; +/delete-node/ &wlan_ce_mem; +/delete-node/ &wlan_fw_mem; +/delete-node/ &wpss_mem; +/delete-node/ &xbl_mem; + +/ { + model = "Radxa Dragon Q6A"; + compatible = "radxa,dragon-q6a", "qcom,qcm6490"; + chassis-type = "embedded"; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &uart5; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9380-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>; + + vdd-rxtx-supply = <&vreg_l18b_1p8>; + vdd-io-supply = <&vreg_l18b_1p8>; + vdd-buck-supply = <&vreg_l17b_1p8>; + vdd-mic-bias-supply = <&vreg_bob_3p296>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + qcom,hphl-jack-type-normally-closed; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&user_led>; + pinctrl-names = "default"; + + user-led { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reserved-memory { + xbl_mem: xbl@80700000 { + reg = <0x0 0x80700000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg = <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + camera_mem: camera@84300000 { + reg = <0x0 0x84300000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp@84800000 { + reg = <0x0 0x84800000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@87000000 { + reg = <0x0 0x87000000 0x0 0x1e00000>; + no-map; + }; + + video_mem: video@88e00000 { + reg = <0x0 0x88e00000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp@89500000 { + reg = <0x0 0x89500000 0x0 0x500000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@89a00000 { + reg = <0x0 0x89a00000 0x0 0x2000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg = <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg = <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg = <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@c1800000 { + reg = <0x0 0xc1800000 0x0 0x1c00000>; + no-map; + }; + + debug_vm_mem: debug-vm@d0600000 { + reg = <0x0 0xd0600000 0x0 0x100000>; + no-map; + }; + }; + + thermal-zones { + msm-skin-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; + }; + + quiet-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; + }; + + ufs-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; + }; + + xo-thermal { + polling-delay-passive = <0>; + thermal-sensors = <&pmk8350_adc_tm 0>; + }; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_5v_peri>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v_peri>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_5v_peri: regulator-vcc-5v-peri { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v_peri"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vph_pwr>; + + regulator-boot-on; + regulator-always-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p536>; + vdd-l2-l7-supply = <&vreg_bob_3p296>; + vdd-l3-supply = <&vreg_s2b_0p572>; + vdd-l5-supply = <&vreg_s2b_0p572>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p2>; + vdd-l8-supply = <&vreg_s7b_0p536>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p84>; + vdd-l13-supply = <&vreg_s7b_0p536>; + vdd-l14-l16-supply = <&vreg_s8b_1p2>; + + vreg_s1b_1p84: smps1 { + regulator-name = "vreg_s1b_1p84"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s2b_0p572: smps2 { + regulator-name = "vreg_s2b_0p572"; + regulator-min-microvolt = <572000>; + regulator-max-microvolt = <1048000>; + }; + + vreg_s7b_0p536: smps7 { + regulator-name = "vreg_s7b_0p536"; + regulator-min-microvolt = <536000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p2: smps8 { + regulator-name = "vreg_s8b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1496000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name = "vreg_l7b_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_1p8: ldo17 { + regulator-name = "vreg_l17b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1b_1p84>; + vdd-l2-l8-supply = <&vreg_s1b_1p84>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; + vdd-l10-supply = <&vreg_s7b_0p536>; + vdd-bob-supply = <&vph_pwr>; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1976000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; + regulator-min-microvolt = <3032000>; + regulator-max-microvolt = <3960000>; + }; + }; +}; + +&gcc { + protected-clocks = <GCC_CFG_NOC_LPASS_CLK>, + <GCC_MSS_CFG_AHB_CLK>, + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, + <GCC_MSS_OFFLINE_AXI_CLK>, + <GCC_MSS_Q6SS_BOOT_CLK_SRC>, + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <GCC_MSS_SNOC_AXI_CLK>, + <GCC_SEC_CTRL_CLK_SRC>, + <GCC_WPSS_AHB_BDG_MST_CLK>, + <GCC_WPSS_AHB_CLK>, + <GCC_WPSS_RSCP_CLK>; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs6490/a660_zap.mbn"; +}; + +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + +&lpass_rx_macro { + status = "okay"; +}; + +&lpass_tx_macro { + status = "okay"; +}; + +&lpass_va_macro { + status = "okay"; +}; + +&pcie0 { + perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; + pinctrl-names = "default"; + + /* Support for QPS615 PCIe switch */ + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x208 &apps_smmu 0x1c84 0x1>, + <0x210 &apps_smmu 0x1c85 0x1>, + <0x218 &apps_smmu 0x1c86 0x1>, + <0x300 &apps_smmu 0x1c87 0x1>, + <0x400 &apps_smmu 0x1c88 0x1>, + <0x500 &apps_smmu 0x1c89 0x1>, + <0x501 &apps_smmu 0x1c90 0x1>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pm7325_gpios { + pm7325_adc_default: adc-default-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; +}; + +&pm7325_temp_alarm { + io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + msm-skin-therm@2 { + reg = <2>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + ufs-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_vadc { + pinctrl-0 = <&pm7325_adc_default>; + pinctrl-names = "default"; + + channel@3 { + reg = <PMK8350_ADC7_DIE_TEMP>; + label = "pmk7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; + label = "xo_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@103 { + reg = <PM7325_ADC7_DIE_TEMP>; + label = "pm7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = <PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "quiet_therm"; + }; + + channel@146 { + reg = <PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "msm_skin_therm"; + }; + + channel@14a { + /* According to datasheet, 0x4a = AMUX1_GPIO = GPIO_02 */ + reg = <PM7325_ADC7_GPIO1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "ufs_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&qspi { + /* It's not possible to use QSPI with iommu */ + /* due to an error in qcom_smmu_write_s2cr */ + /delete-property/ iommus; + + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, + <&qspi_data1>, <&qspi_data23>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; + + spi_flash: flash@0 { + compatible = "winbond,w25q256", "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <104000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs6490/radxa/dragon-q6a/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn"; + status = "okay"; +}; + +&sdhc_1 { + non-removable; + no-sd; + no-sdio; + + vmmc-supply = <&vreg_l7b_2p96>; + vqmmc-supply = <&vreg_l19b_1p8>; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; + + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_2p96>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sound { + compatible = "qcom,qcs6490-rb3gen2-sndcard"; + model = "QCS6490-Radxa-Dragon-Q6A"; + + audio-routing = + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; +}; + +&swr0 { + status = "okay"; + + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr1 { + status = "okay"; + + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + +&tlmm { + gpio-line-names = + /* GPIO_0 ~ GPIO_3 */ + "PIN_13", "PIN_15", "", "", + /* GPIO_4 ~ GPIO_7 */ + "", "", "", "", + /* GPIO_8 ~ GPIO_11 */ + "PIN_27", "PIN_28", "", "", + /* GPIO_12 ~ GPIO_15 */ + "", "", "", "", + /* GPIO_16 ~ GPIO_19 */ + "", "", "", "", + /* GPIO_20 ~ GPIO_23 */ + "", "", "PIN_8", "PIN_10", + /* GPIO_24 ~ GPIO_27 */ + "PIN_3", "PIN_5", "PIN_16", "PIN_27", + /* GPIO_28 ~ GPIO_31 */ + "PIN_31", "PIN_11", "PIN_32", "PIN_29", + /* GPIO_32 ~ GPIO_35 */ + "", "", "", "", + /* GPIO_36 ~ GPIO_39 */ + "", "", "", "", + /* GPIO_40 ~ GPIO_43 */ + "", "", "", "", + /* GPIO_44 ~ GPIO_47 */ + "", "", "", "", + /* GPIO_48 ~ GPIO_51 */ + "PIN_21", "PIN_19", "PIN_23", "PIN_24", + /* GPIO_52 ~ GPIO_55 */ + "", "", "", "PIN_26", + /* GPIO_56 ~ GPIO_59 */ + "PIN_33", "PIN_22", "PIN_37", "PIN_36", + /* GPIO_60 ~ GPIO_63 */ + "", "", "", "", + /* GPIO_64 ~ GPIO_67 */ + "", "", "", "", + /* GPIO_68 ~ GPIO_71 */ + "", "", "", "", + /* GPIO_72 ~ GPIO_75 */ + "", "", "", "", + /* GPIO_76 ~ GPIO_79 */ + "", "", "", "", + /* GPIO_80 ~ GPIO_83 */ + "", "", "", "", + /* GPIO_84 ~ GPIO_87 */ + "", "", "", "", + /* GPIO_88 ~ GPIO_91 */ + "", "", "", "", + /* GPIO_92 ~ GPIO_95 */ + "", "", "", "", + /* GPIO_96 ~ GPIO_99 */ + "PIN_7", "PIN_12", "PIN_38", "PIN_40", + /* GPIO_100 ~ GPIO_103 */ + "PIN_35", "", "", "", + /* GPIO_104 ~ GPIO_107 */ + "", "", "", "", + /* GPIO_108 ~ GPIO_111 */ + "", "", "", "", + /* GPIO_112 ~ GPIO_115 */ + "", "", "", "", + /* GPIO_116 ~ GPIO_119 */ + "", "", "", "", + /* GPIO_120 ~ GPIO_123 */ + "", "", "", "", + /* GPIO_124 ~ GPIO_127 */ + "", "", "", "", + /* GPIO_128 ~ GPIO_131 */ + "", "", "", "", + /* GPIO_132 ~ GPIO_135 */ + "", "", "", "", + /* GPIO_136 ~ GPIO_139 */ + "", "", "", "", + /* GPIO_140 ~ GPIO_143 */ + "", "", "", "", + /* GPIO_144 ~ GPIO_147 */ + "", "", "", "", + /* GPIO_148 ~ GPIO_151 */ + "", "", "", "", + /* GPIO_152 ~ GPIO_155 */ + "", "", "", "", + /* GPIO_156 ~ GPIO_159 */ + "", "", "", "", + /* GPIO_160 ~ GPIO_163 */ + "", "", "", "", + /* GPIO_164 ~ GPIO_167 */ + "", "", "", "", + /* GPIO_168 ~ GPIO_171 */ + "", "", "", "", + /* GPIO_172 ~ GPIO_174 */ + "", "", ""; + + pcie0_reset_n: pcie0-reset-n-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie1_reset_n: pcie1-reset-n-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qspi_sleep: qspi-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17"; + function = "gpio"; + output-disable; + }; + + sd_cd: sd-cd-state { + pins = "gpio91"; + function = "gpio"; + bias-pull-up; + }; + + user_led: user-led-state { + pins = "gpio42"; + function = "gpio"; + bias-pull-up; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&uart5 { + status = "okay"; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda33-supply = <&vreg_l2b_3p072>; + vdda18-supply = <&vreg_l1c_1p8>; +}; + +&venus { + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in sc7280.dtsi */ +&pcie0_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + +&qspi_clk { + bias-disable; + drive-strength = <16>; +}; + +&qspi_cs0 { + bias-disable; + drive-strength = <8>; +}; + +&qspi_data0 { + bias-disable; + drive-strength = <8>; +}; + +&qspi_data1 { + bias-disable; + drive-strength = <8>; +}; + +&qspi_data23 { + bias-disable; + drive-strength = <8>; +}; + +&sdc1_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc1_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_rclk { + bias-pull-down; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; -- 2.51.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v2 2/5] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A 2025-09-14 15:57 ` [PATCH v2 2/5] arm64: dts: qcom: qcs6490: Introduce " Xilin Wu @ 2025-09-14 17:39 ` Krzysztof Kozlowski 2025-09-15 1:20 ` Xilin Wu 0 siblings, 1 reply; 25+ messages in thread From: Krzysztof Kozlowski @ 2025-09-14 17:39 UTC (permalink / raw) To: Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi, Krzysztof Kozlowski On 14/09/2025 17:57, Xilin Wu wrote: > Radxa Dragon Q6A is a single board computer, based on the Qualcomm > QCS6490 platform. > > Features enabled and working: > > - Three USB-A 2.0 ports > - RTL8111K Ethernet connected to PCIe0 > - eMMC module > - SD card > - M.2 M-Key 2230 PCIe 3.0 x2 > - Headphone jack > - Onboard thermal sensors > - QSPI controller for updating boot firmware > - ADSP remoteproc (Type-C and charging features disabled in firmware) > - CDSP remoteproc (for AI applications using QNN) > - Venus video encode and decode accelerator > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> I see huge diff, like 200-300 lines being changed against v1 and you claim that I reviewed this one? No, that's not true. Please read submitting patches - if you change significantly the patch, you must drop the tag and explain the reason. NAK, unreviewed. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 2/5] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A 2025-09-14 17:39 ` Krzysztof Kozlowski @ 2025-09-15 1:20 ` Xilin Wu 0 siblings, 0 replies; 25+ messages in thread From: Xilin Wu @ 2025-09-15 1:20 UTC (permalink / raw) To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi, Krzysztof Kozlowski On 9/15/2025 1:39 AM, Krzysztof Kozlowski wrote: > On 14/09/2025 17:57, Xilin Wu wrote: >> Radxa Dragon Q6A is a single board computer, based on the Qualcomm >> QCS6490 platform. >> >> Features enabled and working: >> >> - Three USB-A 2.0 ports >> - RTL8111K Ethernet connected to PCIe0 >> - eMMC module >> - SD card >> - M.2 M-Key 2230 PCIe 3.0 x2 >> - Headphone jack >> - Onboard thermal sensors >> - QSPI controller for updating boot firmware >> - ADSP remoteproc (Type-C and charging features disabled in firmware) >> - CDSP remoteproc (for AI applications using QNN) >> - Venus video encode and decode accelerator >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > I see huge diff, like 200-300 lines being changed against v1 and you > claim that I reviewed this one? > > No, that's not true. Please read submitting patches - if you change > significantly the patch, you must drop the tag and explain the reason. > > NAK, unreviewed. > > Best regards, > Krzysztof > Hi Krzysztof, Thanks for your detailed review and clear feedback. My apologies for misusing the Reviewed-by tag on a modified patch and for incorrectly declaring dependencies in the DTS patches. I will address the issues in the next series. Thanks again for your guidance. -- Best regards, Xilin Wu <sophon@radxa.com> ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs 2025-09-14 15:57 [PATCH v2 0/5] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A Xilin Wu 2025-09-14 15:57 ` [PATCH v2 1/5] dt-bindings: arm: qcom: Add " Xilin Wu 2025-09-14 15:57 ` [PATCH v2 2/5] arm64: dts: qcom: qcs6490: Introduce " Xilin Wu @ 2025-09-14 15:57 ` Xilin Wu 2025-09-14 17:36 ` Krzysztof Kozlowski 2025-11-03 12:57 ` Konrad Dybcio 2025-09-14 15:57 ` [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller Xilin Wu 2025-09-14 15:57 ` [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports Xilin Wu 4 siblings, 2 replies; 25+ messages in thread From: Xilin Wu @ 2025-09-14 15:57 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi, Xilin Wu Add and enable all available QUP SEs on this board, allowing I2C, SPI and UART functions from the 40-Pin GPIO header to work. Signed-off-by: Xilin Wu <sophon@radxa.com> --- This change depends on the following patch series: https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/ --- .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index 85465702279efb7ab324baea0663bdbdbd5fb5ac..d30cddfc3eff07237c7e3480a5d42b29091d87d6 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -432,6 +432,14 @@ &gcc { <GCC_WPSS_RSCP_CLK>; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + &gpu { status = "okay"; }; @@ -440,6 +448,40 @@ &gpu_zap_shader { firmware-name = "qcom/qcs6490/a660_zap.mbn"; }; +/* Pin 13, 15 in GPIO header */ +&i2c0 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 27, 28 in GPIO header */ +&i2c2 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 3, 5 in GPIO header */ +&i2c6 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +&i2c10 { + qcom,enable-gsi-dma; + status = "okay"; + + rtc: rtc@68 { + compatible = "st,m41t11"; + reg = <0x68>; + }; +}; + +/* External touchscreen */ +&i2c13 { + qcom,enable-gsi-dma; + status = "okay"; +}; + &lpass_audiocc { compatible = "qcom,qcm6490-lpassaudiocc"; /delete-property/ power-domains; @@ -624,6 +666,12 @@ spi_flash: flash@0 { }; &qupv3_id_0 { + firmware-name = "qcom/qcm6490/qupv3fw.elf"; + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcm6490/qupv3fw.elf"; status = "okay"; }; @@ -702,6 +750,24 @@ platform { }; }; +/* Pin 11, 29, 31, 32 in GPIO header */ +&spi7 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 19, 21, 23, 24, 26 in GPIO header */ +&spi12 { + qcom,enable-gsi-dma; + status = "okay"; +}; + +/* Pin 22, 33, 36, 37 in GPIO header */ +&spi14 { + qcom,enable-gsi-dma; + status = "okay"; +}; + &swr0 { status = "okay"; -- 2.51.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs 2025-09-14 15:57 ` [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs Xilin Wu @ 2025-09-14 17:36 ` Krzysztof Kozlowski 2025-09-15 7:13 ` Konrad Dybcio 2025-11-03 12:57 ` Konrad Dybcio 1 sibling, 1 reply; 25+ messages in thread From: Krzysztof Kozlowski @ 2025-09-14 17:36 UTC (permalink / raw) To: Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 14/09/2025 17:57, Xilin Wu wrote: > Add and enable all available QUP SEs on this board, allowing I2C, SPI and > UART functions from the 40-Pin GPIO header to work. > > Signed-off-by: Xilin Wu <sophon@radxa.com> > > --- > > This change depends on the following patch series: > https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/ No, why? It does not. If your DTS depends on drivers it's a mistake to fix. Fix dependency or squash the patches. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs 2025-09-14 17:36 ` Krzysztof Kozlowski @ 2025-09-15 7:13 ` Konrad Dybcio 2025-09-15 7:26 ` Krzysztof Kozlowski 0 siblings, 1 reply; 25+ messages in thread From: Konrad Dybcio @ 2025-09-15 7:13 UTC (permalink / raw) To: Krzysztof Kozlowski, Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 9/14/25 7:36 PM, Krzysztof Kozlowski wrote: > On 14/09/2025 17:57, Xilin Wu wrote: >> Add and enable all available QUP SEs on this board, allowing I2C, SPI and >> UART functions from the 40-Pin GPIO header to work. >> >> Signed-off-by: Xilin Wu <sophon@radxa.com> >> >> --- >> >> This change depends on the following patch series: >> https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/ > > > No, why? It does not. If your DTS depends on drivers it's a mistake to fix. > > Fix dependency or squash the patches. That series also includes bindings changes Konrad ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs 2025-09-15 7:13 ` Konrad Dybcio @ 2025-09-15 7:26 ` Krzysztof Kozlowski 0 siblings, 0 replies; 25+ messages in thread From: Krzysztof Kozlowski @ 2025-09-15 7:26 UTC (permalink / raw) To: Konrad Dybcio, Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 15/09/2025 09:13, Konrad Dybcio wrote: > On 9/14/25 7:36 PM, Krzysztof Kozlowski wrote: >> On 14/09/2025 17:57, Xilin Wu wrote: >>> Add and enable all available QUP SEs on this board, allowing I2C, SPI and >>> UART functions from the 40-Pin GPIO header to work. >>> >>> Signed-off-by: Xilin Wu <sophon@radxa.com> >>> >>> --- >>> >>> This change depends on the following patch series: >>> https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/ >> >> >> No, why? It does not. If your DTS depends on drivers it's a mistake to fix. >> >> Fix dependency or squash the patches. > > That series also includes bindings changes So how does this depends on the bindings? What it the exact dependency that you need to wait one cycle? Cannot be merged to next the same time? That's a warning sign... and I really do not understand how new board depends on the bindings. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs 2025-09-14 15:57 ` [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs Xilin Wu 2025-09-14 17:36 ` Krzysztof Kozlowski @ 2025-11-03 12:57 ` Konrad Dybcio 2025-11-03 13:04 ` Xilin Wu 1 sibling, 1 reply; 25+ messages in thread From: Konrad Dybcio @ 2025-11-03 12:57 UTC (permalink / raw) To: Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 9/14/25 5:57 PM, Xilin Wu wrote: > Add and enable all available QUP SEs on this board, allowing I2C, SPI and > UART functions from the 40-Pin GPIO header to work. > > Signed-off-by: Xilin Wu <sophon@radxa.com> > > --- > > This change depends on the following patch series: > https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/ You should be good to go resending this change now, the series is in> --- > .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 66 ++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > index 85465702279efb7ab324baea0663bdbdbd5fb5ac..d30cddfc3eff07237c7e3480a5d42b29091d87d6 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > @@ -432,6 +432,14 @@ &gcc { > <GCC_WPSS_RSCP_CLK>; > }; > > +&gpi_dma0 { > + status = "okay"; > +}; > + > +&gpi_dma1 { > + status = "okay"; > +}; > + > &gpu { > status = "okay"; > }; > @@ -440,6 +448,40 @@ &gpu_zap_shader { > firmware-name = "qcom/qcs6490/a660_zap.mbn"; > }; > > +/* Pin 13, 15 in GPIO header */ > +&i2c0 { > + qcom,enable-gsi-dma; > + status = "okay"; Please leave a spare \n before status, otherwise lgtm Konrad ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs 2025-11-03 12:57 ` Konrad Dybcio @ 2025-11-03 13:04 ` Xilin Wu 2025-11-03 13:06 ` Konrad Dybcio 0 siblings, 1 reply; 25+ messages in thread From: Xilin Wu @ 2025-11-03 13:04 UTC (permalink / raw) To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 11/3/2025 8:57 PM, Konrad Dybcio wrote: > On 9/14/25 5:57 PM, Xilin Wu wrote: >> Add and enable all available QUP SEs on this board, allowing I2C, SPI and >> UART functions from the 40-Pin GPIO header to work. >> >> Signed-off-by: Xilin Wu <sophon@radxa.com> >> >> --- >> >> This change depends on the following patch series: >> https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/ > > You should be good to go resending this change now Thanks for the reminder. I added the QUP parts in v4 of my patch series, and it's already merged :) https://lore.kernel.org/all/20250929-radxa-dragon-q6a-v5-2-aa96ffc352f8@radxa.com/ -- Best regards, Xilin Wu <sophon@radxa.com> ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs 2025-11-03 13:04 ` Xilin Wu @ 2025-11-03 13:06 ` Konrad Dybcio 0 siblings, 0 replies; 25+ messages in thread From: Konrad Dybcio @ 2025-11-03 13:06 UTC (permalink / raw) To: Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 11/3/25 2:04 PM, Xilin Wu wrote: > On 11/3/2025 8:57 PM, Konrad Dybcio wrote: >> On 9/14/25 5:57 PM, Xilin Wu wrote: >>> Add and enable all available QUP SEs on this board, allowing I2C, SPI and >>> UART functions from the 40-Pin GPIO header to work. >>> >>> Signed-off-by: Xilin Wu <sophon@radxa.com> >>> >>> --- >>> >>> This change depends on the following patch series: >>> https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/ >> >> You should be good to go resending this change now > > Thanks for the reminder. I added the QUP parts in v4 of my patch series, and it's already merged :) > > https://lore.kernel.org/all/20250929-radxa-dragon-q6a-v5-2-aa96ffc352f8@radxa.com/ I had this patch marked as stale in my inbox, it's good to see it was delivered after all :) Konrad> > ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller 2025-09-14 15:57 [PATCH v2 0/5] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A Xilin Wu ` (2 preceding siblings ...) 2025-09-14 15:57 ` [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs Xilin Wu @ 2025-09-14 15:57 ` Xilin Wu 2025-09-14 17:37 ` Krzysztof Kozlowski 2025-09-15 7:24 ` Konrad Dybcio 2025-09-14 15:57 ` [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports Xilin Wu 4 siblings, 2 replies; 25+ messages in thread From: Xilin Wu @ 2025-09-14 15:57 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi, Xilin Wu Add and enable UFS related nodes for this board. Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design limitations. UFS on this board is stable when working at Gear-4 Rate-A. Signed-off-by: Xilin Wu <sophon@radxa.com> --- This change depends on the following patch series: https://lore.kernel.org/all/20250902164900.21685-1-quic_rdwivedi@quicinc.com/ --- .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index d30cddfc3eff07237c7e3480a5d42b29091d87d6..3bf85d68c97891db1f1f0b84fb5649803948e06f 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -482,6 +482,11 @@ &i2c13 { status = "okay"; }; +/* It takes a long time in ufshcd_init_crypto when enabled */ +&ice { + status = "disabled"; +}; + &lpass_audiocc { compatible = "qcom,qcm6490-lpassaudiocc"; /delete-property/ power-domains; @@ -938,6 +943,30 @@ &uart5 { status = "okay"; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p96>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <1300000>; + + /* Gear-4 Rate-B is unstable due to board */ + /* and UFS module design limitations */ + limit-rate = "rate-a"; + /delete-property/ qcom,ice; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + &usb_2 { dr_mode = "host"; -- 2.51.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller 2025-09-14 15:57 ` [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller Xilin Wu @ 2025-09-14 17:37 ` Krzysztof Kozlowski 2025-09-15 7:24 ` Konrad Dybcio 1 sibling, 0 replies; 25+ messages in thread From: Krzysztof Kozlowski @ 2025-09-14 17:37 UTC (permalink / raw) To: Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 14/09/2025 17:57, Xilin Wu wrote: > Add and enable UFS related nodes for this board. > > Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design > limitations. UFS on this board is stable when working at Gear-4 Rate-A. > > Signed-off-by: Xilin Wu <sophon@radxa.com> > > --- > > This change depends on the following patch series: > https://lore.kernel.org/all/20250902164900.21685-1-quic_rdwivedi@quicinc.com/ Please don't add fake dependencies just to inflate the patchset. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller 2025-09-14 15:57 ` [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller Xilin Wu 2025-09-14 17:37 ` Krzysztof Kozlowski @ 2025-09-15 7:24 ` Konrad Dybcio 2025-09-15 7:34 ` Xilin Wu 1 sibling, 1 reply; 25+ messages in thread From: Konrad Dybcio @ 2025-09-15 7:24 UTC (permalink / raw) To: Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 9/14/25 5:57 PM, Xilin Wu wrote: > Add and enable UFS related nodes for this board. > > Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design > limitations. UFS on this board is stable when working at Gear-4 Rate-A. > > Signed-off-by: Xilin Wu <sophon@radxa.com> > > --- > > This change depends on the following patch series: > https://lore.kernel.org/all/20250902164900.21685-1-quic_rdwivedi@quicinc.com/ > --- > .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 29 ++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > index d30cddfc3eff07237c7e3480a5d42b29091d87d6..3bf85d68c97891db1f1f0b84fb5649803948e06f 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > @@ -482,6 +482,11 @@ &i2c13 { > status = "okay"; > }; > > +/* It takes a long time in ufshcd_init_crypto when enabled */ Huh? It only turns on some clocks, writes a couple of mmio registers and turns the clocks back off, could you investigate a little more? > +&ice { > + status = "disabled"; > +}; > + > &lpass_audiocc { > compatible = "qcom,qcm6490-lpassaudiocc"; > /delete-property/ power-domains; > @@ -938,6 +943,30 @@ &uart5 { > status = "okay"; > }; > > +&ufs_mem_hc { > + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; > + vcc-supply = <&vreg_l7b_2p96>; > + vcc-max-microamp = <800000>; > + vccq-supply = <&vreg_l9b_1p2>; > + vccq-max-microamp = <900000>; > + vccq2-supply = <&vreg_l9b_1p2>; > + vccq2-max-microamp = <1300000>; > + > + /* Gear-4 Rate-B is unstable due to board */ > + /* and UFS module design limitations */ /* Gear-4 Rate-B is unstable due to board and UFS module design limitations */ Konrad ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller 2025-09-15 7:24 ` Konrad Dybcio @ 2025-09-15 7:34 ` Xilin Wu 2025-10-08 9:53 ` Konrad Dybcio 0 siblings, 1 reply; 25+ messages in thread From: Xilin Wu @ 2025-09-15 7:34 UTC (permalink / raw) To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 9/15/2025 3:24 PM, Konrad Dybcio wrote: > On 9/14/25 5:57 PM, Xilin Wu wrote: >> Add and enable UFS related nodes for this board. >> >> Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design >> limitations. UFS on this board is stable when working at Gear-4 Rate-A. >> >> Signed-off-by: Xilin Wu <sophon@radxa.com> >> >> --- >> >> This change depends on the following patch series: >> https://lore.kernel.org/all/20250902164900.21685-1-quic_rdwivedi@quicinc.com/ >> --- >> .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 29 ++++++++++++++++++++++ >> 1 file changed, 29 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >> index d30cddfc3eff07237c7e3480a5d42b29091d87d6..3bf85d68c97891db1f1f0b84fb5649803948e06f 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >> @@ -482,6 +482,11 @@ &i2c13 { >> status = "okay"; >> }; >> >> +/* It takes a long time in ufshcd_init_crypto when enabled */ > > Huh? It only turns on some clocks, writes a couple of mmio registers > and turns the clocks back off, could you investigate a little more? More specifically, it takes a long time in `qcom_scm_ice_invalidate_key`. Considering this platform boots from SPI NOR, while TrustZone doesn't really support SPI NOR storage on this platform, there could be something broken in TZ. >> +&ice { >> + status = "disabled"; >> +}; >> + >> &lpass_audiocc { >> compatible = "qcom,qcm6490-lpassaudiocc"; >> /delete-property/ power-domains; >> @@ -938,6 +943,30 @@ &uart5 { >> status = "okay"; >> }; >> >> +&ufs_mem_hc { >> + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; >> + vcc-supply = <&vreg_l7b_2p96>; >> + vcc-max-microamp = <800000>; >> + vccq-supply = <&vreg_l9b_1p2>; >> + vccq-max-microamp = <900000>; >> + vccq2-supply = <&vreg_l9b_1p2>; >> + vccq2-max-microamp = <1300000>; >> + >> + /* Gear-4 Rate-B is unstable due to board */ >> + /* and UFS module design limitations */ > > /* Gear-4 Rate-B is unstable due to board and UFS module design limitations */ > > Konrad > -- Best regards, Xilin Wu <sophon@radxa.com> ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller 2025-09-15 7:34 ` Xilin Wu @ 2025-10-08 9:53 ` Konrad Dybcio 2025-10-09 2:16 ` Xilin Wu 0 siblings, 1 reply; 25+ messages in thread From: Konrad Dybcio @ 2025-10-08 9:53 UTC (permalink / raw) To: Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 9/15/25 9:34 AM, Xilin Wu wrote: > On 9/15/2025 3:24 PM, Konrad Dybcio wrote: >> On 9/14/25 5:57 PM, Xilin Wu wrote: >>> Add and enable UFS related nodes for this board. >>> >>> Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design >>> limitations. UFS on this board is stable when working at Gear-4 Rate-A. >>> >>> Signed-off-by: Xilin Wu <sophon@radxa.com> >>> >>> --- >>> >>> This change depends on the following patch series: >>> https://lore.kernel.org/all/20250902164900.21685-1-quic_rdwivedi@quicinc.com/ >>> --- >>> .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 29 ++++++++++++++++++++++ >>> 1 file changed, 29 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >>> index d30cddfc3eff07237c7e3480a5d42b29091d87d6..3bf85d68c97891db1f1f0b84fb5649803948e06f 100644 >>> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >>> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >>> @@ -482,6 +482,11 @@ &i2c13 { >>> status = "okay"; >>> }; >>> +/* It takes a long time in ufshcd_init_crypto when enabled */ >> >> Huh? It only turns on some clocks, writes a couple of mmio registers >> and turns the clocks back off, could you investigate a little more? > > More specifically, it takes a long time in `qcom_scm_ice_invalidate_key`. Considering this platform boots from SPI NOR, while TrustZone doesn't really support SPI NOR storage on this platform, there could be something broken in TZ. Hm.. if you change the boot order (if you can on your board..) to start with UFS (which would require reflashing of all boot sw onto there), does this still manifest? Konrad ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller 2025-10-08 9:53 ` Konrad Dybcio @ 2025-10-09 2:16 ` Xilin Wu 0 siblings, 0 replies; 25+ messages in thread From: Xilin Wu @ 2025-10-09 2:16 UTC (permalink / raw) To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 10/8/2025 5:53 PM, Konrad Dybcio wrote: > On 9/15/25 9:34 AM, Xilin Wu wrote: >> On 9/15/2025 3:24 PM, Konrad Dybcio wrote: >>> On 9/14/25 5:57 PM, Xilin Wu wrote: >>>> Add and enable UFS related nodes for this board. >>>> >>>> Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design >>>> limitations. UFS on this board is stable when working at Gear-4 Rate-A. >>>> >>>> Signed-off-by: Xilin Wu <sophon@radxa.com> >>>> >>>> --- >>>> >>>> This change depends on the following patch series: >>>> https://lore.kernel.org/all/20250902164900.21685-1-quic_rdwivedi@quicinc.com/ >>>> --- >>>> .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 29 ++++++++++++++++++++++ >>>> 1 file changed, 29 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >>>> index d30cddfc3eff07237c7e3480a5d42b29091d87d6..3bf85d68c97891db1f1f0b84fb5649803948e06f 100644 >>>> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >>>> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >>>> @@ -482,6 +482,11 @@ &i2c13 { >>>> status = "okay"; >>>> }; >>>> +/* It takes a long time in ufshcd_init_crypto when enabled */ >>> >>> Huh? It only turns on some clocks, writes a couple of mmio registers >>> and turns the clocks back off, could you investigate a little more? >> >> More specifically, it takes a long time in `qcom_scm_ice_invalidate_key`. Considering this platform boots from SPI NOR, while TrustZone doesn't really support SPI NOR storage on this platform, there could be something broken in TZ. > > Hm.. if you change the boot order (if you can on your board..) to start > with UFS (which would require reflashing of all boot sw onto there), does > this still manifest? Unfortunately the board is designed to boot from SPI NOR only. And there's no way to change that without replacing some resistors on the board. Just now I tried a v6.17 based kernel, it now simply triggers a reset somewhere when ICE is enabled. -- Best regards, Xilin Wu <sophon@radxa.com> ^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports 2025-09-14 15:57 [PATCH v2 0/5] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A Xilin Wu ` (3 preceding siblings ...) 2025-09-14 15:57 ` [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller Xilin Wu @ 2025-09-14 15:57 ` Xilin Wu 2025-09-14 17:37 ` Krzysztof Kozlowski ` (2 more replies) 4 siblings, 3 replies; 25+ messages in thread From: Xilin Wu @ 2025-09-14 15:57 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi, Xilin Wu This board doesn't feature a regular Type-C port. The usb_1_qmpphy's RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0 pair is connected to the RA620 DP-to-HDMI bridge. Add and enable the nodes for the features to work. Signed-off-by: Xilin Wu <sophon@radxa.com> --- This change depends on the following patch series: https://lore.kernel.org/all/20250908-topic-x1e80100-hdmi-v3-4-c53b0f2bc2fb@linaro.org/ --- .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 152 +++++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index 3bf85d68c97891db1f1f0b84fb5649803948e06f..12bc9a0fcfbfeaabf6ede351f96c61193a8261c0 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -78,6 +78,71 @@ chosen { stdout-path = "serial0:115200n8"; }; + usb3_con: connector { + compatible = "usb-a-connector"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb3_con_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + usb3_con_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out_usb>; + }; + }; + }; + }; + + hdmi-bridge { + compatible = "radxa,ra620"; + + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_bridge_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -504,6 +569,21 @@ &lpass_va_macro { status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_dp { + sound-name-prefix = "Display Port0"; + + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + &pcie0 { perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; @@ -753,6 +833,22 @@ platform { sound-dai = <&q6apm>; }; }; + + dp0-dai-link { + link-name = "DP0 Playback"; + + codec { + sound-dai = <&mdss_dp>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; }; /* Pin 11, 29, 31, 32 in GPIO header */ @@ -967,6 +1063,58 @@ &ufs_mem_phy { status = "okay"; }; +&usb_1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&usb3_con_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda33-supply = <&vreg_l2b_3p072>; + vdda18-supply = <&vreg_l1c_1p8>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p912>; + + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + /* RX1/TX1 is statically connected to USB-A port */ + usb_dp_qmpphy_out_usb: endpoint@0 { + reg = <0>; + + data-lanes = <2 3>; + remote-endpoint = <&usb3_con_ss_in>; + }; + + /* RX0/TX0 is statically connected to RA620 bridge */ + usb_dp_qmpphy_out_dp: endpoint@1 { + reg = <1>; + + data-lanes = <3 2>; + remote-endpoint = <&hdmi_bridge_in>; + }; + }; + }; +}; + &usb_2 { dr_mode = "host"; @@ -986,6 +1134,10 @@ &venus { }; /* PINCTRL - additions to nodes defined in sc7280.dtsi */ +&dp_hot_plug_det { + bias-disable; +}; + &pcie0_clkreq_n { bias-pull-up; drive-strength = <2>; -- 2.51.0 ^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports 2025-09-14 15:57 ` [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports Xilin Wu @ 2025-09-14 17:37 ` Krzysztof Kozlowski 2025-09-15 6:51 ` Neil Armstrong 2025-09-15 7:27 ` Konrad Dybcio 2 siblings, 0 replies; 25+ messages in thread From: Krzysztof Kozlowski @ 2025-09-14 17:37 UTC (permalink / raw) To: Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 14/09/2025 17:57, Xilin Wu wrote: > This board doesn't feature a regular Type-C port. The usb_1_qmpphy's > RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0 > pair is connected to the RA620 DP-to-HDMI bridge. > > Add and enable the nodes for the features to work. > > Signed-off-by: Xilin Wu <sophon@radxa.com> > > --- > > This change depends on the following patch series: > https://lore.kernel.org/all/20250908-topic-x1e80100-hdmi-v3-4-c53b0f2bc2fb@linaro.org/ NAK, you cannot depend on drivers. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports 2025-09-14 15:57 ` [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports Xilin Wu 2025-09-14 17:37 ` Krzysztof Kozlowski @ 2025-09-15 6:51 ` Neil Armstrong 2025-09-15 7:04 ` Xilin Wu 2025-09-15 7:27 ` Konrad Dybcio 2 siblings, 1 reply; 25+ messages in thread From: Neil Armstrong @ 2025-09-15 6:51 UTC (permalink / raw) To: Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Viken Dadhaniya, Ram Kumar Dwivedi On 14/09/2025 17:57, Xilin Wu wrote: > This board doesn't feature a regular Type-C port. The usb_1_qmpphy's > RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0 > pair is connected to the RA620 DP-to-HDMI bridge. > > Add and enable the nodes for the features to work. > > Signed-off-by: Xilin Wu <sophon@radxa.com> > > --- > > This change depends on the following patch series: > https://lore.kernel.org/all/20250908-topic-x1e80100-hdmi-v3-4-c53b0f2bc2fb@linaro.org/ > --- > .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 152 +++++++++++++++++++++ > 1 file changed, 152 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > index 3bf85d68c97891db1f1f0b84fb5649803948e06f..12bc9a0fcfbfeaabf6ede351f96c61193a8261c0 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > @@ -78,6 +78,71 @@ chosen { > stdout-path = "serial0:115200n8"; > }; > > + usb3_con: connector { > + compatible = "usb-a-connector"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + usb3_con_hs_in: endpoint { > + remote-endpoint = <&usb_1_dwc3_hs>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + usb3_con_ss_in: endpoint { > + remote-endpoint = <&usb_dp_qmpphy_out_usb>; > + }; > + }; > + }; > + }; > + > + hdmi-bridge { > + compatible = "radxa,ra620"; > + > + pinctrl-0 = <&dp_hot_plug_det>; > + pinctrl-names = "default"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + hdmi_bridge_in: endpoint { > + remote-endpoint = <&usb_dp_qmpphy_out_dp>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + hdmi_bridge_out: endpoint { > + remote-endpoint = <&hdmi_connector_in>; > + }; > + }; > + }; > + }; > + > + hdmi-connector { > + compatible = "hdmi-connector"; > + label = "hdmi"; > + type = "a"; > + > + port { > + hdmi_connector_in: endpoint { > + remote-endpoint = <&hdmi_bridge_out>; > + }; > + }; > + }; > + > leds { > compatible = "gpio-leds"; > > @@ -504,6 +569,21 @@ &lpass_va_macro { > status = "okay"; > }; > > +&mdss { > + status = "okay"; > +}; > + > +&mdss_dp { > + sound-name-prefix = "Display Port0"; > + > + status = "okay"; > +}; > + > +&mdss_dp_out { > + data-lanes = <0 1>; > + remote-endpoint = <&usb_dp_qmpphy_dp_in>; > +}; > + > &pcie0 { > perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; > wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; > @@ -753,6 +833,22 @@ platform { > sound-dai = <&q6apm>; > }; > }; > + > + dp0-dai-link { > + link-name = "DP0 Playback"; > + > + codec { > + sound-dai = <&mdss_dp>; > + }; > + > + cpu { > + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; > + }; > + > + platform { > + sound-dai = <&q6apm>; > + }; > + }; > }; > > /* Pin 11, 29, 31, 32 in GPIO header */ > @@ -967,6 +1063,58 @@ &ufs_mem_phy { > status = "okay"; > }; > > +&usb_1 { > + dr_mode = "host"; > + > + status = "okay"; > +}; > + > +&usb_1_dwc3_hs { > + remote-endpoint = <&usb3_con_hs_in>; > +}; > + > +&usb_1_hsphy { > + vdda-pll-supply = <&vreg_l10c_0p88>; > + vdda33-supply = <&vreg_l2b_3p072>; > + vdda18-supply = <&vreg_l1c_1p8>; > + > + status = "okay"; > +}; > + > +&usb_1_qmpphy { > + vdda-phy-supply = <&vreg_l6b_1p2>; > + vdda-pll-supply = <&vreg_l1b_0p912>; > + > + /delete-property/ orientation-switch; > + > + status = "okay"; > + > + ports { > + port@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /delete-node/ endpoint; > + > + /* RX1/TX1 is statically connected to USB-A port */ > + usb_dp_qmpphy_out_usb: endpoint@0 { > + reg = <0>; > + > + data-lanes = <2 3>; > + remote-endpoint = <&usb3_con_ss_in>; > + }; > + > + /* RX0/TX0 is statically connected to RA620 bridge */ > + usb_dp_qmpphy_out_dp: endpoint@1 { > + reg = <1>; > + > + data-lanes = <3 2>; > + remote-endpoint = <&hdmi_bridge_in>; > + }; In this WiP patchset endpoint@0 is suposed to be DisplayPort, and endpoint@1 for USB3 lanes. And you must not have colliding data-lanes, so it should be something like: /* DP0/DP1 is statically connected to a RA620 bridge*/ usb_dp_qmpphy_out_dp: endpoint@0 { reg = <0>; data-lanes = <0 1>; remote-endpoint = <&hdmi_bridge_in>; }; /* RX0/TX0 is statically connected to an USB-A Connector */ usb_dp_qmpphy_out_usb: endpoint@1 { reg = <1>; data-lanes = <2 3>; remote-endpoint = <&usb3_con_ss_in>; }; But I just found out while reviewed my patchset is wrong... it should be: + endpoint@0: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + description: Display Port Output lanes of the PHY when used with static mapping + unevaluatedProperties: false + + properties: + data-lanes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 4 + oneOf: + - items: # DisplayPort 2 lanes, normal orientation + - const: 3 + - const: 2 + - items: # DisplayPort 2 lanes, flipped orientation + - const: 0 + - const: 1 + - items: # DisplayPort 4 lanes, normal orientation + - const: 0 + - const: 1 + - const: 2 + - const: 3 + - items: # DisplayPort 4 lanes, flipped orientation + - const: 3 + - const: 2 + - const: 1 + - const: 0 and in driver: +static const u32 dp_2_data_lanes_mapping[][2] = { + [TYPEC_ORIENTATION_NORMAL] = { 3, 2 }, + [TYPEC_ORIENTATION_REVERSE] = { 0, 1 }, Neil + }; > + }; > +}; > + > &usb_2 { > dr_mode = "host"; > > @@ -986,6 +1134,10 @@ &venus { > }; > > /* PINCTRL - additions to nodes defined in sc7280.dtsi */ > +&dp_hot_plug_det { > + bias-disable; > +}; > + > &pcie0_clkreq_n { > bias-pull-up; > drive-strength = <2>; > ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports 2025-09-15 6:51 ` Neil Armstrong @ 2025-09-15 7:04 ` Xilin Wu 2025-09-15 7:51 ` Neil Armstrong 0 siblings, 1 reply; 25+ messages in thread From: Xilin Wu @ 2025-09-15 7:04 UTC (permalink / raw) To: Neil Armstrong, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Viken Dadhaniya, Ram Kumar Dwivedi On 9/15/2025 2:51 PM, Neil Armstrong wrote: > On 14/09/2025 17:57, Xilin Wu wrote: >> This board doesn't feature a regular Type-C port. The usb_1_qmpphy's >> RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0 >> pair is connected to the RA620 DP-to-HDMI bridge. >> >> Add and enable the nodes for the features to work. >> >> Signed-off-by: Xilin Wu <sophon@radxa.com> >> >> --- >> >> This change depends on the following patch series: >> https://lore.kernel.org/all/20250908-topic-x1e80100-hdmi-v3-4- >> c53b0f2bc2fb@linaro.org/ >> --- >> .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 152 +++++++++++ >> ++++++++++ >> 1 file changed, 152 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/ >> arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >> index >> 3bf85d68c97891db1f1f0b84fb5649803948e06f..12bc9a0fcfbfeaabf6ede351f96c61193a8261c0 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >> @@ -78,6 +78,71 @@ chosen { >> stdout-path = "serial0:115200n8"; >> }; >> + usb3_con: connector { >> + compatible = "usb-a-connector"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + >> + usb3_con_hs_in: endpoint { >> + remote-endpoint = <&usb_1_dwc3_hs>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + >> + usb3_con_ss_in: endpoint { >> + remote-endpoint = <&usb_dp_qmpphy_out_usb>; >> + }; >> + }; >> + }; >> + }; >> + >> + hdmi-bridge { >> + compatible = "radxa,ra620"; >> + >> + pinctrl-0 = <&dp_hot_plug_det>; >> + pinctrl-names = "default"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + >> + hdmi_bridge_in: endpoint { >> + remote-endpoint = <&usb_dp_qmpphy_out_dp>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + >> + hdmi_bridge_out: endpoint { >> + remote-endpoint = <&hdmi_connector_in>; >> + }; >> + }; >> + }; >> + }; >> + >> + hdmi-connector { >> + compatible = "hdmi-connector"; >> + label = "hdmi"; >> + type = "a"; >> + >> + port { >> + hdmi_connector_in: endpoint { >> + remote-endpoint = <&hdmi_bridge_out>; >> + }; >> + }; >> + }; >> + >> leds { >> compatible = "gpio-leds"; >> @@ -504,6 +569,21 @@ &lpass_va_macro { >> status = "okay"; >> }; >> +&mdss { >> + status = "okay"; >> +}; >> + >> +&mdss_dp { >> + sound-name-prefix = "Display Port0"; >> + >> + status = "okay"; >> +}; >> + >> +&mdss_dp_out { >> + data-lanes = <0 1>; >> + remote-endpoint = <&usb_dp_qmpphy_dp_in>; >> +}; >> + >> &pcie0 { >> perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; >> wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; >> @@ -753,6 +833,22 @@ platform { >> sound-dai = <&q6apm>; >> }; >> }; >> + >> + dp0-dai-link { >> + link-name = "DP0 Playback"; >> + >> + codec { >> + sound-dai = <&mdss_dp>; >> + }; >> + >> + cpu { >> + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; >> + }; >> + >> + platform { >> + sound-dai = <&q6apm>; >> + }; >> + }; >> }; >> /* Pin 11, 29, 31, 32 in GPIO header */ >> @@ -967,6 +1063,58 @@ &ufs_mem_phy { >> status = "okay"; >> }; >> +&usb_1 { >> + dr_mode = "host"; >> + >> + status = "okay"; >> +}; >> + >> +&usb_1_dwc3_hs { >> + remote-endpoint = <&usb3_con_hs_in>; >> +}; >> + >> +&usb_1_hsphy { >> + vdda-pll-supply = <&vreg_l10c_0p88>; >> + vdda33-supply = <&vreg_l2b_3p072>; >> + vdda18-supply = <&vreg_l1c_1p8>; >> + >> + status = "okay"; >> +}; >> + >> +&usb_1_qmpphy { >> + vdda-phy-supply = <&vreg_l6b_1p2>; >> + vdda-pll-supply = <&vreg_l1b_0p912>; >> + >> + /delete-property/ orientation-switch; >> + >> + status = "okay"; >> + >> + ports { >> + port@0 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + /delete-node/ endpoint; >> + >> + /* RX1/TX1 is statically connected to USB-A port */ >> + usb_dp_qmpphy_out_usb: endpoint@0 { >> + reg = <0>; >> + >> + data-lanes = <2 3>; >> + remote-endpoint = <&usb3_con_ss_in>; >> + }; >> + >> + /* RX0/TX0 is statically connected to RA620 bridge */ >> + usb_dp_qmpphy_out_dp: endpoint@1 { >> + reg = <1>; >> + >> + data-lanes = <3 2>; >> + remote-endpoint = <&hdmi_bridge_in>; >> + }; > > In this WiP patchset endpoint@0 is suposed to be DisplayPort, and > endpoint@1 for USB3 lanes. > > And you must not have colliding data-lanes, so it should be something like: > > /* DP0/DP1 is statically connected to a RA620 bridge*/ > usb_dp_qmpphy_out_dp: endpoint@0 { > reg = <0>; > > data-lanes = <0 1>; > remote-endpoint = <&hdmi_bridge_in>; > }; > > /* RX0/TX0 is statically connected to an USB-A Connector */ > usb_dp_qmpphy_out_usb: endpoint@1 { > reg = <1>; > > data-lanes = <2 3>; > remote-endpoint = <&usb3_con_ss_in>; > }; > > But I just found out while reviewed my patchset is wrong... it should be: > > + endpoint@0: > + $ref: /schemas/graph.yaml#/$defs/endpoint-base > + description: Display Port Output lanes of the PHY when used > with static mapping > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 2 > + maxItems: 4 > + oneOf: > + - items: # DisplayPort 2 lanes, normal orientation > + - const: 3 > + - const: 2 > + - items: # DisplayPort 2 lanes, flipped orientation > + - const: 0 > + - const: 1 > + - items: # DisplayPort 4 lanes, normal orientation > + - const: 0 > + - const: 1 > + - const: 2 > + - const: 3 > + - items: # DisplayPort 4 lanes, flipped orientation > + - const: 3 > + - const: 2 > + - const: 1 > + - const: 0 > > and in driver: > +static const u32 dp_2_data_lanes_mapping[][2] = { > + [TYPEC_ORIENTATION_NORMAL] = { 3, 2 }, > + [TYPEC_ORIENTATION_REVERSE] = { 0, 1 }, > > Neil The driver change in the WIP patchset assumes endpoint@0 to be USB, I forgot to mention that. Either the driver or the binding needs to be fixed indeed. And I think there's another mistake in the driver: --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -4221,7 +4221,7 @@ static int qmp_combo_probe(struct platform_device *pdev) if (!memcmp(data_lanes, usb3_data_lane_mapping[i], sizeof(u32) * 2)) break; - if (i >= TYPEC_ORIENTATION_REVERSE) + if (i > TYPEC_ORIENTATION_REVERSE) /* Property value is invalid, ignore property */ goto usb3_mapping_done; @@ -4265,7 +4265,7 @@ static int qmp_combo_probe(struct platform_device *pdev) break; } - if (i >= TYPEC_ORIENTATION_REVERSE) + if (i > TYPEC_ORIENTATION_REVERSE) /* Property value is invalid, ignore property */ goto dp_mapping_done; After fixing this, the driver works properly with my DT at least. > > + }; >> + }; >> +}; >> + >> &usb_2 { >> dr_mode = "host"; >> @@ -986,6 +1134,10 @@ &venus { >> }; >> /* PINCTRL - additions to nodes defined in sc7280.dtsi */ >> +&dp_hot_plug_det { >> + bias-disable; >> +}; >> + >> &pcie0_clkreq_n { >> bias-pull-up; >> drive-strength = <2>; >> > > -- Best regards, Xilin Wu <sophon@radxa.com> ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports 2025-09-15 7:04 ` Xilin Wu @ 2025-09-15 7:51 ` Neil Armstrong 0 siblings, 0 replies; 25+ messages in thread From: Neil Armstrong @ 2025-09-15 7:51 UTC (permalink / raw) To: Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Viken Dadhaniya, Ram Kumar Dwivedi On 15/09/2025 09:04, Xilin Wu wrote: > On 9/15/2025 2:51 PM, Neil Armstrong wrote: >> On 14/09/2025 17:57, Xilin Wu wrote: >>> This board doesn't feature a regular Type-C port. The usb_1_qmpphy's >>> RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0 >>> pair is connected to the RA620 DP-to-HDMI bridge. >>> >>> Add and enable the nodes for the features to work. >>> >>> Signed-off-by: Xilin Wu <sophon@radxa.com> >>> >>> --- >>> >>> This change depends on the following patch series: >>> https://lore.kernel.org/all/20250908-topic-x1e80100-hdmi-v3-4- c53b0f2bc2fb@linaro.org/ >>> --- >>> .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 152 +++++++++++ ++++++++++ >>> 1 file changed, 152 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/ arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >>> index 3bf85d68c97891db1f1f0b84fb5649803948e06f..12bc9a0fcfbfeaabf6ede351f96c61193a8261c0 100644 >>> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >>> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >>> @@ -78,6 +78,71 @@ chosen { >>> stdout-path = "serial0:115200n8"; >>> }; >>> + usb3_con: connector { >>> + compatible = "usb-a-connector"; >>> + >>> + ports { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + port@0 { >>> + reg = <0>; >>> + >>> + usb3_con_hs_in: endpoint { >>> + remote-endpoint = <&usb_1_dwc3_hs>; >>> + }; >>> + }; >>> + >>> + port@1 { >>> + reg = <1>; >>> + >>> + usb3_con_ss_in: endpoint { >>> + remote-endpoint = <&usb_dp_qmpphy_out_usb>; >>> + }; >>> + }; >>> + }; >>> + }; >>> + >>> + hdmi-bridge { >>> + compatible = "radxa,ra620"; >>> + >>> + pinctrl-0 = <&dp_hot_plug_det>; >>> + pinctrl-names = "default"; >>> + >>> + ports { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + port@0 { >>> + reg = <0>; >>> + >>> + hdmi_bridge_in: endpoint { >>> + remote-endpoint = <&usb_dp_qmpphy_out_dp>; >>> + }; >>> + }; >>> + >>> + port@1 { >>> + reg = <1>; >>> + >>> + hdmi_bridge_out: endpoint { >>> + remote-endpoint = <&hdmi_connector_in>; >>> + }; >>> + }; >>> + }; >>> + }; >>> + >>> + hdmi-connector { >>> + compatible = "hdmi-connector"; >>> + label = "hdmi"; >>> + type = "a"; >>> + >>> + port { >>> + hdmi_connector_in: endpoint { >>> + remote-endpoint = <&hdmi_bridge_out>; >>> + }; >>> + }; >>> + }; >>> + >>> leds { >>> compatible = "gpio-leds"; >>> @@ -504,6 +569,21 @@ &lpass_va_macro { >>> status = "okay"; >>> }; >>> +&mdss { >>> + status = "okay"; >>> +}; >>> + >>> +&mdss_dp { >>> + sound-name-prefix = "Display Port0"; >>> + >>> + status = "okay"; >>> +}; >>> + >>> +&mdss_dp_out { >>> + data-lanes = <0 1>; >>> + remote-endpoint = <&usb_dp_qmpphy_dp_in>; >>> +}; >>> + >>> &pcie0 { >>> perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; >>> wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; >>> @@ -753,6 +833,22 @@ platform { >>> sound-dai = <&q6apm>; >>> }; >>> }; >>> + >>> + dp0-dai-link { >>> + link-name = "DP0 Playback"; >>> + >>> + codec { >>> + sound-dai = <&mdss_dp>; >>> + }; >>> + >>> + cpu { >>> + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; >>> + }; >>> + >>> + platform { >>> + sound-dai = <&q6apm>; >>> + }; >>> + }; >>> }; >>> /* Pin 11, 29, 31, 32 in GPIO header */ >>> @@ -967,6 +1063,58 @@ &ufs_mem_phy { >>> status = "okay"; >>> }; >>> +&usb_1 { >>> + dr_mode = "host"; >>> + >>> + status = "okay"; >>> +}; >>> + >>> +&usb_1_dwc3_hs { >>> + remote-endpoint = <&usb3_con_hs_in>; >>> +}; >>> + >>> +&usb_1_hsphy { >>> + vdda-pll-supply = <&vreg_l10c_0p88>; >>> + vdda33-supply = <&vreg_l2b_3p072>; >>> + vdda18-supply = <&vreg_l1c_1p8>; >>> + >>> + status = "okay"; >>> +}; >>> + >>> +&usb_1_qmpphy { >>> + vdda-phy-supply = <&vreg_l6b_1p2>; >>> + vdda-pll-supply = <&vreg_l1b_0p912>; >>> + >>> + /delete-property/ orientation-switch; >>> + >>> + status = "okay"; >>> + >>> + ports { >>> + port@0 { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + /delete-node/ endpoint; >>> + >>> + /* RX1/TX1 is statically connected to USB-A port */ >>> + usb_dp_qmpphy_out_usb: endpoint@0 { >>> + reg = <0>; >>> + >>> + data-lanes = <2 3>; >>> + remote-endpoint = <&usb3_con_ss_in>; >>> + }; >>> + >>> + /* RX0/TX0 is statically connected to RA620 bridge */ >>> + usb_dp_qmpphy_out_dp: endpoint@1 { >>> + reg = <1>; >>> + >>> + data-lanes = <3 2>; >>> + remote-endpoint = <&hdmi_bridge_in>; >>> + }; >> >> In this WiP patchset endpoint@0 is suposed to be DisplayPort, and endpoint@1 for USB3 lanes. >> >> And you must not have colliding data-lanes, so it should be something like: >> >> /* DP0/DP1 is statically connected to a RA620 bridge*/ >> usb_dp_qmpphy_out_dp: endpoint@0 { >> reg = <0>; >> >> data-lanes = <0 1>; >> remote-endpoint = <&hdmi_bridge_in>; >> }; >> >> /* RX0/TX0 is statically connected to an USB-A Connector */ >> usb_dp_qmpphy_out_usb: endpoint@1 { >> reg = <1>; >> >> data-lanes = <2 3>; >> remote-endpoint = <&usb3_con_ss_in>; >> }; >> >> But I just found out while reviewed my patchset is wrong... it should be: >> >> + endpoint@0: >> + $ref: /schemas/graph.yaml#/$defs/endpoint-base >> + description: Display Port Output lanes of the PHY when used with static mapping >> + unevaluatedProperties: false >> + >> + properties: >> + data-lanes: >> + $ref: /schemas/types.yaml#/definitions/uint32-array >> + minItems: 2 >> + maxItems: 4 >> + oneOf: >> + - items: # DisplayPort 2 lanes, normal orientation >> + - const: 3 >> + - const: 2 >> + - items: # DisplayPort 2 lanes, flipped orientation >> + - const: 0 >> + - const: 1 >> + - items: # DisplayPort 4 lanes, normal orientation >> + - const: 0 >> + - const: 1 >> + - const: 2 >> + - const: 3 >> + - items: # DisplayPort 4 lanes, flipped orientation >> + - const: 3 >> + - const: 2 >> + - const: 1 >> + - const: 0 >> >> and in driver: >> +static const u32 dp_2_data_lanes_mapping[][2] = { >> + [TYPEC_ORIENTATION_NORMAL] = { 3, 2 }, >> + [TYPEC_ORIENTATION_REVERSE] = { 0, 1 }, >> >> Neil > > The driver change in the WIP patchset assumes endpoint@0 to be USB, I forgot to mention that. Either the driver or the binding needs to be fixed indeed. Damn you're right, another thing to fix. > > And I think there's another mistake in the driver: > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c > @@ -4221,7 +4221,7 @@ static int qmp_combo_probe(struct platform_device *pdev) > if (!memcmp(data_lanes, usb3_data_lane_mapping[i], sizeof(u32) * 2)) > break; > > - if (i >= TYPEC_ORIENTATION_REVERSE) > + if (i > TYPEC_ORIENTATION_REVERSE) > /* Property value is invalid, ignore property */ > goto usb3_mapping_done; > > @@ -4265,7 +4265,7 @@ static int qmp_combo_probe(struct platform_device *pdev) > break; > } > > - if (i >= TYPEC_ORIENTATION_REVERSE) > + if (i > TYPEC_ORIENTATION_REVERSE) > /* Property value is invalid, ignore property */ > goto dp_mapping_done; > > > After fixing this, the driver works properly with my DT at least. Ack, thanks for the feedback, I'll post a new version ASAP with all fixed. Neil > >> >> + }; >>> + }; >>> +}; >>> + >>> &usb_2 { >>> dr_mode = "host"; >>> @@ -986,6 +1134,10 @@ &venus { >>> }; >>> /* PINCTRL - additions to nodes defined in sc7280.dtsi */ >>> +&dp_hot_plug_det { >>> + bias-disable; >>> +}; >>> + >>> &pcie0_clkreq_n { >>> bias-pull-up; >>> drive-strength = <2>; >>> >> >> > ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports 2025-09-14 15:57 ` [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports Xilin Wu 2025-09-14 17:37 ` Krzysztof Kozlowski 2025-09-15 6:51 ` Neil Armstrong @ 2025-09-15 7:27 ` Konrad Dybcio 2025-09-15 7:42 ` Xilin Wu 2 siblings, 1 reply; 25+ messages in thread From: Konrad Dybcio @ 2025-09-15 7:27 UTC (permalink / raw) To: Xilin Wu, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 9/14/25 5:57 PM, Xilin Wu wrote: > This board doesn't feature a regular Type-C port. The usb_1_qmpphy's > RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0 > pair is connected to the RA620 DP-to-HDMI bridge. > > Add and enable the nodes for the features to work. > > Signed-off-by: Xilin Wu <sophon@radxa.com> > > --- > > This change depends on the following patch series: > https://lore.kernel.org/all/20250908-topic-x1e80100-hdmi-v3-4-c53b0f2bc2fb@linaro.org/ > --- > .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 152 +++++++++++++++++++++ > 1 file changed, 152 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > index 3bf85d68c97891db1f1f0b84fb5649803948e06f..12bc9a0fcfbfeaabf6ede351f96c61193a8261c0 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts > @@ -78,6 +78,71 @@ chosen { > stdout-path = "serial0:115200n8"; > }; > > + usb3_con: connector { > + compatible = "usb-a-connector"; Looking at https://docs.radxa.com/en/dragon/q6a, I see two of these. I suppose there's a (dumb) hub inbetween - check sdm850-lenovo-yoga-c630 for reference if that's the case Konrad ^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports 2025-09-15 7:27 ` Konrad Dybcio @ 2025-09-15 7:42 ` Xilin Wu 0 siblings, 0 replies; 25+ messages in thread From: Xilin Wu @ 2025-09-15 7:42 UTC (permalink / raw) To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Viken Dadhaniya, Ram Kumar Dwivedi On 9/15/2025 3:27 PM, Konrad Dybcio wrote: > On 9/14/25 5:57 PM, Xilin Wu wrote: >> This board doesn't feature a regular Type-C port. The usb_1_qmpphy's >> RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0 >> pair is connected to the RA620 DP-to-HDMI bridge. >> >> Add and enable the nodes for the features to work. >> >> Signed-off-by: Xilin Wu <sophon@radxa.com> >> >> --- >> >> This change depends on the following patch series: >> https://lore.kernel.org/all/20250908-topic-x1e80100-hdmi-v3-4-c53b0f2bc2fb@linaro.org/ >> --- >> .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 152 +++++++++++++++++++++ >> 1 file changed, 152 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >> index 3bf85d68c97891db1f1f0b84fb5649803948e06f..12bc9a0fcfbfeaabf6ede351f96c61193a8261c0 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts >> @@ -78,6 +78,71 @@ chosen { >> stdout-path = "serial0:115200n8"; >> }; >> >> + usb3_con: connector { >> + compatible = "usb-a-connector"; > > Looking at https://docs.radxa.com/en/dragon/q6a, I see two of these. > > I suppose there's a (dumb) hub inbetween - check sdm850-lenovo-yoga-c630 > for reference if that's the case > > Konrad > There are actually four USB-A ports, but only one of them is USB 3.0, and is directly connected to the SoC. The other three USB 2.0 ports are connected to an always-on USB hub, which is then connected to the second USB controller. -- Best regards, Xilin Wu <sophon@radxa.com> ^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2025-11-03 13:06 UTC | newest] Thread overview: 25+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-09-14 15:57 [PATCH v2 0/5] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A Xilin Wu 2025-09-14 15:57 ` [PATCH v2 1/5] dt-bindings: arm: qcom: Add " Xilin Wu 2025-09-14 15:57 ` [PATCH v2 2/5] arm64: dts: qcom: qcs6490: Introduce " Xilin Wu 2025-09-14 17:39 ` Krzysztof Kozlowski 2025-09-15 1:20 ` Xilin Wu 2025-09-14 15:57 ` [PATCH DNM v2 3/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable all available QUP SEs Xilin Wu 2025-09-14 17:36 ` Krzysztof Kozlowski 2025-09-15 7:13 ` Konrad Dybcio 2025-09-15 7:26 ` Krzysztof Kozlowski 2025-11-03 12:57 ` Konrad Dybcio 2025-11-03 13:04 ` Xilin Wu 2025-11-03 13:06 ` Konrad Dybcio 2025-09-14 15:57 ` [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller Xilin Wu 2025-09-14 17:37 ` Krzysztof Kozlowski 2025-09-15 7:24 ` Konrad Dybcio 2025-09-15 7:34 ` Xilin Wu 2025-10-08 9:53 ` Konrad Dybcio 2025-10-09 2:16 ` Xilin Wu 2025-09-14 15:57 ` [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports Xilin Wu 2025-09-14 17:37 ` Krzysztof Kozlowski 2025-09-15 6:51 ` Neil Armstrong 2025-09-15 7:04 ` Xilin Wu 2025-09-15 7:51 ` Neil Armstrong 2025-09-15 7:27 ` Konrad Dybcio 2025-09-15 7:42 ` Xilin Wu
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