* [PATCH v2 1/4] dt-bindings: display/msm: gpu: Document A612 GPU
2024-12-13 10:35 [PATCH v2 0/4] Devicetree changes for QCS615's GPU Akhil P Oommen
@ 2024-12-13 10:35 ` Akhil P Oommen
2024-12-13 10:35 ` [PATCH v2 2/4] dt-bindings: display/msm/gmu: Document RGMU Akhil P Oommen
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Akhil P Oommen @ 2024-12-13 10:35 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Akhil P Oommen,
20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0,
20241022-qcs615-clock-driver-v4-3-3d716ad0d987,
20240924143958.25-2-quic_rlaggysh,
20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf,
20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624,
20241122074922.28153-1-quic_qqzhou
A612 GPU requires an additional smmu_vote clock. Update the bindings to
reflect this.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
.../devicetree/bindings/display/msm/gpu.yaml | 36 ++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 6ddc72fd85b0..1276331cb262 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -217,6 +217,42 @@ allOf:
required:
- clocks
- clock-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,adreno-612.0
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: core
+ description: GPU Core clock
+ - const: mem_iface
+ description: GPU Memory Interface clock
+ - const: alt_mem_iface
+ description: GPU Alternative Memory Interface clock
+ - const: gmu
+ description: CX GMU clock
+ - const: xo
+ description: GPUCC clocksource clock
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: kgsl_3d0_reg_memory
+ - const: cx_dbgc
+
+ required:
+ - clocks
+ - clock-names
+
else:
if:
properties:
--
2.45.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v2 2/4] dt-bindings: display/msm/gmu: Document RGMU
2024-12-13 10:35 [PATCH v2 0/4] Devicetree changes for QCS615's GPU Akhil P Oommen
2024-12-13 10:35 ` [PATCH v2 1/4] dt-bindings: display/msm: gpu: Document A612 GPU Akhil P Oommen
@ 2024-12-13 10:35 ` Akhil P Oommen
2024-12-13 10:53 ` Konrad Dybcio
2024-12-13 10:35 ` [PATCH v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Akhil P Oommen
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Akhil P Oommen @ 2024-12-13 10:35 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Akhil P Oommen,
20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0,
20241022-qcs615-clock-driver-v4-3-3d716ad0d987,
20240924143958.25-2-quic_rlaggysh,
20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf,
20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624,
20241122074922.28153-1-quic_qqzhou
RGMU a.k.a Reduced Graphics Management Unit is a small state machine
with the sole purpose of providing IFPC support. Compared to GMU, it
doesn't manage GPU clock, voltage scaling, bw voting or any other
functionalities. All it does is detect an idle GPU and toggle the
GDSC switch. So it doesn't require iommu & opp table.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index b1bd372996d5..6889dda7d4be 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -27,6 +27,7 @@ properties:
- pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
- const: qcom,adreno-gmu
- const: qcom,adreno-gmu-wrapper
+ - const: qcom,adreno-rgmu
reg:
minItems: 1
@@ -267,12 +268,14 @@ allOf:
properties:
compatible:
contains:
- const: qcom,adreno-gmu-wrapper
+ enum:
+ - qcom,adreno-gmu-wrapper
+ - qcom,adreno-rgmu
then:
properties:
reg:
items:
- - description: GMU wrapper register space
+ - description: RGMU/GMU wrapper register space
reg-names:
items:
- const: gmu
--
2.45.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 2/4] dt-bindings: display/msm/gmu: Document RGMU
2024-12-13 10:35 ` [PATCH v2 2/4] dt-bindings: display/msm/gmu: Document RGMU Akhil P Oommen
@ 2024-12-13 10:53 ` Konrad Dybcio
2024-12-13 13:37 ` Akhil P Oommen
0 siblings, 1 reply; 10+ messages in thread
From: Konrad Dybcio @ 2024-12-13 10:53 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Dmitry Baryshkov, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0,
20241022-qcs615-clock-driver-v4-3-3d716ad0d987,
20240924143958.25-2-quic_rlaggysh,
20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf,
20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624,
20241122074922.28153-1-quic_qqzhou
On 13.12.2024 11:35 AM, Akhil P Oommen wrote:
> RGMU a.k.a Reduced Graphics Management Unit is a small state machine
> with the sole purpose of providing IFPC support. Compared to GMU, it
> doesn't manage GPU clock, voltage scaling, bw voting or any other
> functionalities. All it does is detect an idle GPU and toggle the
> GDSC switch. So it doesn't require iommu & opp table.
>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
The bindings file exists so that people that are not in the know, can
reference it and learn about the hardware. Please spell out IFPC, as
that's a non-obvious, hw-specific acronym.
Otherwise looks ok
Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/4] dt-bindings: display/msm/gmu: Document RGMU
2024-12-13 10:53 ` Konrad Dybcio
@ 2024-12-13 13:37 ` Akhil P Oommen
0 siblings, 0 replies; 10+ messages in thread
From: Akhil P Oommen @ 2024-12-13 13:37 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0,
20241022-qcs615-clock-driver-v4-3-3d716ad0d987,
20240924143958.25-2-quic_rlaggysh,
20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf,
20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624,
20241122074922.28153-1-quic_qqzhou
On 12/13/2024 4:23 PM, Konrad Dybcio wrote:
> On 13.12.2024 11:35 AM, Akhil P Oommen wrote:
>> RGMU a.k.a Reduced Graphics Management Unit is a small state machine
>> with the sole purpose of providing IFPC support. Compared to GMU, it
>> doesn't manage GPU clock, voltage scaling, bw voting or any other
>> functionalities. All it does is detect an idle GPU and toggle the
>> GDSC switch. So it doesn't require iommu & opp table.
>>
>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
>> ---
>
> The bindings file exists so that people that are not in the know, can
> reference it and learn about the hardware. Please spell out IFPC, as
> that's a non-obvious, hw-specific acronym.
>
> Otherwise looks ok
Ah right. Krzysztof schooled me that a while ago.
Will update.
-Akhil.
>
> Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes
2024-12-13 10:35 [PATCH v2 0/4] Devicetree changes for QCS615's GPU Akhil P Oommen
2024-12-13 10:35 ` [PATCH v2 1/4] dt-bindings: display/msm: gpu: Document A612 GPU Akhil P Oommen
2024-12-13 10:35 ` [PATCH v2 2/4] dt-bindings: display/msm/gmu: Document RGMU Akhil P Oommen
@ 2024-12-13 10:35 ` Akhil P Oommen
2024-12-13 10:57 ` Konrad Dybcio
2024-12-13 10:35 ` [PATCH v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Akhil P Oommen
2024-12-13 11:23 ` [PATCH v2 0/4] Devicetree changes for QCS615's GPU Akhil P Oommen
4 siblings, 1 reply; 10+ messages in thread
From: Akhil P Oommen @ 2024-12-13 10:35 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Akhil P Oommen,
20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0,
20241022-qcs615-clock-driver-v4-3-3d716ad0d987,
20240924143958.25-2-quic_rlaggysh,
20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf,
20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624,
20241122074922.28153-1-quic_qqzhou, Jie Zhang
From: Jie Zhang <quic_jiezh@quicinc.com>
Add gpu and gmu nodes for qcs615 chipset.
Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 88 ++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 8df26efde3fd..dee5d3be4aa3 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -387,6 +387,11 @@ smem_region: smem@86000000 {
no-map;
hwlocks = <&tcsr_mutex 3>;
};
+
+ pil_gpu_mem: pil-gpu@97715000 {
+ reg = <0x0 0x97715000 0x0 0x2000>;
+ no-map;
+ };
};
soc: soc@0 {
@@ -508,6 +513,89 @@ qup_uart0_rx: qup-uart0-rx-state {
};
};
+ gpu: gpu@5000000 {
+ compatible = "qcom,adreno-612.0", "qcom,adreno";
+ reg = <0x0 0x05000000 0x0 0x90000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>;
+ clock-names = "core",
+ "mem_iface",
+ "alt_mem_iface",
+ "gmu",
+ "xo";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+
+ iommus = <&adreno_smmu 0x0 0x401>;
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ qcom,gmu = <&rgmu>;
+
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_zap_shader: zap-shader {
+ memory-region = <&pil_gpu_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-435000000 {
+ opp-hz = /bits/ 64 <435000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <3000000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <3975000>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5287500>;
+ };
+
+ opp-745000000 {
+ opp-hz = /bits/ 64 <745000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ opp-peak-kBps = <6075000>;
+ };
+
+ opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ opp-peak-kBps = <7050000>;
+ };
+ };
+ };
+
+ rgmu: rgmu@506a000 {
+ compatible = "qcom,adreno-rgmu";
+ reg = <0x0 0x0506a000 0x0 0x34000>;
+ reg-names = "gmu";
+ power-domains = <&gpucc CX_GDSC>,
+ <&gpucc GX_GDSC>;
+ power-domain-names = "cx", "gx";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ };
+
gpucc: clock-controller@5090000 {
compatible = "qcom,qcs615-gpucc";
reg = <0 0x5090000 0 0x9000>;
--
2.45.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes
2024-12-13 10:35 ` [PATCH v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Akhil P Oommen
@ 2024-12-13 10:57 ` Konrad Dybcio
0 siblings, 0 replies; 10+ messages in thread
From: Konrad Dybcio @ 2024-12-13 10:57 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Dmitry Baryshkov, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0,
20241022-qcs615-clock-driver-v4-3-3d716ad0d987,
20240924143958.25-2-quic_rlaggysh,
20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf,
20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624,
20241122074922.28153-1-quic_qqzhou, Jie Zhang
On 13.12.2024 11:35 AM, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@quicinc.com>
>
> Add gpu and gmu nodes for qcs615 chipset.
>
> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 88 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 8df26efde3fd..dee5d3be4aa3 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -387,6 +387,11 @@ smem_region: smem@86000000 {
> no-map;
> hwlocks = <&tcsr_mutex 3>;
> };
> +
> + pil_gpu_mem: pil-gpu@97715000 {
> + reg = <0x0 0x97715000 0x0 0x2000>;
> + no-map;
> + };
> };
>
> soc: soc@0 {
> @@ -508,6 +513,89 @@ qup_uart0_rx: qup-uart0-rx-state {
> };
> };
>
> + gpu: gpu@5000000 {
> + compatible = "qcom,adreno-612.0", "qcom,adreno";
> + reg = <0x0 0x05000000 0x0 0x90000>;
> + reg-names = "kgsl_3d0_reg_memory";
> +
> + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>;
> + clock-names = "core",
> + "mem_iface",
> + "alt_mem_iface",
> + "gmu",
> + "xo";
> +
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "gfx-mem";
> +
> + iommus = <&adreno_smmu 0x0 0x401>;
No LPAC context?
> + operating-points-v2 = <&gpu_opp_table>;
> + power-domains = <&rpmhpd RPMHPD_CX>;
> + qcom,gmu = <&rgmu>;
> +
> + #cooling-cells = <2>;
> +
> + status = "disabled";
> +
> + gpu_zap_shader: zap-shader {
> + memory-region = <&pil_gpu_mem>;
> + };
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-435000000 {
> + opp-hz = /bits/ 64 <435000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + opp-peak-kBps = <3000000>;
> + };
I'm also seeing 290 MHz @ LOW_SVS
Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU
2024-12-13 10:35 [PATCH v2 0/4] Devicetree changes for QCS615's GPU Akhil P Oommen
` (2 preceding siblings ...)
2024-12-13 10:35 ` [PATCH v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Akhil P Oommen
@ 2024-12-13 10:35 ` Akhil P Oommen
2024-12-13 10:58 ` Konrad Dybcio
2024-12-13 11:23 ` [PATCH v2 0/4] Devicetree changes for QCS615's GPU Akhil P Oommen
4 siblings, 1 reply; 10+ messages in thread
From: Akhil P Oommen @ 2024-12-13 10:35 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Akhil P Oommen,
20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0,
20241022-qcs615-clock-driver-v4-3-3d716ad0d987,
20240924143958.25-2-quic_rlaggysh,
20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf,
20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624,
20241122074922.28153-1-quic_qqzhou, Jie Zhang
From: Jie Zhang <quic_jiezh@quicinc.com>
Enable GPU for qcs615-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index ee6cab3924a6..860a0db1908c 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -202,6 +202,14 @@ &gcc {
<&sleep_clk>;
};
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/qcs615/a612_zap.mbn";
+};
+
&qupv3_id_0 {
status = "okay";
};
--
2.45.2
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU
2024-12-13 10:35 ` [PATCH v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Akhil P Oommen
@ 2024-12-13 10:58 ` Konrad Dybcio
0 siblings, 0 replies; 10+ messages in thread
From: Konrad Dybcio @ 2024-12-13 10:58 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Dmitry Baryshkov, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0,
20241022-qcs615-clock-driver-v4-3-3d716ad0d987,
20240924143958.25-2-quic_rlaggysh,
20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf,
20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624,
20241122074922.28153-1-quic_qqzhou, Jie Zhang
On 13.12.2024 11:35 AM, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@quicinc.com>
>
> Enable GPU for qcs615-ride platform and provide path for zap
> shader.
>
> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/4] Devicetree changes for QCS615's GPU
2024-12-13 10:35 [PATCH v2 0/4] Devicetree changes for QCS615's GPU Akhil P Oommen
` (3 preceding siblings ...)
2024-12-13 10:35 ` [PATCH v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Akhil P Oommen
@ 2024-12-13 11:23 ` Akhil P Oommen
4 siblings, 0 replies; 10+ messages in thread
From: Akhil P Oommen @ 2024-12-13 11:23 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0,
20241022-qcs615-clock-driver-v4-3-3d716ad0d987,
20240924143958.25-2-quic_rlaggysh,
20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf,
20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624,
20241122074922.28153-1-quic_qqzhou, Jie Zhang
On 12/13/2024 4:05 PM, Akhil P Oommen wrote:
> This series adds support for Adreno 612 to QCS615 chipset's devicetree.
> DRM driver's support was posted earlier and can be found here:
> https://patchwork.freedesktop.org/patch/626066/
>
> Patch#1 & #2 are for Rob Clark and the other 2 for Bjorn
>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
> Changes in v2:
> - Completely describe RGMU in devicetree and also add necessary binding
> documentation (Konrad, feedback on the driver patch)
> - Remove smmu_vote clk from clock list (Konrad)
> - Add R-b from Dmitry
> - Link to v1: https://lore.kernel.org/r/20241126-qcs615-gpu-dt-v1-0-a87782976dad@quicinc.com
>
> ---
> Akhil P Oommen (2):
> dt-bindings: display/msm: gpu: Document A612 GPU
> dt-bindings: display/msm/gmu: Document RGMU
>
> Jie Zhang (2):
> arm64: dts: qcom: qcs615: Add gpu and gmu nodes
> arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU
>
> .../devicetree/bindings/display/msm/gmu.yaml | 7 +-
> .../devicetree/bindings/display/msm/gpu.yaml | 36 +++++++++
> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 88 ++++++++++++++++++++++
> 4 files changed, 137 insertions(+), 2 deletions(-)
> ---
> base-commit: 30eb6f0b08b13fd25ea12a3a6fa0a85915190c1c
> change-id: 20241125-qcs615-gpu-dt-facbd8ac318f
> prerequisite-message-id: <20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0@quicinc.com>
> prerequisite-patch-id: 82481c82a20345548e2cb292d3098ed51843b809
> prerequisite-patch-id: fc1cfec4ecd56e669c161c4d2c3797fc0abff0ae
> prerequisite-patch-id: 04ca722967256efddc402b7bab94136a5174b0b9
> prerequisite-patch-id: 3bd8edd83297815fcb1b81fcd891d3c14908442f
> prerequisite-patch-id: 09782474af7eecf1013425fd34f9d2f082fb3616
> prerequisite-message-id: <20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com>
> prerequisite-patch-id: a57054b890d767b45cca87e71b4a0f6bf6914c2f
> prerequisite-patch-id: 07f2c7378c7bbd560f26b61785b6814270647f1b
> prerequisite-patch-id: cd9fc0a399ab430e293764d0911a38109664ca91
> prerequisite-patch-id: 5a8e9ea15a2c3d60b4dbdf11b4e2695742d6333c
> prerequisite-message-id: <20240924143958.25-2-quic_rlaggysh@quicinc.com>
> prerequisite-patch-id: 0e224a7310d36e9a633d57c4a177ff24c1e8e767
> prerequisite-patch-id: 3c73bafb074ea339d387a6aa39e5362c8775596d
> prerequisite-message-id: <20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf@quicinc.com>
> prerequisite-patch-id: df8e2fdd997cbf6c0a107f1871ed9e2caaa97582
> prerequisite-patch-id: b3cc42570d5826a4704f7702e7b26af9a0fe57b0
> prerequisite-patch-id: 125bb8cb367109ba22cededf6e78754579e1ed03
> prerequisite-patch-id: 8e2e841401fefbd96d78dd4a7c47514058c83bf2
> prerequisite-patch-id: 807019bedabd47c04f7ac78e9461d0b5a6e9131b
> prerequisite-patch-id: 13b0dbf97ac1865d241791afb4b46a28ca499523
> prerequisite-patch-id: 40b79fe0b9101f5db3bddad23551c1123572aee5
> prerequisite-patch-id: cb93e5798f6bfe8cc3044c4ce973e3ae5f20dc6b
> prerequisite-patch-id: da2b7a74f1afd58833c6a9a4544a0e271720641f
> prerequisite-patch-id: 72a894a3b19fdbd431e1cec9397365bc5b27abfe
> prerequisite-patch-id: 748a4e51bbedae9c6ebdbd642b2fd1badf958788
> prerequisite-message-id: <20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624@quicinc.com>
> prerequisite-patch-id: 8844a4661902eb44406639a3b7344416a0c88ed9
> prerequisite-patch-id: bcb1328b70868bb9c87c0e4c48e5c9d38853bc60
> prerequisite-message-id: <20241122074922.28153-1-quic_qqzhou@quicinc.com>
> prerequisite-patch-id: c71c7897d6f250b381f7a9ac66ec58f4a10d49d6
> prerequisite-patch-id: 50223f2370a7ae8053b164fa5219a1690d7e4567
>
> Best regards,
A bad version of B4 tool CC'ed a few bogus email addresses. I will
resend this series after fixing that.
-Akhil.
^ permalink raw reply [flat|nested] 10+ messages in thread