[PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[Pratyush Brahma]

Add the device node for gfx smmu that is required for gpu
specific address translations.

This patch depends on the patch series [1] posted by Imran Shaik
adding the clock support for gpu.

[1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/

Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 80226992a65d..8eb688e2df0a 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -816,6 +816,43 @@
 			#power-domain-cells = <1>;
 		};
 
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
+				   "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x3da0000 0x0 0x20000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+			dma-coherent;
+
+			power-domains = <&gpucc GPU_CC_CX_GDSC>;
+			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+				 <&gpucc GPU_CC_AHB_CLK>,
+				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+				 <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+				 <&gpucc GPU_CC_HUB_AON_CLK>;
+			clock-names = "gcc_gpu_memnoc_gfx_clk",
+				      "gcc_gpu_snoc_dvm_gfx_clk",
+				      "gpu_cc_ahb_clk",
+				      "gpu_cc_hlos1_vote_gpu_smmu_clk",
+				      "gpu_cc_cx_gmu_clk",
+				      "gpu_cc_hub_cx_int_clk",
+				      "gpu_cc_hub_aon_clk";
+			interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		pmu@9091000 {
 			compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
 			reg = <0x0 0x9091000 0x0 0x1000>;
-- 
2.17.1

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[Bjorn Andersson]

On Fri, Dec 27, 2024 at 04:30:24PM +0530, Pratyush Brahma wrote:
> Add the device node for gfx smmu that is required for gpu
> specific address translations.
> 
> This patch depends on the patch series [1] posted by Imran Shaik
> adding the clock support for gpu.
> 
> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/

It's over a month since Konrad rejected that patch so you're just
wasting out time sending this to the list.

Further, this dependency has no value in the git history, and as such it
should not be mentioned in the commit message, but rather under the
'---' line.

Lastly, you sent this same patch both as part of a series and then
alone, within 2 minutes. go/upstream has instructions on how to use b4
instead of making these manual mistakes.


PS. Just to be clear, either make sure this patch is sent together with
the next version of [1], or wait for that to have become available in
linux-next before resubmitting it.

Regards,
Bjorn

> 
> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index 80226992a65d..8eb688e2df0a 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -816,6 +816,43 @@
>  			#power-domain-cells = <1>;
>  		};
>  
> +		adreno_smmu: iommu@3da0000 {
> +			compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
> +				   "qcom,smmu-500", "arm,mmu-500";
> +			reg = <0x0 0x3da0000 0x0 0x20000>;
> +			#iommu-cells = <2>;
> +			#global-interrupts = <2>;
> +			dma-coherent;
> +
> +			power-domains = <&gpucc GPU_CC_CX_GDSC>;
> +			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> +				 <&gpucc GPU_CC_AHB_CLK>,
> +				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
> +				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> +				 <&gpucc GPU_CC_HUB_AON_CLK>;
> +			clock-names = "gcc_gpu_memnoc_gfx_clk",
> +				      "gcc_gpu_snoc_dvm_gfx_clk",
> +				      "gpu_cc_ahb_clk",
> +				      "gpu_cc_hlos1_vote_gpu_smmu_clk",
> +				      "gpu_cc_cx_gmu_clk",
> +				      "gpu_cc_hub_cx_int_clk",
> +				      "gpu_cc_hub_aon_clk";
> +			interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>  		pmu@9091000 {
>  			compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
>  			reg = <0x0 0x9091000 0x0 0x1000>;
> -- 
> 2.17.1
> 

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[Konrad Dybcio]

On 27.12.2024 12:00 PM, Pratyush Brahma wrote:
> Add the device node for gfx smmu that is required for gpu
> specific address translations.
> 
> This patch depends on the patch series [1] posted by Imran Shaik
> adding the clock support for gpu.
> 
> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/
> 
> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index 80226992a65d..8eb688e2df0a 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -816,6 +816,43 @@
>  			#power-domain-cells = <1>;
>  		};
>  
> +		adreno_smmu: iommu@3da0000 {
> +			compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
> +				   "qcom,smmu-500", "arm,mmu-500";
> +			reg = <0x0 0x3da0000 0x0 0x20000>;
> +			#iommu-cells = <2>;
> +			#global-interrupts = <2>;
> +			dma-coherent;
> +
> +			power-domains = <&gpucc GPU_CC_CX_GDSC>;
> +			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> +				 <&gpucc GPU_CC_AHB_CLK>,
> +				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
> +				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> +				 <&gpucc GPU_CC_HUB_AON_CLK>;
> +			clock-names = "gcc_gpu_memnoc_gfx_clk",
> +				      "gcc_gpu_snoc_dvm_gfx_clk",
> +				      "gpu_cc_ahb_clk",
> +				      "gpu_cc_hlos1_vote_gpu_smmu_clk",
> +				      "gpu_cc_cx_gmu_clk",
> +				      "gpu_cc_hub_cx_int_clk",
> +				      "gpu_cc_hub_aon_clk";

Most of these entries look totally bogus, please make sure you only
reference the ones actually required

Konrad

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[Pratyush Brahma]

On 12/30/2024 6:49 PM, Konrad Dybcio wrote:
> On 27.12.2024 12:00 PM, Pratyush Brahma wrote:
>> Add the device node for gfx smmu that is required for gpu
>> specific address translations.
>>
>> This patch depends on the patch series [1] posted by Imran Shaik
>> adding the clock support for gpu.
>>
>> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/
>>
>> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
>>   1 file changed, 37 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> index 80226992a65d..8eb688e2df0a 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> @@ -816,6 +816,43 @@
>>   			#power-domain-cells = <1>;
>>   		};
>>   
>> +		adreno_smmu: iommu@3da0000 {
>> +			compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
>> +				   "qcom,smmu-500", "arm,mmu-500";
>> +			reg = <0x0 0x3da0000 0x0 0x20000>;
>> +			#iommu-cells = <2>;
>> +			#global-interrupts = <2>;
>> +			dma-coherent;
>> +
>> +			power-domains = <&gpucc GPU_CC_CX_GDSC>;
>> +			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>> +				 <&gpucc GPU_CC_AHB_CLK>,
>> +				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
>> +				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>> +				 <&gpucc GPU_CC_HUB_AON_CLK>;
>> +			clock-names = "gcc_gpu_memnoc_gfx_clk",
>> +				      "gcc_gpu_snoc_dvm_gfx_clk",
>> +				      "gpu_cc_ahb_clk",
>> +				      "gpu_cc_hlos1_vote_gpu_smmu_clk",
>> +				      "gpu_cc_cx_gmu_clk",
>> +				      "gpu_cc_hub_cx_int_clk",
>> +				      "gpu_cc_hub_aon_clk";
> Most of these entries look totally bogus, please make sure you only
> reference the ones actually required
These entries are exactly similar to the ones we use in sa8775p as well 
[1] and the usecases
haven't changed between qcs8300 and sa8775p.

Can you please let me know which entries you find irrelevant here?

[1] commit 1a1ff00c1626c "arm64: dts: qcom: sa8775p: add the GPU IOMMU node"

>
> Konrad

-- 
Thanks and Regards
Pratyush Brahma

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[Pratyush Brahma]

On 12/28/2024 9:05 AM, Bjorn Andersson wrote:
> On Fri, Dec 27, 2024 at 04:30:24PM +0530, Pratyush Brahma wrote:
>> Add the device node for gfx smmu that is required for gpu
>> specific address translations.
>>
>> This patch depends on the patch series [1] posted by Imran Shaik
>> adding the clock support for gpu.
>>
>> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/
> It's over a month since Konrad rejected that patch so you're just
> wasting out time sending this to the list.
>
> Further, this dependency has no value in the git history, and as such it
> should not be mentioned in the commit message, but rather under the
> '---' line.
>
> Lastly, you sent this same patch both as part of a series and then
> alone, within 2 minutes. go/upstream has instructions on how to use b4
> instead of making these manual mistakes.
>
>
> PS. Just to be clear, either make sure this patch is sent together with
> the next version of [1], or wait for that to have become available in
> linux-next before resubmitting it.
I see the patch [1] has been merged now [2]. Will resend another version 
of this on top of
the merged commit using b4.

[2] 
https://lore.kernel.org/all/173631205044.113795.272368168541784140.b4-ty@kernel.org/

>
> Regards,
> Bjorn
>
>> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
>>   1 file changed, 37 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> index 80226992a65d..8eb688e2df0a 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>> @@ -816,6 +816,43 @@
>>   			#power-domain-cells = <1>;
>>   		};
>>   
>> +		adreno_smmu: iommu@3da0000 {
>> +			compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
>> +				   "qcom,smmu-500", "arm,mmu-500";
>> +			reg = <0x0 0x3da0000 0x0 0x20000>;
>> +			#iommu-cells = <2>;
>> +			#global-interrupts = <2>;
>> +			dma-coherent;
>> +
>> +			power-domains = <&gpucc GPU_CC_CX_GDSC>;
>> +			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>> +				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>> +				 <&gpucc GPU_CC_AHB_CLK>,
>> +				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>> +				 <&gpucc GPU_CC_CX_GMU_CLK>,
>> +				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>> +				 <&gpucc GPU_CC_HUB_AON_CLK>;
>> +			clock-names = "gcc_gpu_memnoc_gfx_clk",
>> +				      "gcc_gpu_snoc_dvm_gfx_clk",
>> +				      "gpu_cc_ahb_clk",
>> +				      "gpu_cc_hlos1_vote_gpu_smmu_clk",
>> +				      "gpu_cc_cx_gmu_clk",
>> +				      "gpu_cc_hub_cx_int_clk",
>> +				      "gpu_cc_hub_aon_clk";
>> +			interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
>> +
>>   		pmu@9091000 {
>>   			compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
>>   			reg = <0x0 0x9091000 0x0 0x1000>;
>> -- 
>> 2.17.1
>>
-- 
Thanks and Regards
Pratyush Brahma

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[Konrad Dybcio]

On 8.01.2025 1:10 PM, Pratyush Brahma wrote:
> 
> On 12/30/2024 6:49 PM, Konrad Dybcio wrote:
>> On 27.12.2024 12:00 PM, Pratyush Brahma wrote:
>>> Add the device node for gfx smmu that is required for gpu
>>> specific address translations.
>>>
>>> This patch depends on the patch series [1] posted by Imran Shaik
>>> adding the clock support for gpu.
>>>
>>> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/
>>>
>>> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
>>>   1 file changed, 37 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>> index 80226992a65d..8eb688e2df0a 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>> @@ -816,6 +816,43 @@
>>>               #power-domain-cells = <1>;
>>>           };
>>>   +        adreno_smmu: iommu@3da0000 {
>>> +            compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
>>> +                   "qcom,smmu-500", "arm,mmu-500";
>>> +            reg = <0x0 0x3da0000 0x0 0x20000>;
>>> +            #iommu-cells = <2>;
>>> +            #global-interrupts = <2>;
>>> +            dma-coherent;
>>> +
>>> +            power-domains = <&gpucc GPU_CC_CX_GDSC>;
>>> +            clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>> +                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>>> +                 <&gpucc GPU_CC_AHB_CLK>,
>>> +                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>>> +                 <&gpucc GPU_CC_CX_GMU_CLK>,
>>> +                 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>>> +                 <&gpucc GPU_CC_HUB_AON_CLK>;
>>> +            clock-names = "gcc_gpu_memnoc_gfx_clk",
>>> +                      "gcc_gpu_snoc_dvm_gfx_clk",
>>> +                      "gpu_cc_ahb_clk",
>>> +                      "gpu_cc_hlos1_vote_gpu_smmu_clk",
>>> +                      "gpu_cc_cx_gmu_clk",
>>> +                      "gpu_cc_hub_cx_int_clk",
>>> +                      "gpu_cc_hub_aon_clk";
>> Most of these entries look totally bogus, please make sure you only
>> reference the ones actually required
> These entries are exactly similar to the ones we use in sa8775p as well [1] and the usecases
> haven't changed between qcs8300 and sa8775p.
> 
> Can you please let me know which entries you find irrelevant here?

Well, I'm particularly unsure about CX_GMU and the HUB clocks.
I >>don't think<< they don't have much to do with the SMMU, but please
check internally with someone who knows for sure

Konrad

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[Pratyush Brahma]

On 1/9/2025 8:56 PM, Konrad Dybcio wrote:
> On 8.01.2025 1:10 PM, Pratyush Brahma wrote:
>> On 12/30/2024 6:49 PM, Konrad Dybcio wrote:
>>> On 27.12.2024 12:00 PM, Pratyush Brahma wrote:
>>>> Add the device node for gfx smmu that is required for gpu
>>>> specific address translations.
>>>>
>>>> This patch depends on the patch series [1] posted by Imran Shaik
>>>> adding the clock support for gpu.
>>>>
>>>> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/
>>>>
>>>> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
>>>>    1 file changed, 37 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>> index 80226992a65d..8eb688e2df0a 100644
>>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>> @@ -816,6 +816,43 @@
>>>>                #power-domain-cells = <1>;
>>>>            };
>>>>    +        adreno_smmu: iommu@3da0000 {
>>>> +            compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
>>>> +                   "qcom,smmu-500", "arm,mmu-500";
>>>> +            reg = <0x0 0x3da0000 0x0 0x20000>;
>>>> +            #iommu-cells = <2>;
>>>> +            #global-interrupts = <2>;
>>>> +            dma-coherent;
>>>> +
>>>> +            power-domains = <&gpucc GPU_CC_CX_GDSC>;
>>>> +            clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>>> +                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>>>> +                 <&gpucc GPU_CC_AHB_CLK>,
>>>> +                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>>>> +                 <&gpucc GPU_CC_CX_GMU_CLK>,
>>>> +                 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>>>> +                 <&gpucc GPU_CC_HUB_AON_CLK>;
>>>> +            clock-names = "gcc_gpu_memnoc_gfx_clk",
>>>> +                      "gcc_gpu_snoc_dvm_gfx_clk",
>>>> +                      "gpu_cc_ahb_clk",
>>>> +                      "gpu_cc_hlos1_vote_gpu_smmu_clk",
>>>> +                      "gpu_cc_cx_gmu_clk",
>>>> +                      "gpu_cc_hub_cx_int_clk",
>>>> +                      "gpu_cc_hub_aon_clk";
>>> Most of these entries look totally bogus, please make sure you only
>>> reference the ones actually required
>> These entries are exactly similar to the ones we use in sa8775p as well [1] and the usecases
>> haven't changed between qcs8300 and sa8775p.
>>
>> Can you please let me know which entries you find irrelevant here?
> Well, I'm particularly unsure about CX_GMU and the HUB clocks.
> I >>don't think<< they don't have much to do with the SMMU, but please
> check internally with someone who knows for sure
I checked internally and found that these clocks are required for gpu 
smmu operations
as we don't use interconnect voting mechanism here as we do downstream. 
Hence the
list of clocks is same across all targets using gpu smmu as described in 
[1] previously.
> Konrad

-- 
Thanks and Regards
Pratyush Brahma

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[Konrad Dybcio]

On 28.01.2025 11:02 AM, Pratyush Brahma wrote:
> 
> On 1/9/2025 8:56 PM, Konrad Dybcio wrote:
>> On 8.01.2025 1:10 PM, Pratyush Brahma wrote:
>>> On 12/30/2024 6:49 PM, Konrad Dybcio wrote:
>>>> On 27.12.2024 12:00 PM, Pratyush Brahma wrote:
>>>>> Add the device node for gfx smmu that is required for gpu
>>>>> specific address translations.
>>>>>
>>>>> This patch depends on the patch series [1] posted by Imran Shaik
>>>>> adding the clock support for gpu.
>>>>>
>>>>> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/
>>>>>
>>>>> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
>>>>> ---
>>>>>    arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
>>>>>    1 file changed, 37 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>> index 80226992a65d..8eb688e2df0a 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>> @@ -816,6 +816,43 @@
>>>>>                #power-domain-cells = <1>;
>>>>>            };
>>>>>    +        adreno_smmu: iommu@3da0000 {
>>>>> +            compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
>>>>> +                   "qcom,smmu-500", "arm,mmu-500";
>>>>> +            reg = <0x0 0x3da0000 0x0 0x20000>;
>>>>> +            #iommu-cells = <2>;
>>>>> +            #global-interrupts = <2>;
>>>>> +            dma-coherent;
>>>>> +
>>>>> +            power-domains = <&gpucc GPU_CC_CX_GDSC>;
>>>>> +            clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>>>> +                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>>>>> +                 <&gpucc GPU_CC_AHB_CLK>,
>>>>> +                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>>>>> +                 <&gpucc GPU_CC_CX_GMU_CLK>,
>>>>> +                 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>>>>> +                 <&gpucc GPU_CC_HUB_AON_CLK>;
>>>>> +            clock-names = "gcc_gpu_memnoc_gfx_clk",
>>>>> +                      "gcc_gpu_snoc_dvm_gfx_clk",
>>>>> +                      "gpu_cc_ahb_clk",
>>>>> +                      "gpu_cc_hlos1_vote_gpu_smmu_clk",
>>>>> +                      "gpu_cc_cx_gmu_clk",
>>>>> +                      "gpu_cc_hub_cx_int_clk",
>>>>> +                      "gpu_cc_hub_aon_clk";
>>>> Most of these entries look totally bogus, please make sure you only
>>>> reference the ones actually required
>>> These entries are exactly similar to the ones we use in sa8775p as well [1] and the usecases
>>> haven't changed between qcs8300 and sa8775p.
>>>
>>> Can you please let me know which entries you find irrelevant here?
>> Well, I'm particularly unsure about CX_GMU and the HUB clocks.
>> I >>don't think<< they don't have much to do with the SMMU, but please
>> check internally with someone who knows for sure
> I checked internally and found that these clocks are required for gpu smmu operations
> as we don't use interconnect voting mechanism here as we do downstream. Hence the
> list of clocks is same across all targets using gpu smmu as described in [1] previously.

I managed to dig up some documents too.. It seems you're right, however the order
is supposed to be slightly different:

GPU_CC_CX_GMU_CLK
GPU_CC_HUB_CX_INT_CLK
GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK
GCC_GPU_MEMNOC_GFX_CLK

Unsure if it *actually* matters given we've added them in a random order on a
multitude of platforms and there haven't been any visible adverse effects.

With GPU_CC_AHB not being mentioned but it being quite reasonable to be there
judging by its name. Enabling HLOS1_VOTE normally enables some more clocks (some
known by Linux, some not), but here the docs are rather cryptic on that topic.

I'm not sure about SNoC_DVM on this one as well, but other SoCs require it so
it's probably safe so assume this one does so as well

I've verified the interrupt numbers, so please just alter the property order /
whitespaces / general style of the node to match x1e80100.dtsi and we'll get
this merged

Konrad

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[Pratyush Brahma]

On 1/29/2025 7:56 PM, Konrad Dybcio wrote:
> On 28.01.2025 11:02 AM, Pratyush Brahma wrote:
>> On 1/9/2025 8:56 PM, Konrad Dybcio wrote:
>>> On 8.01.2025 1:10 PM, Pratyush Brahma wrote:
>>>> On 12/30/2024 6:49 PM, Konrad Dybcio wrote:
>>>>> On 27.12.2024 12:00 PM, Pratyush Brahma wrote:
>>>>>> Add the device node for gfx smmu that is required for gpu
>>>>>> specific address translations.
>>>>>>
>>>>>> This patch depends on the patch series [1] posted by Imran Shaik
>>>>>> adding the clock support for gpu.
>>>>>>
>>>>>> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/
>>>>>>
>>>>>> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
>>>>>> ---
>>>>>>     arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
>>>>>>     1 file changed, 37 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>> index 80226992a65d..8eb688e2df0a 100644
>>>>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>> @@ -816,6 +816,43 @@
>>>>>>                 #power-domain-cells = <1>;
>>>>>>             };
>>>>>>     +        adreno_smmu: iommu@3da0000 {
>>>>>> +            compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
>>>>>> +                   "qcom,smmu-500", "arm,mmu-500";
>>>>>> +            reg = <0x0 0x3da0000 0x0 0x20000>;
>>>>>> +            #iommu-cells = <2>;
>>>>>> +            #global-interrupts = <2>;
>>>>>> +            dma-coherent;
>>>>>> +
>>>>>> +            power-domains = <&gpucc GPU_CC_CX_GDSC>;
>>>>>> +            clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>>>>> +                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>>>>>> +                 <&gpucc GPU_CC_AHB_CLK>,
>>>>>> +                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>>>>>> +                 <&gpucc GPU_CC_CX_GMU_CLK>,
>>>>>> +                 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>>>>>> +                 <&gpucc GPU_CC_HUB_AON_CLK>;
>>>>>> +            clock-names = "gcc_gpu_memnoc_gfx_clk",
>>>>>> +                      "gcc_gpu_snoc_dvm_gfx_clk",
>>>>>> +                      "gpu_cc_ahb_clk",
>>>>>> +                      "gpu_cc_hlos1_vote_gpu_smmu_clk",
>>>>>> +                      "gpu_cc_cx_gmu_clk",
>>>>>> +                      "gpu_cc_hub_cx_int_clk",
>>>>>> +                      "gpu_cc_hub_aon_clk";
>>>>> Most of these entries look totally bogus, please make sure you only
>>>>> reference the ones actually required
>>>> These entries are exactly similar to the ones we use in sa8775p as well [1] and the usecases
>>>> haven't changed between qcs8300 and sa8775p.
>>>>
>>>> Can you please let me know which entries you find irrelevant here?
>>> Well, I'm particularly unsure about CX_GMU and the HUB clocks.
>>> I >>don't think<< they don't have much to do with the SMMU, but please
>>> check internally with someone who knows for sure
>> I checked internally and found that these clocks are required for gpu smmu operations
>> as we don't use interconnect voting mechanism here as we do downstream. Hence the
>> list of clocks is same across all targets using gpu smmu as described in [1] previously.
> I managed to dig up some documents too.. It seems you're right, however the order
> is supposed to be slightly different:
>
> GPU_CC_CX_GMU_CLK
> GPU_CC_HUB_CX_INT_CLK
> GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK
> GCC_GPU_MEMNOC_GFX_CLK
>
> Unsure if it *actually* matters given we've added them in a random order on a
> multitude of platforms and there haven't been any visible adverse effects.
Thanks for checking this. We haven't really adhered to this order in
most of our platforms and things have been running fine. So I guess it 
doesn't matter.
However, I'll still send out the next patchset in the order you've 
mentioned. Just so that we
are in consonance, the final order would look like the following. Please 
correct me if you'd
prefer otherwise.

                 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
                                <&gpucc GPU_CC_HUB_CX_INT_CLK>,
                                <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
                                <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
                                <&gpucc GPU_CC_AHB_CLK>,
                                <&gpucc GPU_CC_HUB_AON_CLK>;

>
> With GPU_CC_AHB not being mentioned but it being quite reasonable to be there
> judging by its name. Enabling HLOS1_VOTE normally enables some more clocks (some
> known by Linux, some not), but here the docs are rather cryptic on that topic.
>
> I'm not sure about SNoC_DVM on this one as well, but other SoCs require it so
> it's probably safe so assume this one does so as well
Yes, I have been conservative to include all the clocks that are 
required on other platforms
here as well.
>
> I've verified the interrupt numbers, so please just alter the property order /
> whitespaces / general style of the node to match x1e80100.dtsi and we'll get
> this merged

Sure, will take care of this in the next version.

> Konrad

-- 
Thanks and Regards
Pratyush Brahma

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[Konrad Dybcio]

On 30.01.2025 6:40 AM, Pratyush Brahma wrote:
> 
> On 1/29/2025 7:56 PM, Konrad Dybcio wrote:
>> On 28.01.2025 11:02 AM, Pratyush Brahma wrote:
>>> On 1/9/2025 8:56 PM, Konrad Dybcio wrote:
>>>> On 8.01.2025 1:10 PM, Pratyush Brahma wrote:
>>>>> On 12/30/2024 6:49 PM, Konrad Dybcio wrote:
>>>>>> On 27.12.2024 12:00 PM, Pratyush Brahma wrote:
>>>>>>> Add the device node for gfx smmu that is required for gpu
>>>>>>> specific address translations.
>>>>>>>
>>>>>>> This patch depends on the patch series [1] posted by Imran Shaik
>>>>>>> adding the clock support for gpu.
>>>>>>>
>>>>>>> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/
>>>>>>>
>>>>>>> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
>>>>>>> ---
>>>>>>>     arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
>>>>>>>     1 file changed, 37 insertions(+)
>>>>>>>
>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>>> index 80226992a65d..8eb688e2df0a 100644
>>>>>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>>> @@ -816,6 +816,43 @@
>>>>>>>                 #power-domain-cells = <1>;
>>>>>>>             };
>>>>>>>     +        adreno_smmu: iommu@3da0000 {
>>>>>>> +            compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
>>>>>>> +                   "qcom,smmu-500", "arm,mmu-500";
>>>>>>> +            reg = <0x0 0x3da0000 0x0 0x20000>;
>>>>>>> +            #iommu-cells = <2>;
>>>>>>> +            #global-interrupts = <2>;
>>>>>>> +            dma-coherent;
>>>>>>> +
>>>>>>> +            power-domains = <&gpucc GPU_CC_CX_GDSC>;
>>>>>>> +            clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>>>>>> +                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>>>>>>> +                 <&gpucc GPU_CC_AHB_CLK>,
>>>>>>> +                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>>>>>>> +                 <&gpucc GPU_CC_CX_GMU_CLK>,
>>>>>>> +                 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>>>>>>> +                 <&gpucc GPU_CC_HUB_AON_CLK>;
>>>>>>> +            clock-names = "gcc_gpu_memnoc_gfx_clk",
>>>>>>> +                      "gcc_gpu_snoc_dvm_gfx_clk",
>>>>>>> +                      "gpu_cc_ahb_clk",
>>>>>>> +                      "gpu_cc_hlos1_vote_gpu_smmu_clk",
>>>>>>> +                      "gpu_cc_cx_gmu_clk",
>>>>>>> +                      "gpu_cc_hub_cx_int_clk",
>>>>>>> +                      "gpu_cc_hub_aon_clk";
>>>>>> Most of these entries look totally bogus, please make sure you only
>>>>>> reference the ones actually required
>>>>> These entries are exactly similar to the ones we use in sa8775p as well [1] and the usecases
>>>>> haven't changed between qcs8300 and sa8775p.
>>>>>
>>>>> Can you please let me know which entries you find irrelevant here?
>>>> Well, I'm particularly unsure about CX_GMU and the HUB clocks.
>>>> I >>don't think<< they don't have much to do with the SMMU, but please
>>>> check internally with someone who knows for sure
>>> I checked internally and found that these clocks are required for gpu smmu operations
>>> as we don't use interconnect voting mechanism here as we do downstream. Hence the
>>> list of clocks is same across all targets using gpu smmu as described in [1] previously.
>> I managed to dig up some documents too.. It seems you're right, however the order
>> is supposed to be slightly different:
>>
>> GPU_CC_CX_GMU_CLK
>> GPU_CC_HUB_CX_INT_CLK
>> GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK
>> GCC_GPU_MEMNOC_GFX_CLK
>>
>> Unsure if it *actually* matters given we've added them in a random order on a
>> multitude of platforms and there haven't been any visible adverse effects.
> Thanks for checking this. We haven't really adhered to this order in
> most of our platforms and things have been running fine. So I guess it doesn't matter.
> However, I'll still send out the next patchset in the order you've mentioned. Just so that we
> are in consonance, the final order would look like the following. Please correct me if you'd
> prefer otherwise.
> 
>                 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
>                                <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>                                <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>                                <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>                                <&gpucc GPU_CC_AHB_CLK>,
>                                <&gpucc GPU_CC_HUB_AON_CLK>;

Looks good, please double-check if it works without clk_ignore_unused

Konrad

Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu

[Pratyush Brahma]

On 2/1/2025 9:21 PM, Konrad Dybcio wrote:
> On 30.01.2025 6:40 AM, Pratyush Brahma wrote:
>> On 1/29/2025 7:56 PM, Konrad Dybcio wrote:
>>> On 28.01.2025 11:02 AM, Pratyush Brahma wrote:
>>>> On 1/9/2025 8:56 PM, Konrad Dybcio wrote:
>>>>> On 8.01.2025 1:10 PM, Pratyush Brahma wrote:
>>>>>> On 12/30/2024 6:49 PM, Konrad Dybcio wrote:
>>>>>>> On 27.12.2024 12:00 PM, Pratyush Brahma wrote:
>>>>>>>> Add the device node for gfx smmu that is required for gpu
>>>>>>>> specific address translations.
>>>>>>>>
>>>>>>>> This patch depends on the patch series [1] posted by Imran Shaik
>>>>>>>> adding the clock support for gpu.
>>>>>>>>
>>>>>>>> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/
>>>>>>>>
>>>>>>>> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
>>>>>>>> ---
>>>>>>>>      arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++
>>>>>>>>      1 file changed, 37 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>>>> index 80226992a65d..8eb688e2df0a 100644
>>>>>>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
>>>>>>>> @@ -816,6 +816,43 @@
>>>>>>>>                  #power-domain-cells = <1>;
>>>>>>>>              };
>>>>>>>>      +        adreno_smmu: iommu@3da0000 {
>>>>>>>> +            compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu",
>>>>>>>> +                   "qcom,smmu-500", "arm,mmu-500";
>>>>>>>> +            reg = <0x0 0x3da0000 0x0 0x20000>;
>>>>>>>> +            #iommu-cells = <2>;
>>>>>>>> +            #global-interrupts = <2>;
>>>>>>>> +            dma-coherent;
>>>>>>>> +
>>>>>>>> +            power-domains = <&gpucc GPU_CC_CX_GDSC>;
>>>>>>>> +            clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>>>>>>> +                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>>>>>>>> +                 <&gpucc GPU_CC_AHB_CLK>,
>>>>>>>> +                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>>>>>>>> +                 <&gpucc GPU_CC_CX_GMU_CLK>,
>>>>>>>> +                 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>>>>>>>> +                 <&gpucc GPU_CC_HUB_AON_CLK>;
>>>>>>>> +            clock-names = "gcc_gpu_memnoc_gfx_clk",
>>>>>>>> +                      "gcc_gpu_snoc_dvm_gfx_clk",
>>>>>>>> +                      "gpu_cc_ahb_clk",
>>>>>>>> +                      "gpu_cc_hlos1_vote_gpu_smmu_clk",
>>>>>>>> +                      "gpu_cc_cx_gmu_clk",
>>>>>>>> +                      "gpu_cc_hub_cx_int_clk",
>>>>>>>> +                      "gpu_cc_hub_aon_clk";
>>>>>>> Most of these entries look totally bogus, please make sure you only
>>>>>>> reference the ones actually required
>>>>>> These entries are exactly similar to the ones we use in sa8775p as well [1] and the usecases
>>>>>> haven't changed between qcs8300 and sa8775p.
>>>>>>
>>>>>> Can you please let me know which entries you find irrelevant here?
>>>>> Well, I'm particularly unsure about CX_GMU and the HUB clocks.
>>>>> I >>don't think<< they don't have much to do with the SMMU, but please
>>>>> check internally with someone who knows for sure
>>>> I checked internally and found that these clocks are required for gpu smmu operations
>>>> as we don't use interconnect voting mechanism here as we do downstream. Hence the
>>>> list of clocks is same across all targets using gpu smmu as described in [1] previously.
>>> I managed to dig up some documents too.. It seems you're right, however the order
>>> is supposed to be slightly different:
>>>
>>> GPU_CC_CX_GMU_CLK
>>> GPU_CC_HUB_CX_INT_CLK
>>> GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK
>>> GCC_GPU_MEMNOC_GFX_CLK
>>>
>>> Unsure if it *actually* matters given we've added them in a random order on a
>>> multitude of platforms and there haven't been any visible adverse effects.
>> Thanks for checking this. We haven't really adhered to this order in
>> most of our platforms and things have been running fine. So I guess it doesn't matter.
>> However, I'll still send out the next patchset in the order you've mentioned. Just so that we
>> are in consonance, the final order would look like the following. Please correct me if you'd
>> prefer otherwise.
>>
>>                  clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
>>                                 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
>>                                 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
>>                                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>>                                 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
>>                                 <&gpucc GPU_CC_AHB_CLK>,
>>                                 <&gpucc GPU_CC_HUB_AON_CLK>;
> Looks good, please double-check if it works without clk_ignore_unused
Thanks. Yes, these have been tested without clk_ignore_unused. I will 
send out the next set of patches
with this order.
>
> Konrad

-- 
Thanks and Regards
Pratyush Brahma