* [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers
@ 2022-09-10 6:38 Manivannan Sadhasivam
2022-09-20 6:45 ` Vinod Koul
2022-09-21 13:06 ` Dmitry Baryshkov
0 siblings, 2 replies; 6+ messages in thread
From: Manivannan Sadhasivam @ 2022-09-10 6:38 UTC (permalink / raw)
To: vkoul, andersson
Cc: kishon, linux-arm-msm, linux-phy, linux-kernel,
Manivannan Sadhasivam
In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and
QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2
and QPHY_V5_PCS_EQ_CONFIG3.
This causes high latency when ASPM is enabled, so fix it!
Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 ++--
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 4648467d5cac..b508903d77d0 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1332,8 +1332,8 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
};
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG4, 0x16),
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x22),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
};
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
index 61a44519f969..cca6455ec98c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
@@ -11,7 +11,7 @@
#define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
#define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
-#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
-#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
+#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0
+#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers
2022-09-10 6:38 [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers Manivannan Sadhasivam
@ 2022-09-20 6:45 ` Vinod Koul
2022-09-20 9:29 ` Johan Hovold
2022-09-21 13:06 ` Dmitry Baryshkov
1 sibling, 1 reply; 6+ messages in thread
From: Vinod Koul @ 2022-09-20 6:45 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: andersson, kishon, linux-arm-msm, linux-phy, linux-kernel
On 10-09-22, 12:08, Manivannan Sadhasivam wrote:
> In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and
> QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2
> and QPHY_V5_PCS_EQ_CONFIG3.
>
> This causes high latency when ASPM is enabled, so fix it!
>
> Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 ++--
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index 4648467d5cac..b508903d77d0 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -1332,8 +1332,8 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
> };
>
> static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
> - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
> - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG4, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x22),
> QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
> QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
> };
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> index 61a44519f969..cca6455ec98c 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> @@ -11,7 +11,7 @@
> #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
> #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
> #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
> -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
> -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
> +#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0
> +#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4
This conflicts with c0c7769cdae2 ("phy: qcom-qmp: Add SC8280XP USB3 UNI phy")
where QPHY_V5_PCS_EQ_CONFIG5 was added as 0x1e0
Do we have a different v5 for SM8450 and SC8280XP?
--
~Vinod
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers
2022-09-20 6:45 ` Vinod Koul
@ 2022-09-20 9:29 ` Johan Hovold
0 siblings, 0 replies; 6+ messages in thread
From: Johan Hovold @ 2022-09-20 9:29 UTC (permalink / raw)
To: Vinod Koul, Manivannan Sadhasivam
Cc: andersson, kishon, linux-arm-msm, linux-phy, linux-kernel
On Tue, Sep 20, 2022 at 12:15:56PM +0530, Vinod Koul wrote:
> On 10-09-22, 12:08, Manivannan Sadhasivam wrote:
> > In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and
> > QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2
> > and QPHY_V5_PCS_EQ_CONFIG3.
> >
> > This causes high latency when ASPM is enabled, so fix it!
> >
> > Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > index 61a44519f969..cca6455ec98c 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > @@ -11,7 +11,7 @@
> > #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
> > #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
> > #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
> > -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
> > -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
Why are you removing these defines? (They are correct for sc8280xp.)
> > +#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0
> > +#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4
>
> This conflicts with c0c7769cdae2 ("phy: qcom-qmp: Add SC8280XP USB3 UNI phy")
>
> where QPHY_V5_PCS_EQ_CONFIG5 was added as 0x1e0
>
> Do we have a different v5 for SM8450 and SC8280XP?
I can confirm that the PCS_EQ_CONFIG defines added for sc8280xp matches
the vendor's headers for both the combo and USB PHYs.
Johan
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers
2022-09-10 6:38 [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers Manivannan Sadhasivam
2022-09-20 6:45 ` Vinod Koul
@ 2022-09-21 13:06 ` Dmitry Baryshkov
2022-10-26 14:31 ` Manivannan Sadhasivam
1 sibling, 1 reply; 6+ messages in thread
From: Dmitry Baryshkov @ 2022-09-21 13:06 UTC (permalink / raw)
To: Manivannan Sadhasivam, vkoul, andersson
Cc: kishon, linux-arm-msm, linux-phy, linux-kernel
On 10/09/2022 09:38, Manivannan Sadhasivam wrote:
> In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and
> QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2
> and QPHY_V5_PCS_EQ_CONFIG3.
>
> This causes high latency when ASPM is enabled, so fix it!
I have checked against vendor's tree [1]. The registers in question have
offsets 0x01c0f3e0 / 0x01c0f3e4. The sm8450.dtsi uses 0x1c0f200 as the
PCS region base for the PCIe PHY1. Thus the correct offsets for the
table are 0x1e0/0x1e4.
There might be a mistake in the name of the register, but the address
corresponds to the address in the vendor's tree.
[1]
https://github.com/MiCode/kernel_devicetree/blob/zeus-s-oss/qcom/waipio-pcie.dtsi#L520
>
> Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 ++--
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index 4648467d5cac..b508903d77d0 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -1332,8 +1332,8 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
> };
>
> static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
> - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
> - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG4, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x22),
> QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
> QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
> };
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> index 61a44519f969..cca6455ec98c 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> @@ -11,7 +11,7 @@
> #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
> #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
> #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
> -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
> -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
> +#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0
> +#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4
>
> #endif
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers
2022-09-21 13:06 ` Dmitry Baryshkov
@ 2022-10-26 14:31 ` Manivannan Sadhasivam
2022-10-26 16:45 ` Dmitry Baryshkov
0 siblings, 1 reply; 6+ messages in thread
From: Manivannan Sadhasivam @ 2022-10-26 14:31 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: vkoul, andersson, kishon, linux-arm-msm, linux-phy, linux-kernel
On Wed, Sep 21, 2022 at 04:06:10PM +0300, Dmitry Baryshkov wrote:
> On 10/09/2022 09:38, Manivannan Sadhasivam wrote:
> > In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and
> > QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2
> > and QPHY_V5_PCS_EQ_CONFIG3.
> >
> > This causes high latency when ASPM is enabled, so fix it!
>
> I have checked against vendor's tree [1]. The registers in question have
> offsets 0x01c0f3e0 / 0x01c0f3e4. The sm8450.dtsi uses 0x1c0f200 as the PCS
> region base for the PCIe PHY1. Thus the correct offsets for the table are
> 0x1e0/0x1e4.
>
> There might be a mistake in the name of the register, but the address
> corresponds to the address in the vendor's tree.
>
Right. Only the register name is wrong and I've got the offset wrong here.
But the actual latency issue is fixed by clearing the
QPHY_V4_PCS_PCIE_PRESET_P10_POST register in pcs_misc register space.
I will check with Qcom on this behaviour and post v2 with register name fix.
Thanks,
Mani
> [1] https://github.com/MiCode/kernel_devicetree/blob/zeus-s-oss/qcom/waipio-pcie.dtsi#L520
>
> >
> > Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 ++--
> > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 4 ++--
> > 2 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > index 4648467d5cac..b508903d77d0 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > @@ -1332,8 +1332,8 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
> > };
> > static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
> > - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
> > - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG4, 0x16),
> > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x22),
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
> > };
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > index 61a44519f969..cca6455ec98c 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
> > @@ -11,7 +11,7 @@
> > #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
> > #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
> > #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
> > -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
> > -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
> > +#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0
> > +#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4
> > #endif
>
> --
> With best wishes
> Dmitry
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers
2022-10-26 14:31 ` Manivannan Sadhasivam
@ 2022-10-26 16:45 ` Dmitry Baryshkov
0 siblings, 0 replies; 6+ messages in thread
From: Dmitry Baryshkov @ 2022-10-26 16:45 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: vkoul, andersson, kishon, linux-arm-msm, linux-phy, linux-kernel
On 26/10/2022 17:31, Manivannan Sadhasivam wrote:
> On Wed, Sep 21, 2022 at 04:06:10PM +0300, Dmitry Baryshkov wrote:
>> On 10/09/2022 09:38, Manivannan Sadhasivam wrote:
>>> In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and
>>> QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2
>>> and QPHY_V5_PCS_EQ_CONFIG3.
>>>
>>> This causes high latency when ASPM is enabled, so fix it!
>>
>> I have checked against vendor's tree [1]. The registers in question have
>> offsets 0x01c0f3e0 / 0x01c0f3e4. The sm8450.dtsi uses 0x1c0f200 as the PCS
>> region base for the PCIe PHY1. Thus the correct offsets for the table are
>> 0x1e0/0x1e4.
>>
>> There might be a mistake in the name of the register, but the address
>> corresponds to the address in the vendor's tree.
>>
>
> Right. Only the register name is wrong and I've got the offset wrong here.
> But the actual latency issue is fixed by clearing the
> QPHY_V4_PCS_PCIE_PRESET_P10_POST register in pcs_misc register space.
Please, don't use v4 register names in v5.2 tables. If the register
matches, could you please add corresponding define?
>
> I will check with Qcom on this behaviour and post v2 with register name fix.
>
> Thanks,
> Mani
>
>> [1] https://github.com/MiCode/kernel_devicetree/blob/zeus-s-oss/qcom/waipio-pcie.dtsi#L520
>>
>>>
>>> Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
>>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>> ---
>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 ++--
>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 4 ++--
>>> 2 files changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>>> index 4648467d5cac..b508903d77d0 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>>> @@ -1332,8 +1332,8 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
>>> };
>>> static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
>>> - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
>>> - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
>>> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG4, 0x16),
>>> + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x22),
>>> QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
>>> QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
>>> };
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
>>> index 61a44519f969..cca6455ec98c 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h
>>> @@ -11,7 +11,7 @@
>>> #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170
>>> #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188
>>> #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198
>>> -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0
>>> -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4
>>> +#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0
>>> +#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4
>>> #endif
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 6+ messages in thread
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Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2022-09-10 6:38 [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers Manivannan Sadhasivam
2022-09-20 6:45 ` Vinod Koul
2022-09-20 9:29 ` Johan Hovold
2022-09-21 13:06 ` Dmitry Baryshkov
2022-10-26 14:31 ` Manivannan Sadhasivam
2022-10-26 16:45 ` Dmitry Baryshkov
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