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* [PATCH] arm64: dts: qcom: sa8775p: Mark APPS and PCIE SMMUs as DMA coherent
@ 2024-07-15  7:16 Qingqing Zhou
  2024-07-15 16:39 ` Konrad Dybcio
  2024-07-15 18:14 ` Andrew Halaney
  0 siblings, 2 replies; 7+ messages in thread
From: Qingqing Zhou @ 2024-07-15  7:16 UTC (permalink / raw)
  To: andersson, konrad.dybcio, robh, krzk+dt, conor+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, Qingqing Zhou

The SMMUs on sa8775p are cache-coherent. GPU SMMU is marked as such,
mark the APPS and PCIE ones as well.

Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 23f1b2e5e624..95691ab58a23 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3070,6 +3070,7 @@
 			reg = <0x0 0x15000000 0x0 0x100000>;
 			#iommu-cells = <2>;
 			#global-interrupts = <2>;
+			dma-coherent;
 
 			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
@@ -3208,6 +3209,7 @@
 			reg = <0x0 0x15200000 0x0 0x80000>;
 			#iommu-cells = <2>;
 			#global-interrupts = <2>;
+			dma-coherent;
 
 			interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2024-07-16  7:00 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2024-07-15  7:16 [PATCH] arm64: dts: qcom: sa8775p: Mark APPS and PCIE SMMUs as DMA coherent Qingqing Zhou
2024-07-15 16:39 ` Konrad Dybcio
2024-07-15 16:40   ` Konrad Dybcio
2024-07-15 18:14 ` Andrew Halaney
2024-07-16  6:00   ` Qingqing Zhou
2024-07-16  6:05     ` Manivannan Sadhasivam
2024-07-16  7:00       ` Qingqing Zhou

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