Linux ARM-MSM sub-architecture
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From: Antonino Maniscalco <antomani103@gmail.com>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
	 Konrad Dybcio <konrad.dybcio@linaro.org>,
	 Abhinav Kumar <quic_abhinavk@quicinc.com>,
	 Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	 Marijn Suijten <marijn.suijten@somainline.org>,
	 David Airlie <airlied@gmail.com>,
	Daniel Vetter <daniel@ffwll.ch>,
	 Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	 Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	 freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	 Antonino Maniscalco <antomani103@gmail.com>,
	 Sharat Masetty <smasetty@codeaurora.org>,
	 Akhil P Oommen <quic_akhilpo@quicinc.com>,
	 Neil Armstrong <neil.armstrong@linaro.org>
Subject: [PATCH v2 2/9] drm/msm: Add submitqueue setup and close
Date: Fri, 30 Aug 2024 17:32:44 +0200	[thread overview]
Message-ID: <20240830-preemption-a750-t-v2-2-86aeead2cd80@gmail.com> (raw)
In-Reply-To: <20240830-preemption-a750-t-v2-0-86aeead2cd80@gmail.com>

This patch adds a bit of infrastructure to give the different Adreno
targets the flexibility to setup the submitqueues per their needs.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Antonino Maniscalco <antomani103@gmail.com>
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
---
 drivers/gpu/drm/msm/msm_gpu.h         |  7 +++++++
 drivers/gpu/drm/msm/msm_submitqueue.c | 10 ++++++++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 1f02bb9956be..70f5c18e5aee 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -92,6 +92,10 @@ struct msm_gpu_funcs {
 	 * for cmdstream that is buffered in this FIFO upstream of the CP fw.
 	 */
 	bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
+	int (*submitqueue_setup)(struct msm_gpu *gpu,
+			struct msm_gpu_submitqueue *queue);
+	void (*submitqueue_close)(struct msm_gpu *gpu,
+			struct msm_gpu_submitqueue *queue);
 };
 
 /* Additional state for iommu faults: */
@@ -522,6 +526,9 @@ struct msm_gpu_submitqueue {
 	struct mutex lock;
 	struct kref ref;
 	struct drm_sched_entity *entity;
+	struct msm_gpu *gpu;
+	struct drm_gem_object *bo;
+	uint64_t bo_iova;
 };
 
 struct msm_gpu_state_bo {
diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c
index 0e803125a325..4ffb336d9a60 100644
--- a/drivers/gpu/drm/msm/msm_submitqueue.c
+++ b/drivers/gpu/drm/msm/msm_submitqueue.c
@@ -71,6 +71,11 @@ void msm_submitqueue_destroy(struct kref *kref)
 	struct msm_gpu_submitqueue *queue = container_of(kref,
 		struct msm_gpu_submitqueue, ref);
 
+	struct msm_gpu *gpu = queue->gpu;
+
+	if (gpu && gpu->funcs->submitqueue_close)
+		gpu->funcs->submitqueue_close(gpu, queue);
+
 	idr_destroy(&queue->fence_idr);
 
 	msm_file_private_put(queue->ctx);
@@ -160,6 +165,7 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,
 {
 	struct msm_drm_private *priv = drm->dev_private;
 	struct msm_gpu_submitqueue *queue;
+	struct msm_gpu *gpu = priv->gpu;
 	enum drm_sched_priority sched_prio;
 	unsigned ring_nr;
 	int ret;
@@ -195,6 +201,7 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,
 
 	queue->ctx = msm_file_private_get(ctx);
 	queue->id = ctx->queueid++;
+	queue->gpu = gpu;
 
 	if (id)
 		*id = queue->id;
@@ -207,6 +214,9 @@ int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,
 
 	write_unlock(&ctx->queuelock);
 
+	if (gpu && gpu->funcs->submitqueue_setup)
+		gpu->funcs->submitqueue_setup(gpu, queue);
+
 	return 0;
 }
 

-- 
2.46.0


  parent reply	other threads:[~2024-08-30 15:33 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-30 15:32 [PATCH v2 0/9] Preemption support for A7XX Antonino Maniscalco
2024-08-30 15:32 ` [PATCH v2 1/9] drm/msm: Fix bv_fence being used as bv_rptr Antonino Maniscalco
2024-08-30 15:32 ` Antonino Maniscalco [this message]
2024-08-30 15:32 ` [PATCH v2 3/9] drm/msm: Add a `preempt_record_size` field Antonino Maniscalco
2024-08-30 15:32 ` [PATCH v2 4/9] drm/msm/A6xx: Implement preemption for A7XX targets Antonino Maniscalco
2024-08-30 18:01   ` Rob Clark
2024-08-30 18:54     ` Connor Abbott
2024-08-30 19:00       ` Rob Clark
2024-08-30 19:09         ` Connor Abbott
2024-08-30 20:19           ` Rob Clark
2024-08-30 20:25   ` Rob Clark
2024-08-31 14:26     ` Antonino Maniscalco
2024-08-30 20:36   ` Rob Clark
2024-08-30 15:32 ` [PATCH v2 5/9] drm/msm/A6xx: Sync relevant adreno_pm4.xml changes Antonino Maniscalco
2024-08-30 15:32 ` [PATCH v2 6/9] drm/msm/A6xx: Use posamble to reset counters on preemption Antonino Maniscalco
2024-08-30 18:32   ` Rob Clark
2024-09-04 13:38     ` Antonino Maniscalco
2024-09-04 14:30       ` Rob Clark
2024-08-30 15:32 ` [PATCH v2 7/9] drm/msm/A6xx: Add traces for preemption Antonino Maniscalco
2024-08-30 15:32 ` [PATCH v2 8/9] drm/msm/A6XX: Add a flag to allow preemption to submitqueue_create Antonino Maniscalco
2024-08-30 15:32 ` [PATCH v2 9/9] drm/msm/A6xx: Enable preemption for A750 Antonino Maniscalco
2024-08-30 18:23   ` Rob Clark

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