* [PATCH v2] arm64: dts: qcom: sm8550: Add UART15
@ 2026-02-11 22:35 Aaron Kling via B4 Relay
2026-02-12 10:49 ` Konrad Dybcio
0 siblings, 1 reply; 4+ messages in thread
From: Aaron Kling via B4 Relay @ 2026-02-11 22:35 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Xilin Wu, Molly Sophia,
Aaron Kling, Dmitry Baryshkov
From: Xilin Wu <wuxilin123@gmail.com>
Add uart15 node for UART bus present on sm8550 SoC.
Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
This patch was originally submitted as part of a series to support the
AYN Odin 2 [0]. That series stalled, so submitting separately.
[0] https://lore.kernel.org/all/20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com/
---
Changes in v2:
- Use QCOM_ICC_TAG_ define in interconnect paths phandle third argument
- Link to v1: https://lore.kernel.org/r/20260207-sm8550-uart15-v1-1-d8ccf746d102@gmail.com
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..a54f375f7f041a193a4396e4aa911abb42e3e6dc 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1251,6 +1251,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
#size-cells = <0>;
status = "disabled";
};
+
+ uart15: serial@89c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x89c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart15_default>;
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
};
i2c_master_hub_0: geniqup@9c0000 {
@@ -5095,6 +5111,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
bias-pull-down;
};
+ qup_uart15_default: qup-uart15-default-state {
+ /* TX, RX */
+ pins = "gpio74", "gpio75";
+ function = "qup2_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
sdc2_sleep: sdc2-sleep-state {
clk-pins {
pins = "sdc2_clk";
---
base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
change-id: 20260207-sm8550-uart15-9b7bd48e747d
Best regards,
--
Aaron Kling <webgeek1234@gmail.com>
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v2] arm64: dts: qcom: sm8550: Add UART15
2026-02-11 22:35 [PATCH v2] arm64: dts: qcom: sm8550: Add UART15 Aaron Kling via B4 Relay
@ 2026-02-12 10:49 ` Konrad Dybcio
2026-02-12 14:53 ` Aaron Kling
0 siblings, 1 reply; 4+ messages in thread
From: Konrad Dybcio @ 2026-02-12 10:49 UTC (permalink / raw)
To: webgeek1234, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Xilin Wu, Molly Sophia,
Dmitry Baryshkov
On 2/11/26 11:35 PM, Aaron Kling via B4 Relay wrote:
> From: Xilin Wu <wuxilin123@gmail.com>
>
> Add uart15 node for UART bus present on sm8550 SoC.
>
> Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
> Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> This patch was originally submitted as part of a series to support the
> AYN Odin 2 [0]. That series stalled, so submitting separately.
>
> [0] https://lore.kernel.org/all/20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com/
> ---
> Changes in v2:
> - Use QCOM_ICC_TAG_ define in interconnect paths phandle third argument
> - Link to v1: https://lore.kernel.org/r/20260207-sm8550-uart15-v1-1-d8ccf746d102@gmail.com
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..a54f375f7f041a193a4396e4aa911abb42e3e6dc 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1251,6 +1251,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + uart15: serial@89c000 {
This should be uart23 (see other nodes at this base addr have that index)
> + compatible = "qcom,geni-uart";
> + reg = <0 0x89c000 0 0x4000>;
Please pad the address to 8 hex digits with leading zeroes
[...]
> + qup_uart15_default: qup-uart15-default-state {
And let's also update the name here
Konrad
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v2] arm64: dts: qcom: sm8550: Add UART15
2026-02-12 10:49 ` Konrad Dybcio
@ 2026-02-12 14:53 ` Aaron Kling
2026-02-12 14:57 ` Konrad Dybcio
0 siblings, 1 reply; 4+ messages in thread
From: Aaron Kling @ 2026-02-12 14:53 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, Xilin Wu,
Molly Sophia, Dmitry Baryshkov
On Thu, Feb 12, 2026 at 4:49 AM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 2/11/26 11:35 PM, Aaron Kling via B4 Relay wrote:
> > From: Xilin Wu <wuxilin123@gmail.com>
> >
> > Add uart15 node for UART bus present on sm8550 SoC.
> >
> > Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
> > Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> > ---
> > This patch was originally submitted as part of a series to support the
> > AYN Odin 2 [0]. That series stalled, so submitting separately.
> >
> > [0] https://lore.kernel.org/all/20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com/
> > ---
> > Changes in v2:
> > - Use QCOM_ICC_TAG_ define in interconnect paths phandle third argument
> > - Link to v1: https://lore.kernel.org/r/20260207-sm8550-uart15-v1-1-d8ccf746d102@gmail.com
> > ---
> > arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++++++
> > 1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..a54f375f7f041a193a4396e4aa911abb42e3e6dc 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > @@ -1251,6 +1251,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
> > #size-cells = <0>;
> > status = "disabled";
> > };
> > +
> > + uart15: serial@89c000 {
>
> This should be uart23 (see other nodes at this base addr have that index)
Am I missing something here? For sm8550 [0], I see i2c@89c000 and
spi@89c000 labelled as i2c15 and spi15 respectively.
> > + compatible = "qcom,geni-uart";
> > + reg = <0 0x89c000 0 0x4000>;
>
> Please pad the address to 8 hex digits with leading zeroes
Ack.
> [...]
> > + qup_uart15_default: qup-uart15-default-state {
>
> And let's also update the name here
>
> Konrad
Aaron
[0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/qcom/sm8550.dtsi?h=v6.19#n1205
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v2] arm64: dts: qcom: sm8550: Add UART15
2026-02-12 14:53 ` Aaron Kling
@ 2026-02-12 14:57 ` Konrad Dybcio
0 siblings, 0 replies; 4+ messages in thread
From: Konrad Dybcio @ 2026-02-12 14:57 UTC (permalink / raw)
To: Aaron Kling
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, Xilin Wu,
Molly Sophia, Dmitry Baryshkov
On 2/12/26 3:53 PM, Aaron Kling wrote:
> On Thu, Feb 12, 2026 at 4:49 AM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 2/11/26 11:35 PM, Aaron Kling via B4 Relay wrote:
>>> From: Xilin Wu <wuxilin123@gmail.com>
>>>
>>> Add uart15 node for UART bus present on sm8550 SoC.
>>>
>>> Signed-off-by: Molly Sophia <mollysophia379@gmail.com>
>>> Signed-off-by: Xilin Wu <wuxilin123@gmail.com>
>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
>>> ---
>>> This patch was originally submitted as part of a series to support the
>>> AYN Odin 2 [0]. That series stalled, so submitting separately.
>>>
>>> [0] https://lore.kernel.org/all/20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com/
>>> ---
>>> Changes in v2:
>>> - Use QCOM_ICC_TAG_ define in interconnect paths phandle third argument
>>> - Link to v1: https://lore.kernel.org/r/20260207-sm8550-uart15-v1-1-d8ccf746d102@gmail.com
>>> ---
>>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++++++
>>> 1 file changed, 24 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>> index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..a54f375f7f041a193a4396e4aa911abb42e3e6dc 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>>> @@ -1251,6 +1251,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
>>> #size-cells = <0>;
>>> status = "disabled";
>>> };
>>> +
>>> + uart15: serial@89c000 {
>>
>> This should be uart23 (see other nodes at this base addr have that index)
>
> Am I missing something here? For sm8550 [0], I see i2c@89c000 and
> spi@89c000 labelled as i2c15 and spi15 respectively.
Well, it seems like I implicitly upgraded your device in my brain.. what I
said is true for x elite..
Konrad
^ permalink raw reply [flat|nested] 4+ messages in thread
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2026-02-11 22:35 [PATCH v2] arm64: dts: qcom: sm8550: Add UART15 Aaron Kling via B4 Relay
2026-02-12 10:49 ` Konrad Dybcio
2026-02-12 14:53 ` Aaron Kling
2026-02-12 14:57 ` Konrad Dybcio
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