From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <quic_abhinavk@quicinc.com>
Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
Bjorn Andersson <andersson@kernel.org>,
dri-devel@lists.freedesktop.org,
Stephen Boyd <swboyd@chromium.org>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@gmail.com>
Subject: Re: [v2,48/50] drm/msm/dpu: rename VIG and DMA_foo_MASK to contain major DPU version
Date: Thu, 30 Mar 2023 15:24:28 +0200 [thread overview]
Message-ID: <308a8696-c8df-2fb0-026a-576756642e05@linaro.org> (raw)
In-Reply-To: <20230211231259.1308718-49-dmitry.baryshkov@linaro.org>
On 12.02.2023 00:12, Dmitry Baryshkov wrote:
> To ease review and reuse rename VIG and DMA feature masks to contain
> base DPU version since which this mask is used.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 16 ++++++-------
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 16 ++++++-------
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h | 16 ++++++-------
> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 16 ++++++-------
> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 +++----
> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 4 ++--
> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 4 +++-
> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 16 ++++++-------
> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 8 +++----
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h | 16 ++++++-------
> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 20 ++++++++--------
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 24 +++++++++----------
> 12 files changed, 82 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index d42c380275bd..88b7949f803e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -79,21 +79,21 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg msm8998_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_DPU_3_MASK,
I guess I answered by own question
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK,
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_DPU_3_MASK,
> msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK,
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_DPU_3_MASK,
> msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_DPU_3_MASK,
> msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_DPU_3_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_DPU_3_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_DPU_3_CURSOR_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_DPU_3_CURSOR_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 281556416322..c8c57250473a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -77,21 +77,21 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sdm845_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_DPU_4_MASK,
> sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_DPU_4_MASK,
> sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_DPU_4_MASK,
> sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_DPU_4_MASK,
> sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_DPU_4_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_DPU_4_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
> index 7c051c142e06..2f849cbaaa0f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
> @@ -78,21 +78,21 @@ static const struct dpu_ctl_cfg dpu_5_lm6_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg dpu_5_lm6_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_DPU_4_MASK,
> sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_DPU_4_MASK,
> sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_DPU_4_MASK,
> sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_DPU_4_MASK,
> sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_DPU_4_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_DPU_4_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index cffbb6bcc535..071814394b52 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -84,21 +84,21 @@ static const struct dpu_ctl_cfg sm8250_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sm8250_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_DPU_6_MASK,
> sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_DPU_6_MASK,
> sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_DPU_6_MASK,
> sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_DPU_6_MASK,
> sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_DPU_4_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_DPU_4_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 78f8b2506675..4be65088de0e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -58,13 +58,13 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sc7180_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_DPU_6_MASK,
> sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_DPU_4_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 1ba646cb96a9..e7c8df358228 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -27,9 +27,9 @@ static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
> };
>
> static const struct dpu_sspp_cfg sm6115_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_DPU_6_MASK,
> sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_DPU_4_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 2d9b54ff6510..c2592ae953f0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -9,6 +9,8 @@
>
> #include "dpu_6_lm1.h"
>
> +#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
> +
> static const struct dpu_caps qcm2290_dpu_caps = {
> .max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
> .max_mixer_blendstages = 0x4,
> @@ -26,7 +28,7 @@ static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
> static const struct dpu_sspp_cfg qcm2290_sspp[] = {
> SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
> qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_DPU_4_MASK,
> qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 6826758fa202..31c12b0415ad 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -82,21 +82,21 @@ static const struct dpu_ctl_cfg sm8350_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sm8350_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_DPU_6_MASK,
> sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_DPU_6_MASK,
> sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_DPU_6_MASK,
> sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_DPU_6_MASK,
> sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_DPU_4_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_DPU_4_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index c5981ea3ec7c..a7040d9d83de 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -63,13 +63,13 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sc7280_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_DPU_7_ROT_MASK,
> sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_DPU_4_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h
> index 5c87e919ea22..fb1fbba12a5b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h
> @@ -77,21 +77,21 @@ static const struct dpu_ctl_cfg dpu_8_lm6_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg dpu_8_lm6_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x328, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x328, VIG_DPU_6_MASK,
> sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x328, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x328, VIG_DPU_6_MASK,
> sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x328, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x328, VIG_DPU_6_MASK,
> sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x328, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x328, VIG_DPU_6_MASK,
> sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x328, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x328, DMA_DPU_4_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x328, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x328, DMA_DPU_4_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x328, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x328, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x328, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x328, DMA_DPU_4_CURSOR_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 334946c8d4e8..1d38d1c3e12a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -84,25 +84,25 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
> };
>
> static const struct dpu_sspp_cfg sm8550_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_DPU_6_MASK,
> sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_DPU_6_MASK,
> sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_DPU_6_MASK,
> sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK,
> + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_DPU_6_MASK,
> sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_DPU_4_MASK,
> sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_DPU_4_MASK,
> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_DPU_4_MASK,
> sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK,
> + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_DPU_4_MASK,
> sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> - SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_DPU_4_CURSOR_MASK,
> sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4),
> - SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK,
> + SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_DPU_4_CURSOR_MASK,
> sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5),
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 3c604f7b88aa..0a86428af393 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -21,35 +21,33 @@
> (VIG_BASE_MASK | \
> BIT(DPU_SSPP_CSC_10BIT))
>
> -#define VIG_MSM8998_MASK \
> +#define VIG_DPU_3_MASK \
> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
>
> -#define VIG_SDM845_MASK \
> +#define VIG_DPU_4_MASK \
> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3))
>
> -#define VIG_SC7180_MASK \
> +#define VIG_DPU_6_MASK \
> (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
>
> -#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
> +#define VIG_DPU_7_ROT_MASK \
> + (VIG_DPU_6_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
>
> -#define DMA_MSM8998_MASK \
> +#define DMA_DPU_3_MASK \
> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
> BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
> BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
>
> -#define VIG_SC7280_MASK \
> - (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
> -
> -#define DMA_SDM845_MASK \
> +#define DMA_DPU_4_MASK \
> (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
> BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
> BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
>
> -#define DMA_CURSOR_SDM845_MASK \
> - (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
> +#define DMA_DPU_3_CURSOR_MASK \
> + (DMA_DPU_3_MASK | BIT(DPU_SSPP_CURSOR))
>
> -#define DMA_CURSOR_MSM8998_MASK \
> - (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
> +#define DMA_DPU_4_CURSOR_MASK \
> + (DMA_DPU_4_MASK | BIT(DPU_SSPP_CURSOR))
>
> #define MIXER_MSM8998_MASK \
> (BIT(DPU_MIXER_SOURCESPLIT))
next prev parent reply other threads:[~2023-03-30 13:24 UTC|newest]
Thread overview: 127+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-11 23:12 [PATCH v2 00/50] drm/msm/dpu: rework HW catalog Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 01/50] drm/msm/dpu: set DPU_MDP_PERIPH_0_REMOVED for sc8280xp Dmitry Baryshkov
2023-03-16 0:27 ` (subset) " Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 02/50] drm/msm/dpu: disable features unsupported by QCM2290 Dmitry Baryshkov
2023-03-16 0:30 ` (subset) " Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 03/50] drm/msm/dpu: fix typo in in sm8550's dma_sblk_5 Dmitry Baryshkov
2023-02-13 17:37 ` Neil Armstrong
2023-02-24 18:06 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 04/50] drm/msm/dpu: fix len of sc7180 ctl blocks Dmitry Baryshkov
2023-02-24 18:12 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 05/50] drm/msm/dpu: fix sm6115 and qcm2290 mixer width limits Dmitry Baryshkov
2023-02-24 19:11 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 06/50] drm/msm/dpu: correct sm8550 scaler Dmitry Baryshkov
2023-02-13 10:41 ` Neil Armstrong
2023-02-13 11:16 ` Dmitry Baryshkov
2023-02-13 17:36 ` neil.armstrong
2023-02-24 20:51 ` Abhinav Kumar
2023-02-25 23:06 ` Dmitry Baryshkov
2023-02-25 23:27 ` Abhinav Kumar
2023-02-26 0:06 ` Dmitry Baryshkov
2023-02-26 2:10 ` Abhinav Kumar
2023-02-26 12:59 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 07/50] drm/msm/dpu: correct sc8280xp scaler Dmitry Baryshkov
2023-02-25 22:55 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 08/50] drm/msm/dpu: correct sm8450 scaler Dmitry Baryshkov
2023-02-25 22:55 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 09/50] drm/msm/dpu: correct sm8250 and sm8350 scaler Dmitry Baryshkov
2023-02-25 22:59 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 10/50] drm/msm/dpu: correct sm6115 scaler Dmitry Baryshkov
2023-02-25 23:11 ` Abhinav Kumar
2023-02-26 0:01 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 11/50] drm/msm/dpu: drop DPU_DIM_LAYER from MIXER_MSM8998_MASK Dmitry Baryshkov
2023-02-28 23:04 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 12/50] drm/msm/dpu: fix clocks settings for msm8998 SSPP blocks Dmitry Baryshkov
2023-02-25 23:32 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 13/50] drm/msm/dpu: don't use DPU_CLK_CTRL_CURSORn for DMA SSPP clocks Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 14/50] drm/msm/dpu: Allow variable SSPP/INTF_BLK size Dmitry Baryshkov
2023-02-13 11:01 ` Konrad Dybcio
2023-02-13 11:18 ` Dmitry Baryshkov
2023-03-29 20:01 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 15/50] drm/msm/dpu: constify DSC data structures Dmitry Baryshkov
2023-03-29 19:49 ` [v2,15/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 16/50] drm/msm/dpu: mark remaining pp data as const Dmitry Baryshkov
2023-03-29 20:15 ` [v2,16/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 17/50] drm/msm/dpu: move UBWC/memory configuration to separate struct Dmitry Baryshkov
2023-03-29 20:23 ` [v2,17/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 18/50] drm/msm/dpu: split SM8550 catalog entry to the separate file Dmitry Baryshkov
2023-03-29 20:25 ` [v2,18/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 19/50] drm/msm/dpu: split SM8450 " Dmitry Baryshkov
2023-03-30 11:34 ` [v2,19/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 20/50] drm/msm/dpu: split SC8280XP " Dmitry Baryshkov
2023-03-30 11:39 ` [v2,20/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 21/50] drm/msm/dpu: split SC7280 " Dmitry Baryshkov
2023-03-30 11:41 ` [v2,21/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 22/50] drm/msm/dpu: split SM8350 " Dmitry Baryshkov
2023-03-30 11:46 ` [v2,22/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 23/50] drm/msm/dpu: split SM6115 " Dmitry Baryshkov
2023-03-30 11:47 ` [v2,23/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 24/50] drm/msm/dpu: split QCM2290 " Dmitry Baryshkov
2023-03-30 11:50 ` [v2,24/50] " Konrad Dybcio
2023-03-30 11:52 ` Dmitry Baryshkov
2023-03-30 11:53 ` Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 25/50] drm/msm/dpu: split SC7180 " Dmitry Baryshkov
2023-03-30 11:55 ` [v2,25/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 26/50] drm/msm/dpu: split SM8250 " Dmitry Baryshkov
2023-03-30 12:06 ` [v2,26/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 27/50] drm/msm/dpu: split SC8180X " Dmitry Baryshkov
2023-03-30 12:08 ` [v2,27/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 28/50] drm/msm/dpu: split SM8150 " Dmitry Baryshkov
2023-03-30 12:10 ` [v2,28/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 29/50] drm/msm/dpu: split MSM8998 " Dmitry Baryshkov
2023-03-30 12:14 ` [v2,29/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 30/50] drm/msm/dpu: split SDM845 " Dmitry Baryshkov
2023-03-30 12:19 ` [v2,30/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 31/50] drm/msm/dpu: duplicate sdm845 catalog entries Dmitry Baryshkov
2023-03-30 12:21 ` [v2,31/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 32/50] drm/msm/dpu: duplicate sc7180 " Dmitry Baryshkov
2023-03-30 12:22 ` [v2,32/50] " Konrad Dybcio
2023-03-30 12:24 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 33/50] drm/msm/dpu: duplicate sm8150 " Dmitry Baryshkov
2023-03-30 12:26 ` [v2,33/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 34/50] drm/msm/dpu: duplicate sm8250 " Dmitry Baryshkov
2023-03-30 12:27 ` [v2,34/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 35/50] drm/msm/dpu: duplicate sm8350 " Dmitry Baryshkov
2023-03-30 12:27 ` [v2,35/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 36/50] drm/msm/dpu: use defined symbol for sc8280xp's maxwidth Dmitry Baryshkov
2023-03-30 12:28 ` [v2,36/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 37/50] drm/msm/dpu: enable DPU_CTL_SPLIT_DISPLAY for sc8280xp Dmitry Baryshkov
2023-03-30 12:29 ` [v2,37/50] " Konrad Dybcio
2023-03-30 21:32 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 38/50] drm/msm/dpu: enable DSPP_2/3 for LM_2/3 on sm8450 Dmitry Baryshkov
2023-03-30 12:33 ` [v2,38/50] " Konrad Dybcio
2023-03-30 12:38 ` Dmitry Baryshkov
2023-03-30 12:42 ` Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 39/50] drm/msm/dpu: drop duplicate vig_sblk instances Dmitry Baryshkov
2023-03-07 18:31 ` Dmitry Baryshkov
2023-03-30 12:34 ` [v2,39/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 40/50] drm/msm/dpu: enable DSPP on sc8180x Dmitry Baryshkov
2023-03-30 12:39 ` [v2,40/50] " Konrad Dybcio
2023-03-30 21:46 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 41/50] drm/msm/dpu: deduplicate sc8180x with sm8150 Dmitry Baryshkov
2023-03-30 12:55 ` [v2,41/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 42/50] drm/msm/dpu: deduplicate sm6115 with qcm2290 Dmitry Baryshkov
2023-03-30 12:56 ` [v2,42/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 43/50] drm/msm/dpu: deduplicate sc8280xp with sm8450 Dmitry Baryshkov
2023-03-30 12:59 ` [v2,43/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 44/50] drm/msm/dpu: drop unused macros from hw catalog Dmitry Baryshkov
2023-03-30 13:02 ` [v2,44/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 45/50] drm/msm/dpu: inline IRQ_n_MASK defines Dmitry Baryshkov
2023-03-30 13:08 ` [v2,45/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 46/50] drm/msm/dpu: rename INTF_foo_MASK to contain major DPU version Dmitry Baryshkov
2023-03-30 13:14 ` [v2,46/50] " Konrad Dybcio
2023-03-30 13:25 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 47/50] drm/msm/dpu: rename CTL_foo_MASK " Dmitry Baryshkov
2023-03-30 13:15 ` [v2,47/50] " Konrad Dybcio
2023-03-30 13:16 ` Konrad Dybcio
2023-03-30 13:26 ` Dmitry Baryshkov
2023-03-30 13:27 ` Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 48/50] drm/msm/dpu: rename VIG and DMA_foo_MASK " Dmitry Baryshkov
2023-03-30 13:24 ` Konrad Dybcio [this message]
2023-02-11 23:12 ` [PATCH v2 49/50] drm/msm/dpu: rename MIXER_foo_MASK " Dmitry Baryshkov
2023-03-30 13:25 ` [v2,49/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 50/50] drm/msm/dpu: rename MERGE_3D_foo_MASK " Dmitry Baryshkov
2023-03-30 13:26 ` [v2,50/50] " Konrad Dybcio
2023-03-07 18:02 ` [PATCH v2 00/50] drm/msm/dpu: rework HW catalog Dmitry Baryshkov
2023-03-07 18:20 ` [Freedreno] " Abhinav Kumar
2023-03-16 2:28 ` (subset) " Abhinav Kumar
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