From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <quic_abhinavk@quicinc.com>
Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
Bjorn Andersson <andersson@kernel.org>,
dri-devel@lists.freedesktop.org,
Stephen Boyd <swboyd@chromium.org>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@gmail.com>
Subject: Re: [v2,47/50] drm/msm/dpu: rename CTL_foo_MASK to contain major DPU version
Date: Thu, 30 Mar 2023 15:16:45 +0200 [thread overview]
Message-ID: <a699774e-d403-46e8-921e-6a4a048cab79@linaro.org> (raw)
In-Reply-To: <045895cf-7866-1c0c-51c3-34ea3a7f0cab@linaro.org>
On 30.03.2023 15:15, Konrad Dybcio wrote:
>
>
> On 12.02.2023 00:12, Dmitry Baryshkov wrote:
>> To ease review and reuse rename CTL feature masks to contain base DPU
>> version since which this mask is used.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 10 +++++-----
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 10 +++++-----
>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h | 12 ++++++------
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 12 ++++++------
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 6 +++---
>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_lm1.h | 2 +-
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 12 ++++++------
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 8 ++++----
>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h | 12 ++++++------
>> .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++------
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++++++++----
>> 11 files changed, 56 insertions(+), 52 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
>> index 5e8200d929e4..d42c380275bd 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
>> @@ -49,31 +49,31 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
>> .base = 0x1000, .len = 0x94,
>> - .features = BIT(DPU_CTL_SPLIT_DISPLAY),
>> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_0_MASK,
> Again, I'd vote for DPU_3
Though thinking about it again, the 8996-and-earlier setup was
probably the same and that's what you had in mind. Please confirm
Konrad
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Konrad
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> },
>> {
>> .name = "ctl_1", .id = CTL_1,
>> .base = 0x1200, .len = 0x94,
>> - .features = 0,
>> + .features = CTL_DPU_0_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> },
>> {
>> .name = "ctl_2", .id = CTL_2,
>> .base = 0x1400, .len = 0x94,
>> - .features = BIT(DPU_CTL_SPLIT_DISPLAY),
>> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_0_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> },
>> {
>> .name = "ctl_3", .id = CTL_3,
>> .base = 0x1600, .len = 0x94,
>> - .features = 0,
>> + .features = CTL_DPU_0_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> },
>> {
>> .name = "ctl_4", .id = CTL_4,
>> .base = 0x1800, .len = 0x94,
>> - .features = 0,
>> + .features = CTL_DPU_0_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>> },
>> };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
>> index daef5e48e7ee..281556416322 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
>> @@ -47,31 +47,31 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
>> .base = 0x1000, .len = 0xe4,
>> - .features = BIT(DPU_CTL_SPLIT_DISPLAY),
>> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_0_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> },
>> {
>> .name = "ctl_1", .id = CTL_1,
>> .base = 0x1200, .len = 0xe4,
>> - .features = BIT(DPU_CTL_SPLIT_DISPLAY),
>> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_0_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> },
>> {
>> .name = "ctl_2", .id = CTL_2,
>> .base = 0x1400, .len = 0xe4,
>> - .features = 0,
>> + .features = CTL_DPU_0_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> },
>> {
>> .name = "ctl_3", .id = CTL_3,
>> .base = 0x1600, .len = 0xe4,
>> - .features = 0,
>> + .features = CTL_DPU_0_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> },
>> {
>> .name = "ctl_4", .id = CTL_4,
>> .base = 0x1800, .len = 0xe4,
>> - .features = 0,
>> + .features = CTL_DPU_0_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>> },
>> };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
>> index 294702531ce2..7c051c142e06 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_lm6.h
>> @@ -42,37 +42,37 @@ static const struct dpu_ctl_cfg dpu_5_lm6_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
>> .base = 0x1000, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
>> + .features = CTL_DPU_5_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> },
>> {
>> .name = "ctl_1", .id = CTL_1,
>> .base = 0x1200, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
>> + .features = CTL_DPU_5_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> },
>> {
>> .name = "ctl_2", .id = CTL_2,
>> .base = 0x1400, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> },
>> {
>> .name = "ctl_3", .id = CTL_3,
>> .base = 0x1600, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> },
>> {
>> .name = "ctl_4", .id = CTL_4,
>> .base = 0x1800, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>> },
>> {
>> .name = "ctl_5", .id = CTL_5,
>> .base = 0x1a00, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>> },
>> };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
>> index fd5df2bdec0e..cffbb6bcc535 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
>> @@ -48,37 +48,37 @@ static const struct dpu_ctl_cfg sm8250_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
>> .base = 0x1000, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
>> + .features = CTL_DPU_5_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> },
>> {
>> .name = "ctl_1", .id = CTL_1,
>> .base = 0x1200, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
>> + .features = CTL_DPU_5_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> },
>> {
>> .name = "ctl_2", .id = CTL_2,
>> .base = 0x1400, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> },
>> {
>> .name = "ctl_3", .id = CTL_3,
>> .base = 0x1600, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> },
>> {
>> .name = "ctl_4", .id = CTL_4,
>> .base = 0x1800, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>> },
>> {
>> .name = "ctl_5", .id = CTL_5,
>> .base = 0x1a00, .len = 0x1e0,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>> },
>> };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
>> index 66762a0706de..78f8b2506675 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
>> @@ -40,19 +40,19 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
>> .base = 0x1000, .len = 0x1dc,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> },
>> {
>> .name = "ctl_1", .id = CTL_1,
>> .base = 0x1200, .len = 0x1dc,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> },
>> {
>> .name = "ctl_2", .id = CTL_2,
>> .base = 0x1400, .len = 0x1dc,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> },
>> };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_lm1.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_lm1.h
>> index 2849c017ddf2..4f42105d3755 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_lm1.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_lm1.h
>> @@ -21,7 +21,7 @@ static const struct dpu_ctl_cfg dpu_6_lm1_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
>> .base = 0x1000, .len = 0x1dc,
>> - .features = BIT(DPU_CTL_ACTIVE_CFG),
>> + .features = CTL_DPU_5_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> },
>> };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>> index 60ad844cfa25..6826758fa202 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>> @@ -46,37 +46,37 @@ static const struct dpu_ctl_cfg sm8350_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
>> .base = 0x15000, .len = 0x1e8,
>> - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
>> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> },
>> {
>> .name = "ctl_1", .id = CTL_1,
>> .base = 0x16000, .len = 0x1e8,
>> - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
>> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> },
>> {
>> .name = "ctl_2", .id = CTL_2,
>> .base = 0x17000, .len = 0x1e8,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> },
>> {
>> .name = "ctl_3", .id = CTL_3,
>> .base = 0x18000, .len = 0x1e8,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> },
>> {
>> .name = "ctl_4", .id = CTL_4,
>> .base = 0x19000, .len = 0x1e8,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>> },
>> {
>> .name = "ctl_5", .id = CTL_5,
>> .base = 0x1a000, .len = 0x1e8,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>> },
>> };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>> index 387f2b6c5b56..c5981ea3ec7c 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>> @@ -39,25 +39,25 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
>> .base = 0x15000, .len = 0x1e8,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> },
>> {
>> .name = "ctl_1", .id = CTL_1,
>> .base = 0x16000, .len = 0x1e8,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> },
>> {
>> .name = "ctl_2", .id = CTL_2,
>> .base = 0x17000, .len = 0x1e8,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> },
>> {
>> .name = "ctl_3", .id = CTL_3,
>> .base = 0x18000, .len = 0x1e8,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> },
>> };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h
>> index 80a7b0670467..5c87e919ea22 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h
>> @@ -41,37 +41,37 @@ static const struct dpu_ctl_cfg dpu_8_lm6_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
>> .base = 0x15000, .len = 0x204,
>> - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
>> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> },
>> {
>> .name = "ctl_1", .id = CTL_1,
>> .base = 0x16000, .len = 0x204,
>> - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
>> + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> },
>> {
>> .name = "ctl_2", .id = CTL_2,
>> .base = 0x17000, .len = 0x204,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> },
>> {
>> .name = "ctl_3", .id = CTL_3,
>> .base = 0x18000, .len = 0x204,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> },
>> {
>> .name = "ctl_4", .id = CTL_4,
>> .base = 0x19000, .len = 0x204,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>> },
>> {
>> .name = "ctl_5", .id = CTL_5,
>> .base = 0x1a000, .len = 0x204,
>> - .features = CTL_SC7280_MASK,
>> + .features = CTL_DPU_7_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>> },
>> };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>> index 53db0049eecc..334946c8d4e8 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>> @@ -48,37 +48,37 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
>> {
>> .name = "ctl_0", .id = CTL_0,
>> .base = 0x15000, .len = 0x290,
>> - .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> + .features = CTL_DPU_9_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
>> },
>> {
>> .name = "ctl_1", .id = CTL_1,
>> .base = 0x16000, .len = 0x290,
>> - .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> + .features = CTL_DPU_9_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
>> },
>> {
>> .name = "ctl_2", .id = CTL_2,
>> .base = 0x17000, .len = 0x290,
>> - .features = CTL_SM8550_MASK,
>> + .features = CTL_DPU_9_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
>> },
>> {
>> .name = "ctl_3", .id = CTL_3,
>> .base = 0x18000, .len = 0x290,
>> - .features = CTL_SM8550_MASK,
>> + .features = CTL_DPU_9_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
>> },
>> {
>> .name = "ctl_4", .id = CTL_4,
>> .base = 0x19000, .len = 0x290,
>> - .features = CTL_SM8550_MASK,
>> + .features = CTL_DPU_9_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
>> },
>> {
>> .name = "ctl_5", .id = CTL_5,
>> .base = 0x1a000, .len = 0x290,
>> - .features = CTL_SM8550_MASK,
>> + .features = CTL_DPU_9_MASK,
>> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
>> },
>> };
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 6b78554df30c..3c604f7b88aa 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -65,11 +65,15 @@
>> #define PINGPONG_SDM845_SPLIT_MASK \
>> (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
>>
>> -#define CTL_SC7280_MASK \
>> - (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG))
>> +#define CTL_DPU_0_MASK (0)
>>
>> -#define CTL_SM8550_MASK \
>> - (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
>> +#define CTL_DPU_5_MASK (CTL_DPU_0_MASK | BIT(DPU_CTL_ACTIVE_CFG))
>> +
>> +#define CTL_DPU_7_MASK \
>> + (CTL_DPU_5_MASK | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG))
>> +
>> +#define CTL_DPU_9_MASK \
>> + (CTL_DPU_7_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
>>
>> #define MERGE_3D_SM8150_MASK (0)
>>
next prev parent reply other threads:[~2023-03-30 13:17 UTC|newest]
Thread overview: 127+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-11 23:12 [PATCH v2 00/50] drm/msm/dpu: rework HW catalog Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 01/50] drm/msm/dpu: set DPU_MDP_PERIPH_0_REMOVED for sc8280xp Dmitry Baryshkov
2023-03-16 0:27 ` (subset) " Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 02/50] drm/msm/dpu: disable features unsupported by QCM2290 Dmitry Baryshkov
2023-03-16 0:30 ` (subset) " Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 03/50] drm/msm/dpu: fix typo in in sm8550's dma_sblk_5 Dmitry Baryshkov
2023-02-13 17:37 ` Neil Armstrong
2023-02-24 18:06 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 04/50] drm/msm/dpu: fix len of sc7180 ctl blocks Dmitry Baryshkov
2023-02-24 18:12 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 05/50] drm/msm/dpu: fix sm6115 and qcm2290 mixer width limits Dmitry Baryshkov
2023-02-24 19:11 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 06/50] drm/msm/dpu: correct sm8550 scaler Dmitry Baryshkov
2023-02-13 10:41 ` Neil Armstrong
2023-02-13 11:16 ` Dmitry Baryshkov
2023-02-13 17:36 ` neil.armstrong
2023-02-24 20:51 ` Abhinav Kumar
2023-02-25 23:06 ` Dmitry Baryshkov
2023-02-25 23:27 ` Abhinav Kumar
2023-02-26 0:06 ` Dmitry Baryshkov
2023-02-26 2:10 ` Abhinav Kumar
2023-02-26 12:59 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 07/50] drm/msm/dpu: correct sc8280xp scaler Dmitry Baryshkov
2023-02-25 22:55 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 08/50] drm/msm/dpu: correct sm8450 scaler Dmitry Baryshkov
2023-02-25 22:55 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 09/50] drm/msm/dpu: correct sm8250 and sm8350 scaler Dmitry Baryshkov
2023-02-25 22:59 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 10/50] drm/msm/dpu: correct sm6115 scaler Dmitry Baryshkov
2023-02-25 23:11 ` Abhinav Kumar
2023-02-26 0:01 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 11/50] drm/msm/dpu: drop DPU_DIM_LAYER from MIXER_MSM8998_MASK Dmitry Baryshkov
2023-02-28 23:04 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 12/50] drm/msm/dpu: fix clocks settings for msm8998 SSPP blocks Dmitry Baryshkov
2023-02-25 23:32 ` Abhinav Kumar
2023-02-11 23:12 ` [PATCH v2 13/50] drm/msm/dpu: don't use DPU_CLK_CTRL_CURSORn for DMA SSPP clocks Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 14/50] drm/msm/dpu: Allow variable SSPP/INTF_BLK size Dmitry Baryshkov
2023-02-13 11:01 ` Konrad Dybcio
2023-02-13 11:18 ` Dmitry Baryshkov
2023-03-29 20:01 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 15/50] drm/msm/dpu: constify DSC data structures Dmitry Baryshkov
2023-03-29 19:49 ` [v2,15/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 16/50] drm/msm/dpu: mark remaining pp data as const Dmitry Baryshkov
2023-03-29 20:15 ` [v2,16/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 17/50] drm/msm/dpu: move UBWC/memory configuration to separate struct Dmitry Baryshkov
2023-03-29 20:23 ` [v2,17/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 18/50] drm/msm/dpu: split SM8550 catalog entry to the separate file Dmitry Baryshkov
2023-03-29 20:25 ` [v2,18/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 19/50] drm/msm/dpu: split SM8450 " Dmitry Baryshkov
2023-03-30 11:34 ` [v2,19/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 20/50] drm/msm/dpu: split SC8280XP " Dmitry Baryshkov
2023-03-30 11:39 ` [v2,20/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 21/50] drm/msm/dpu: split SC7280 " Dmitry Baryshkov
2023-03-30 11:41 ` [v2,21/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 22/50] drm/msm/dpu: split SM8350 " Dmitry Baryshkov
2023-03-30 11:46 ` [v2,22/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 23/50] drm/msm/dpu: split SM6115 " Dmitry Baryshkov
2023-03-30 11:47 ` [v2,23/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 24/50] drm/msm/dpu: split QCM2290 " Dmitry Baryshkov
2023-03-30 11:50 ` [v2,24/50] " Konrad Dybcio
2023-03-30 11:52 ` Dmitry Baryshkov
2023-03-30 11:53 ` Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 25/50] drm/msm/dpu: split SC7180 " Dmitry Baryshkov
2023-03-30 11:55 ` [v2,25/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 26/50] drm/msm/dpu: split SM8250 " Dmitry Baryshkov
2023-03-30 12:06 ` [v2,26/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 27/50] drm/msm/dpu: split SC8180X " Dmitry Baryshkov
2023-03-30 12:08 ` [v2,27/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 28/50] drm/msm/dpu: split SM8150 " Dmitry Baryshkov
2023-03-30 12:10 ` [v2,28/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 29/50] drm/msm/dpu: split MSM8998 " Dmitry Baryshkov
2023-03-30 12:14 ` [v2,29/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 30/50] drm/msm/dpu: split SDM845 " Dmitry Baryshkov
2023-03-30 12:19 ` [v2,30/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 31/50] drm/msm/dpu: duplicate sdm845 catalog entries Dmitry Baryshkov
2023-03-30 12:21 ` [v2,31/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 32/50] drm/msm/dpu: duplicate sc7180 " Dmitry Baryshkov
2023-03-30 12:22 ` [v2,32/50] " Konrad Dybcio
2023-03-30 12:24 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 33/50] drm/msm/dpu: duplicate sm8150 " Dmitry Baryshkov
2023-03-30 12:26 ` [v2,33/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 34/50] drm/msm/dpu: duplicate sm8250 " Dmitry Baryshkov
2023-03-30 12:27 ` [v2,34/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 35/50] drm/msm/dpu: duplicate sm8350 " Dmitry Baryshkov
2023-03-30 12:27 ` [v2,35/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 36/50] drm/msm/dpu: use defined symbol for sc8280xp's maxwidth Dmitry Baryshkov
2023-03-30 12:28 ` [v2,36/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 37/50] drm/msm/dpu: enable DPU_CTL_SPLIT_DISPLAY for sc8280xp Dmitry Baryshkov
2023-03-30 12:29 ` [v2,37/50] " Konrad Dybcio
2023-03-30 21:32 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 38/50] drm/msm/dpu: enable DSPP_2/3 for LM_2/3 on sm8450 Dmitry Baryshkov
2023-03-30 12:33 ` [v2,38/50] " Konrad Dybcio
2023-03-30 12:38 ` Dmitry Baryshkov
2023-03-30 12:42 ` Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 39/50] drm/msm/dpu: drop duplicate vig_sblk instances Dmitry Baryshkov
2023-03-07 18:31 ` Dmitry Baryshkov
2023-03-30 12:34 ` [v2,39/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 40/50] drm/msm/dpu: enable DSPP on sc8180x Dmitry Baryshkov
2023-03-30 12:39 ` [v2,40/50] " Konrad Dybcio
2023-03-30 21:46 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 41/50] drm/msm/dpu: deduplicate sc8180x with sm8150 Dmitry Baryshkov
2023-03-30 12:55 ` [v2,41/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 42/50] drm/msm/dpu: deduplicate sm6115 with qcm2290 Dmitry Baryshkov
2023-03-30 12:56 ` [v2,42/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 43/50] drm/msm/dpu: deduplicate sc8280xp with sm8450 Dmitry Baryshkov
2023-03-30 12:59 ` [v2,43/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 44/50] drm/msm/dpu: drop unused macros from hw catalog Dmitry Baryshkov
2023-03-30 13:02 ` [v2,44/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 45/50] drm/msm/dpu: inline IRQ_n_MASK defines Dmitry Baryshkov
2023-03-30 13:08 ` [v2,45/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 46/50] drm/msm/dpu: rename INTF_foo_MASK to contain major DPU version Dmitry Baryshkov
2023-03-30 13:14 ` [v2,46/50] " Konrad Dybcio
2023-03-30 13:25 ` Dmitry Baryshkov
2023-02-11 23:12 ` [PATCH v2 47/50] drm/msm/dpu: rename CTL_foo_MASK " Dmitry Baryshkov
2023-03-30 13:15 ` [v2,47/50] " Konrad Dybcio
2023-03-30 13:16 ` Konrad Dybcio [this message]
2023-03-30 13:26 ` Dmitry Baryshkov
2023-03-30 13:27 ` Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 48/50] drm/msm/dpu: rename VIG and DMA_foo_MASK " Dmitry Baryshkov
2023-03-30 13:24 ` [v2,48/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 49/50] drm/msm/dpu: rename MIXER_foo_MASK " Dmitry Baryshkov
2023-03-30 13:25 ` [v2,49/50] " Konrad Dybcio
2023-02-11 23:12 ` [PATCH v2 50/50] drm/msm/dpu: rename MERGE_3D_foo_MASK " Dmitry Baryshkov
2023-03-30 13:26 ` [v2,50/50] " Konrad Dybcio
2023-03-07 18:02 ` [PATCH v2 00/50] drm/msm/dpu: rework HW catalog Dmitry Baryshkov
2023-03-07 18:20 ` [Freedreno] " Abhinav Kumar
2023-03-16 2:28 ` (subset) " Abhinav Kumar
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