From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
linux-arm-msm@vger.kernel.org, andersson@kernel.org,
agross@kernel.org
Cc: marijn.suijten@somainline.org, Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Akhil P Oommen <quic_akhilpo@quicinc.com>,
Chia-I Wu <olvaffe@gmail.com>,
Douglas Anderson <dianders@chromium.org>,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 13/14] drm/msm/a6xx: Add A619_holi speedbin support
Date: Fri, 17 Feb 2023 23:25:10 +0200 [thread overview]
Message-ID: <5fdb7416-4764-1bae-08b4-31fc2cdd7860@linaro.org> (raw)
In-Reply-To: <20230214173145.2482651-14-konrad.dybcio@linaro.org>
On 14/02/2023 19:31, Konrad Dybcio wrote:
> A619_holi is implemented on at least two SoCs: SM4350 (holi) and SM6375
> (blair). This is what seems to be a first occurrence of this happening,
> but it's easy to overcome by guarding the SoC-specific fuse values with
> of_machine_is_compatible(). Do just that to enable frequency limiting
> on these SoCs.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31 +++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index ffe0fd431a76..94b4d93619ed 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -2094,6 +2094,34 @@ static u32 a618_get_speed_bin(u32 fuse)
> return UINT_MAX;
> }
>
> +static u32 a619_holi_get_speed_bin(u32 fuse)
> +{
> + /*
> + * There are (at least) two SoCs implementing A619_holi: SM4350 (holi)
> + * and SM6375 (blair). Limit the fuse matching to the corresponding
> + * SoC to prevent bogus frequency setting (as improbable as it may be,
> + * given unexpected fuse values are.. unexpected! But still possible.)
> + */
> +
> + if (fuse == 0)
> + return 0;
> +
> + if (of_machine_is_compatible("qcom,sm4350")) {
> + if (fuse == 138)
> + return 1;
> + else if (fuse == 92)
> + return 2;
> + } else if (of_machine_is_compatible("qcom,sm6375")) {
> + if (fuse == 190)
> + return 1;
> + else if (fuse == 177)
> + return 2;
Ugh.
> + } else
> + pr_warn("Unknown SoC implementing A619_holi!\n");
> +
> + return UINT_MAX;
> +}
> +
> static u32 a619_get_speed_bin(u32 fuse)
> {
> if (fuse == 0)
> @@ -2153,6 +2181,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
> if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
> val = a618_get_speed_bin(fuse);
>
> + else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, 1), rev))
I really think it begs to have && !of_find_property(dev->of_node,
"qcom,gmu") here.
> + val = a619_holi_get_speed_bin(fuse);
> +
> else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev))
> val = a619_get_speed_bin(fuse);
>
--
With best wishes
Dmitry
next prev parent reply other threads:[~2023-02-17 21:25 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-14 17:31 [PATCH v2 00/14] GMU-less A6xx support (A610, A619_holi) Konrad Dybcio
2023-02-14 17:31 ` [PATCH v2 01/14] drm/msm/a6xx: De-staticize sptprac en/disable functions Konrad Dybcio
2023-02-17 20:41 ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 02/14] drm/msm/a6xx: Extend UBWC config Konrad Dybcio
2023-02-17 20:46 ` Dmitry Baryshkov
2023-02-17 20:51 ` Konrad Dybcio
2023-02-14 17:31 ` [PATCH v2 03/14] drm/msm/a6xx: Introduce GMU wrapper support Konrad Dybcio
2023-02-17 21:37 ` Dmitry Baryshkov
2023-02-17 21:41 ` Konrad Dybcio
2023-02-17 21:44 ` Dmitry Baryshkov
2023-02-17 21:45 ` Konrad Dybcio
2023-02-14 17:31 ` [PATCH v2 04/14] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init Konrad Dybcio
2023-02-14 17:31 ` [PATCH v2 05/14] drm/msm/adreno: Disable has_cached_coherent for A610/A619_holi Konrad Dybcio
2023-02-17 20:54 ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 06/14] drm/msm/gpu: Use dev_pm_opp_set_rate for non-GMU GPUs Konrad Dybcio
2023-02-17 21:07 ` Dmitry Baryshkov
2023-02-18 11:04 ` Konrad Dybcio
2023-02-18 16:47 ` Dmitry Baryshkov
2023-02-20 9:59 ` Konrad Dybcio
2023-02-20 10:12 ` Konrad Dybcio
2023-02-20 10:45 ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 07/14] drm/msm/a6xx: Add support for A619_holi Konrad Dybcio
2023-02-17 21:19 ` Dmitry Baryshkov
2023-02-17 21:21 ` Konrad Dybcio
2023-02-18 13:04 ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 08/14] drm/msm/a6xx: Add A610 support Konrad Dybcio
2023-02-17 21:42 ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 09/14] drm/msm/a6xx: Fix some A619 tunables Konrad Dybcio
2023-02-17 21:42 ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 10/14] drm/msm/a6xx: Fix up A6XX protected registers Konrad Dybcio
2023-02-14 21:56 ` Rob Clark
2023-02-15 0:10 ` Dmitry Baryshkov
2023-02-15 0:38 ` Konrad Dybcio
2023-02-15 1:28 ` Rob Clark
2023-02-14 17:31 ` [PATCH v2 11/14] drm/msm/a6xx: Enable optional icc voting from OPP tables Konrad Dybcio
2023-02-17 21:19 ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 12/14] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching Konrad Dybcio
2023-02-17 21:20 ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 13/14] drm/msm/a6xx: Add A619_holi speedbin support Konrad Dybcio
2023-02-17 21:25 ` Dmitry Baryshkov [this message]
2023-02-14 17:31 ` [PATCH v2 14/14] drm/msm/a6xx: Add A610 " Konrad Dybcio
2023-02-17 21:25 ` Dmitry Baryshkov
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