Linux ARM-MSM sub-architecture
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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
	linux-arm-msm@vger.kernel.org, andersson@kernel.org,
	agross@kernel.org
Cc: marijn.suijten@somainline.org, Rob Clark <robdclark@gmail.com>,
	Abhinav Kumar <quic_abhinavk@quicinc.com>,
	Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
	Daniel Vetter <daniel@ffwll.ch>,
	Akhil P Oommen <quic_akhilpo@quicinc.com>,
	Emma Anholt <emma@anholt.net>, Chia-I Wu <olvaffe@gmail.com>,
	Dan Carpenter <error27@gmail.com>,
	dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 06/14] drm/msm/gpu: Use dev_pm_opp_set_rate for non-GMU GPUs
Date: Fri, 17 Feb 2023 23:07:05 +0200	[thread overview]
Message-ID: <2e129fd6-d4e5-a955-5355-3ca71166fb33@linaro.org> (raw)
In-Reply-To: <20230214173145.2482651-7-konrad.dybcio@linaro.org>

On 14/02/2023 19:31, Konrad Dybcio wrote:
> Currently we only utilize the OPP table connected to the GPU for
> getting (available) frequencies. We do however need to scale the
> voltage rail(s) accordingly to ensure that we aren't trying to
> run the GPU at 1GHz with a VDD_LOW vote, as that would result in
> an otherwise inexplainable hang.
> 
> Tell the OPP framework that we want to scale the "core" clock
> and swap out the clk_set_rate to a dev_pm_opp_set_rate in
> msm_devfreq_target() to enable usage of required-opps and by
> extension proper voltage level/corner scaling.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 ++++
>   drivers/gpu/drm/msm/msm_gpu_devfreq.c   | 2 +-
>   2 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index ce6b76c45b6f..15e405e4f977 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -1047,6 +1047,10 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>   	const char *gpu_name;
>   	u32 speedbin;
>   
> +	/* This can only be done here, or devm_pm_opp_set_supported_hw will WARN_ON() */
> +	if (!IS_ERR(devm_clk_get(dev, "core")))
> +		devm_pm_opp_set_clkname(dev, "core");

Can we instead move a call to a6xx_set_supported_hw() / check_speed_bin 
after the adreno_gpu_init() ? It will call msm_gpu_init, which in turn 
sets gpu->core_clk.

Ideally you can call devm_pm_opp_set_clkname() from that function. Or 
maybe completely drop gpu->core_clk and always use 
devm_pm_opp_set_clk_rate().

> +
>   	adreno_gpu->funcs = funcs;
>   	adreno_gpu->info = adreno_info(config->rev);
>   	adreno_gpu->gmem = adreno_gpu->info->gmem;
> diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
> index e27dbf12b5e8..ea70c1c32d94 100644
> --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
> +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
> @@ -48,7 +48,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq,
>   		gpu->funcs->gpu_set_freq(gpu, opp, df->suspended);
>   		mutex_unlock(&df->lock);
>   	} else {
> -		clk_set_rate(gpu->core_clk, *freq);
> +		dev_pm_opp_set_rate(dev, *freq);

This is not enough, there are calls to clk_set_rate(gpu->core_clk) in 
msm_gpu.c which are called from the suspend/resume path.

>   	}
>   
>   	dev_pm_opp_put(opp);

-- 
With best wishes
Dmitry


  reply	other threads:[~2023-02-17 21:07 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-14 17:31 [PATCH v2 00/14] GMU-less A6xx support (A610, A619_holi) Konrad Dybcio
2023-02-14 17:31 ` [PATCH v2 01/14] drm/msm/a6xx: De-staticize sptprac en/disable functions Konrad Dybcio
2023-02-17 20:41   ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 02/14] drm/msm/a6xx: Extend UBWC config Konrad Dybcio
2023-02-17 20:46   ` Dmitry Baryshkov
2023-02-17 20:51     ` Konrad Dybcio
2023-02-14 17:31 ` [PATCH v2 03/14] drm/msm/a6xx: Introduce GMU wrapper support Konrad Dybcio
2023-02-17 21:37   ` Dmitry Baryshkov
2023-02-17 21:41     ` Konrad Dybcio
2023-02-17 21:44       ` Dmitry Baryshkov
2023-02-17 21:45         ` Konrad Dybcio
2023-02-14 17:31 ` [PATCH v2 04/14] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init Konrad Dybcio
2023-02-14 17:31 ` [PATCH v2 05/14] drm/msm/adreno: Disable has_cached_coherent for A610/A619_holi Konrad Dybcio
2023-02-17 20:54   ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 06/14] drm/msm/gpu: Use dev_pm_opp_set_rate for non-GMU GPUs Konrad Dybcio
2023-02-17 21:07   ` Dmitry Baryshkov [this message]
2023-02-18 11:04     ` Konrad Dybcio
2023-02-18 16:47       ` Dmitry Baryshkov
2023-02-20  9:59         ` Konrad Dybcio
2023-02-20 10:12           ` Konrad Dybcio
2023-02-20 10:45           ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 07/14] drm/msm/a6xx: Add support for A619_holi Konrad Dybcio
2023-02-17 21:19   ` Dmitry Baryshkov
2023-02-17 21:21     ` Konrad Dybcio
2023-02-18 13:04       ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 08/14] drm/msm/a6xx: Add A610 support Konrad Dybcio
2023-02-17 21:42   ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 09/14] drm/msm/a6xx: Fix some A619 tunables Konrad Dybcio
2023-02-17 21:42   ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 10/14] drm/msm/a6xx: Fix up A6XX protected registers Konrad Dybcio
2023-02-14 21:56   ` Rob Clark
2023-02-15  0:10     ` Dmitry Baryshkov
2023-02-15  0:38       ` Konrad Dybcio
2023-02-15  1:28         ` Rob Clark
2023-02-14 17:31 ` [PATCH v2 11/14] drm/msm/a6xx: Enable optional icc voting from OPP tables Konrad Dybcio
2023-02-17 21:19   ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 12/14] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching Konrad Dybcio
2023-02-17 21:20   ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 13/14] drm/msm/a6xx: Add A619_holi speedbin support Konrad Dybcio
2023-02-17 21:25   ` Dmitry Baryshkov
2023-02-14 17:31 ` [PATCH v2 14/14] drm/msm/a6xx: Add A610 " Konrad Dybcio
2023-02-17 21:25   ` Dmitry Baryshkov

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