[PATCH 0/3] Enable QoS configuration on QCS615

[PATCH 0/3] Enable QoS configuration on QCS615

[Odelu Kukatla]

This series enables QoS configuration for QNOC type device which
can be found on QCS615 platform. It enables QoS configuration
for master ports with predefined priority and urgency forwarding.
This helps in prioritizing the traffic originating from different
interconnect masters at NOC (Network On Chip). 
The system may function normally without this feature. However,
enabling QoS helps optimize latency and bandwidth across subsystems
like CPU, GPU, and multimedia engines, which becomes important in
high-throughput scenarios. This is a feature aimed at performance
enhancement to improve system performance under concurrent workloads.

Odelu Kukatla (3):
  dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to
    enable QoS
  interconnect: qcom: qcs615: enable QoS configuration
  arm64: dts: qcom: talos: Add clocks for QoS configuration

 .../interconnect/qcom,qcs615-rpmh.yaml        |  44 ++++
 arch/arm64/boot/dts/qcom/talos.dtsi           |   3 +
 drivers/interconnect/qcom/qcs615.c            | 247 ++++++++++++++++++
 3 files changed, 294 insertions(+)

-- 
2.43.0

[PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS

[Odelu Kukatla]

Aggre1-noc interconnect node on QCS615 has QoS registers located
inside a block whose interface is clock-gated. For that node,
driver must enable the corresponding clock(s) before accessing
the registers. Add the 'clocks' property so the driver can obtain
and enable the required clock(s).

Only interconnects that have clock‑gated QoS register interface
use this property; it is not applicable to all interconnect nodes.

Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
---
 .../interconnect/qcom,qcs615-rpmh.yaml        | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
index e06404828824..096a9064cc01 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
@@ -34,6 +34,10 @@ properties:
   reg:
     maxItems: 1
 
+  clocks:
+    minItems: 3
+    maxItems: 3
+
 required:
   - compatible
 
@@ -53,6 +57,36 @@ allOf:
       required:
         - reg
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,qcs615-aggre1-noc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre UFS PHY AXI clock
+            - description: aggre USB2 SEC AXI clock
+            - description: aggre USB3 PRIM AXI clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,qcs615-camnoc-virt
+              - qcom,qcs615-config-noc
+              - qcom,qcs615-dc-noc
+              - qcom,qcs615-gem-noc
+              - qcom,qcs615-mc-virt
+              - qcom,qcs615-mmss-noc
+              - qcom,qcs615-system-noc
+    then:
+      properties:
+        clocks: false
+
 unevaluatedProperties: false
 
 examples:
@@ -69,3 +103,13 @@ examples:
         #interconnect-cells = <2>;
         qcom,bcm-voters = <&apps_bcm_voter>;
     };
+
+    aggre1_noc: interconnect@1700000 {
+        compatible = "qcom,qcs615-aggre1-noc";
+        reg = <0x1700000 0x3f200>;
+        #interconnect-cells = <2>;
+        qcom,bcm-voters = <&apps_bcm_voter>;
+        clocks = <&gcc_aggre_ufs_phy_axi_clk>,
+                 <&gcc_aggre_usb2_sec_axi_clk>,
+                 <&gcc_aggre_usb3_prim_axi_clk>;
+    };
-- 
2.43.0

[PATCH 2/3] interconnect: qcom: qcs615: enable QoS configuration

[Odelu Kukatla]

Enable QoS configuration for master ports with predefined priority
and urgency forwarding.

Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
---
 drivers/interconnect/qcom/qcs615.c | 247 +++++++++++++++++++++++++++++
 1 file changed, 247 insertions(+)

diff --git a/drivers/interconnect/qcom/qcs615.c b/drivers/interconnect/qcom/qcs615.c
index 797956eb6ff5..017a6017421f 100644
--- a/drivers/interconnect/qcom/qcs615.c
+++ b/drivers/interconnect/qcom/qcs615.c
@@ -142,6 +142,12 @@ static struct qcom_icc_node qhm_qdss_bam = {
 	.name = "qhm_qdss_bam",
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xc000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -150,6 +156,12 @@ static struct qcom_icc_node qhm_qspi = {
 	.name = "qhm_qspi",
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x17000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -158,6 +170,12 @@ static struct qcom_icc_node qhm_qup0 = {
 	.name = "qhm_qup0",
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x10000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -166,6 +184,12 @@ static struct qcom_icc_node qhm_qup1 = {
 	.name = "qhm_qup1",
 	.channels = 1,
 	.buswidth = 4,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x12000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -174,6 +198,12 @@ static struct qcom_icc_node qnm_cnoc = {
 	.name = "qnm_cnoc",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x4000 },
+		.prio = 2,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -182,6 +212,12 @@ static struct qcom_icc_node qxm_crypto = {
 	.name = "qxm_crypto",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x5000 },
+		.prio = 2,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -190,6 +226,12 @@ static struct qcom_icc_node qxm_ipa = {
 	.name = "qxm_ipa",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x6000 },
+		.prio = 2,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_lpass_snoc },
 };
@@ -198,6 +240,12 @@ static struct qcom_icc_node xm_emac_avb = {
 	.name = "xm_emac_avb",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xa000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -206,6 +254,12 @@ static struct qcom_icc_node xm_pcie = {
 	.name = "xm_pcie",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x13000 },
+		.prio = 0,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_pcie_snoc },
 };
@@ -214,6 +268,12 @@ static struct qcom_icc_node xm_qdss_etr = {
 	.name = "xm_qdss_etr",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xb000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -222,6 +282,12 @@ static struct qcom_icc_node xm_sdc1 = {
 	.name = "xm_sdc1",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xe000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -230,6 +296,12 @@ static struct qcom_icc_node xm_sdc2 = {
 	.name = "xm_sdc2",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x16000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -238,6 +310,12 @@ static struct qcom_icc_node xm_ufs_mem = {
 	.name = "xm_ufs_mem",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x11000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -246,6 +324,12 @@ static struct qcom_icc_node xm_usb2 = {
 	.name = "xm_usb2",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x15000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -254,6 +338,12 @@ static struct qcom_icc_node xm_usb3_0 = {
 	.name = "xm_usb3_0",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xd000 },
+		.prio = 2,
+		.urg_fwd = 0,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_a1noc_snoc },
 };
@@ -356,6 +446,12 @@ static struct qcom_icc_node acm_apps = {
 	.name = "acm_apps",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x2e000, 0x2e100 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 3,
 	.link_nodes = { &qns_gem_noc_snoc, &qns_llcc,
 			&qns_sys_pcie },
@@ -365,6 +461,12 @@ static struct qcom_icc_node acm_gpu_tcu = {
 	.name = "acm_gpu_tcu",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x36000 },
+		.prio = 6,
+		.urg_fwd = 0,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
 };
@@ -373,6 +475,12 @@ static struct qcom_icc_node acm_sys_tcu = {
 	.name = "acm_sys_tcu",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x37000 },
+		.prio = 6,
+		.urg_fwd = 0,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
 };
@@ -389,6 +497,12 @@ static struct qcom_icc_node qnm_gpu = {
 	.name = "qnm_gpu",
 	.channels = 2,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 2,
+		.port_offsets = { 0x34000, 0x34080 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
 };
@@ -397,6 +511,12 @@ static struct qcom_icc_node qnm_mnoc_hf = {
 	.name = "qnm_mnoc_hf",
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x2f000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_llcc },
 };
@@ -405,6 +525,12 @@ static struct qcom_icc_node qnm_mnoc_sf = {
 	.name = "qnm_mnoc_sf",
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x35000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },
 };
@@ -413,6 +539,12 @@ static struct qcom_icc_node qnm_snoc_gc = {
 	.name = "qnm_snoc_gc",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x31000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_llcc },
 };
@@ -421,6 +553,12 @@ static struct qcom_icc_node qnm_snoc_sf = {
 	.name = "qnm_snoc_sf",
 	.channels = 1,
 	.buswidth = 16,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x30000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_llcc },
 };
@@ -445,6 +583,12 @@ static struct qcom_icc_node qxm_camnoc_hf0 = {
 	.name = "qxm_camnoc_hf0",
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xa000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_hf },
 };
@@ -453,6 +597,12 @@ static struct qcom_icc_node qxm_camnoc_hf1 = {
 	.name = "qxm_camnoc_hf1",
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xb000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_hf },
 };
@@ -461,6 +611,12 @@ static struct qcom_icc_node qxm_camnoc_sf = {
 	.name = "qxm_camnoc_sf",
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x9000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns2_mem_noc },
 };
@@ -469,6 +625,12 @@ static struct qcom_icc_node qxm_mdp0 = {
 	.name = "qxm_mdp0",
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xc000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns_mem_noc_hf },
 };
@@ -477,6 +639,12 @@ static struct qcom_icc_node qxm_rot = {
 	.name = "qxm_rot",
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xe000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns2_mem_noc },
 };
@@ -485,6 +653,12 @@ static struct qcom_icc_node qxm_venus0 = {
 	.name = "qxm_venus0",
 	.channels = 1,
 	.buswidth = 32,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xf000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns2_mem_noc },
 };
@@ -493,6 +667,12 @@ static struct qcom_icc_node qxm_venus_arm9 = {
 	.name = "qxm_venus_arm9",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0x11000 },
+		.prio = 0,
+		.urg_fwd = 1,
+	},
 	.num_links = 1,
 	.link_nodes = { &qns2_mem_noc },
 };
@@ -559,6 +739,12 @@ static struct qcom_icc_node qxm_pimem = {
 	.name = "qxm_pimem",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xc000 },
+		.prio = 2,
+		.urg_fwd = 1,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_memnoc_gc, &qxs_imem },
 };
@@ -567,6 +753,12 @@ static struct qcom_icc_node xm_gic = {
 	.name = "xm_gic",
 	.channels = 1,
 	.buswidth = 8,
+	.qosbox = &(const struct qcom_icc_qosbox) {
+		.num_ports = 1,
+		.port_offsets = { 0xd000 },
+		.prio = 2,
+		.urg_fwd = 1,
+	},
 	.num_links = 2,
 	.link_nodes = { &qns_memnoc_gc, &qxs_imem },
 };
@@ -1213,11 +1405,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
 	[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
 };
 
+static const struct regmap_config qcs615_aggre1_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x3f200,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc qcs615_aggre1_noc = {
+	.config = &qcs615_aggre1_noc_regmap_config,
 	.nodes = aggre1_noc_nodes,
 	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
 	.bcms = aggre1_noc_bcms,
 	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+	.qos_requires_clocks = true,
 };
 
 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
@@ -1289,7 +1491,16 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
 	[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
 };
 
+static const struct regmap_config qcs615_config_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x5080,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc qcs615_config_noc = {
+	.config = &qcs615_config_noc_regmap_config,
 	.nodes = config_noc_nodes,
 	.num_nodes = ARRAY_SIZE(config_noc_nodes),
 	.bcms = config_noc_bcms,
@@ -1302,7 +1513,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
 	[SLAVE_LLCC_CFG] = &qhs_llcc,
 };
 
+static const struct regmap_config qcs615_dc_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x3200,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc qcs615_dc_noc = {
+	.config = &qcs615_dc_noc_regmap_config,
 	.nodes = dc_noc_nodes,
 	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
 };
@@ -1331,7 +1551,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
 	[SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
 };
 
+static const struct regmap_config qcs615_gem_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x3e200,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc qcs615_gem_noc = {
+	.config = &qcs615_gem_noc_regmap_config,
 	.nodes = gem_noc_nodes,
 	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
 	.bcms = gem_noc_bcms,
@@ -1376,7 +1605,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
 	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
 };
 
+static const struct regmap_config qcs615_mmss_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x1c100,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc qcs615_mmss_noc = {
+	.config = &qcs615_mmss_noc_regmap_config,
 	.nodes = mmss_noc_nodes,
 	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
 	.bcms = mmss_noc_bcms,
@@ -1418,7 +1656,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
 	[SLAVE_TCU] = &xs_sys_tcu_cfg,
 };
 
+static const struct regmap_config qcs615_system_noc_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x1f300,
+	.fast_io = true,
+};
+
 static const struct qcom_icc_desc qcs615_system_noc = {
+	.config = &qcs615_system_noc_regmap_config,
 	.nodes = system_noc_nodes,
 	.num_nodes = ARRAY_SIZE(system_noc_nodes),
 	.bcms = system_noc_bcms,
-- 
2.43.0

[PATCH 3/3] arm64: dts: qcom: talos: Add clocks for QoS configuration

[Odelu Kukatla]

Add clocks which need to be enabled for configuring QoS on
talos SoC.

Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/talos.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index 75716b4a58d6..a6d7cdd4284d 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -1234,6 +1234,9 @@ aggre1_noc: interconnect@1700000 {
 			compatible = "qcom,qcs615-aggre1-noc";
 			#interconnect-cells = <2>;
 			qcom,bcm-voters = <&apps_bcm_voter>;
+			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
 		};
 
 		mmss_noc: interconnect@1740000 {
-- 
2.43.0

Re: [PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS

[Konrad Dybcio]

On 2/2/26 8:05 AM, Odelu Kukatla wrote:
> Aggre1-noc interconnect node on QCS615 has QoS registers located
> inside a block whose interface is clock-gated. For that node,
> driver must enable the corresponding clock(s) before accessing
> the registers. Add the 'clocks' property so the driver can obtain
> and enable the required clock(s).
> 
> Only interconnects that have clock‑gated QoS register interface
> use this property; it is not applicable to all interconnect nodes.
> 
> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> ---
>  .../interconnect/qcom,qcs615-rpmh.yaml        | 44 +++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
> index e06404828824..096a9064cc01 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
> @@ -34,6 +34,10 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  clocks:
> +    minItems: 3
> +    maxItems: 3
> +
>  required:
>    - compatible
>  
> @@ -53,6 +57,36 @@ allOf:
>        required:
>          - reg
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,qcs615-aggre1-noc
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: aggre UFS PHY AXI clock
> +            - description: aggre USB2 SEC AXI clock
> +            - description: aggre USB3 PRIM AXI clock

Should we also include the IPA clock here?

Konrad

Re: [PATCH 2/3] interconnect: qcom: qcs615: enable QoS configuration

[Dmitry Baryshkov]

On Mon, Feb 02, 2026 at 12:35:33PM +0530, Odelu Kukatla wrote:
> Enable QoS configuration for master ports with predefined priority
> and urgency forwarding.
> 
> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> ---
>  drivers/interconnect/qcom/qcs615.c | 247 +++++++++++++++++++++++++++++
>  1 file changed, 247 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS

[Odelu Kukatla]

On 2/2/2026 4:33 PM, Konrad Dybcio wrote:
> On 2/2/26 8:05 AM, Odelu Kukatla wrote:
>> Aggre1-noc interconnect node on QCS615 has QoS registers located
>> inside a block whose interface is clock-gated. For that node,
>> driver must enable the corresponding clock(s) before accessing
>> the registers. Add the 'clocks' property so the driver can obtain
>> and enable the required clock(s).
>>
>> Only interconnects that have clock‑gated QoS register interface
>> use this property; it is not applicable to all interconnect nodes.
>>
>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
>> ---
>>  .../interconnect/qcom,qcs615-rpmh.yaml        | 44 +++++++++++++++++++
>>  1 file changed, 44 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
>> index e06404828824..096a9064cc01 100644
>> --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
>> @@ -34,6 +34,10 @@ properties:
>>    reg:
>>      maxItems: 1
>>  
>> +  clocks:
>> +    minItems: 3
>> +    maxItems: 3
>> +
>>  required:
>>    - compatible
>>  
>> @@ -53,6 +57,36 @@ allOf:
>>        required:
>>          - reg
>>  
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - qcom,qcs615-aggre1-noc
>> +    then:
>> +      properties:
>> +        clocks:
>> +          items:
>> +            - description: aggre UFS PHY AXI clock
>> +            - description: aggre USB2 SEC AXI clock
>> +            - description: aggre USB3 PRIM AXI clock
> 
> Should we also include the IPA clock here?
> 

Thanks for the review!

For QCS615, the IPA clock is already enabled by the bootloader (xBL) and
kept on during the boot‑up stage. Because of this, we do not need to
explicitly enable the IPA clock in the interconnect driver when
accessing the QoS registers.

Thanks,
Odelu

> Konrad

Re: [PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS

[Konrad Dybcio]

On 2/5/26 7:06 AM, Odelu Kukatla wrote:
> 
> 
> On 2/2/2026 4:33 PM, Konrad Dybcio wrote:
>> On 2/2/26 8:05 AM, Odelu Kukatla wrote:
>>> Aggre1-noc interconnect node on QCS615 has QoS registers located
>>> inside a block whose interface is clock-gated. For that node,
>>> driver must enable the corresponding clock(s) before accessing
>>> the registers. Add the 'clocks' property so the driver can obtain
>>> and enable the required clock(s).
>>>
>>> Only interconnects that have clock‑gated QoS register interface
>>> use this property; it is not applicable to all interconnect nodes.
>>>
>>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
>>> ---

[...]

>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - qcom,qcs615-aggre1-noc
>>> +    then:
>>> +      properties:
>>> +        clocks:
>>> +          items:
>>> +            - description: aggre UFS PHY AXI clock
>>> +            - description: aggre USB2 SEC AXI clock
>>> +            - description: aggre USB3 PRIM AXI clock
>>
>> Should we also include the IPA clock here?
>>
> 
> Thanks for the review!
> 
> For QCS615, the IPA clock is already enabled by the bootloader (xBL) and
> kept on during the boot‑up stage. Because of this, we do not need to
> explicitly enable the IPA clock in the interconnect driver when
> accessing the QoS registers.

Would we need to re-enable it to re-program the hardware if say the
icc module is loaded after unused clk cleanup or after a cx collapse?

Konrad

Re: [PATCH 2/3] interconnect: qcom: qcs615: enable QoS configuration

[Konrad Dybcio]

On 2/2/26 8:05 AM, Odelu Kukatla wrote:
> Enable QoS configuration for master ports with predefined priority
> and urgency forwarding.
> 
> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS

[Odelu Kukatla]

On 2/5/2026 2:31 PM, Konrad Dybcio wrote:
> On 2/5/26 7:06 AM, Odelu Kukatla wrote:
>>
>>
>> On 2/2/2026 4:33 PM, Konrad Dybcio wrote:
>>> On 2/2/26 8:05 AM, Odelu Kukatla wrote:
>>>> Aggre1-noc interconnect node on QCS615 has QoS registers located
>>>> inside a block whose interface is clock-gated. For that node,
>>>> driver must enable the corresponding clock(s) before accessing
>>>> the registers. Add the 'clocks' property so the driver can obtain
>>>> and enable the required clock(s).
>>>>
>>>> Only interconnects that have clock‑gated QoS register interface
>>>> use this property; it is not applicable to all interconnect nodes.
>>>>
>>>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
>>>> ---
> 
> [...]
> 
>>>> +  - if:
>>>> +      properties:
>>>> +        compatible:
>>>> +          contains:
>>>> +            enum:
>>>> +              - qcom,qcs615-aggre1-noc
>>>> +    then:
>>>> +      properties:
>>>> +        clocks:
>>>> +          items:
>>>> +            - description: aggre UFS PHY AXI clock
>>>> +            - description: aggre USB2 SEC AXI clock
>>>> +            - description: aggre USB3 PRIM AXI clock
>>>
>>> Should we also include the IPA clock here?
>>>
>>
>> Thanks for the review!
>>
>> For QCS615, the IPA clock is already enabled by the bootloader (xBL) and
>> kept on during the boot‑up stage. Because of this, we do not need to
>> explicitly enable the IPA clock in the interconnect driver when
>> accessing the QoS registers.
> 
> Would we need to re-enable it to re-program the hardware if say the
> icc module is loaded after unused clk cleanup or after a cx collapse?
> 

IPA clock is not managed by GCC clock controller driver, so
clk_disable_unused does not disable it. As a result, the icc provider
does not need to re enable an IPA clock for QoS access after unused clk
cleanup. And QCS615 does *not* support Cx collapse.

Thanks,
Odelu

> Konrad

Re: [PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS

[Dmitry Baryshkov]

On Thu, Feb 05, 2026 at 03:10:31PM +0530, Odelu Kukatla wrote:
> 
> 
> On 2/5/2026 2:31 PM, Konrad Dybcio wrote:
> > On 2/5/26 7:06 AM, Odelu Kukatla wrote:
> >>
> >>
> >> On 2/2/2026 4:33 PM, Konrad Dybcio wrote:
> >>> On 2/2/26 8:05 AM, Odelu Kukatla wrote:
> >>>> Aggre1-noc interconnect node on QCS615 has QoS registers located
> >>>> inside a block whose interface is clock-gated. For that node,
> >>>> driver must enable the corresponding clock(s) before accessing
> >>>> the registers. Add the 'clocks' property so the driver can obtain
> >>>> and enable the required clock(s).
> >>>>
> >>>> Only interconnects that have clock‑gated QoS register interface
> >>>> use this property; it is not applicable to all interconnect nodes.
> >>>>
> >>>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> >>>> ---
> > 
> > [...]
> > 
> >>>> +  - if:
> >>>> +      properties:
> >>>> +        compatible:
> >>>> +          contains:
> >>>> +            enum:
> >>>> +              - qcom,qcs615-aggre1-noc
> >>>> +    then:
> >>>> +      properties:
> >>>> +        clocks:
> >>>> +          items:
> >>>> +            - description: aggre UFS PHY AXI clock
> >>>> +            - description: aggre USB2 SEC AXI clock
> >>>> +            - description: aggre USB3 PRIM AXI clock
> >>>
> >>> Should we also include the IPA clock here?
> >>>
> >>
> >> Thanks for the review!
> >>
> >> For QCS615, the IPA clock is already enabled by the bootloader (xBL) and
> >> kept on during the boot‑up stage. Because of this, we do not need to
> >> explicitly enable the IPA clock in the interconnect driver when
> >> accessing the QoS registers.
> > 
> > Would we need to re-enable it to re-program the hardware if say the
> > icc module is loaded after unused clk cleanup or after a cx collapse?
> > 
> 
> IPA clock is not managed by GCC clock controller driver, so
> clk_disable_unused does not disable it.

The clk_disable_unused is not limited to the GCC. The clock is managed
by the clk-rpmh, so clk_disable_unused applies to it too. 

> As a result, the icc provider
> does not need to re enable an IPA clock for QoS access after unused clk
> cleanup. And QCS615 does *not* support Cx collapse.

Does lack of CX collapse apply to SM6150?

-- 
With best wishes
Dmitry

Re: [PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS

[Odelu Kukatla]

On 2/5/2026 3:59 PM, Dmitry Baryshkov wrote:
> On Thu, Feb 05, 2026 at 03:10:31PM +0530, Odelu Kukatla wrote:
>>
>>
>> On 2/5/2026 2:31 PM, Konrad Dybcio wrote:
>>> On 2/5/26 7:06 AM, Odelu Kukatla wrote:
>>>>
>>>>
>>>> On 2/2/2026 4:33 PM, Konrad Dybcio wrote:
>>>>> On 2/2/26 8:05 AM, Odelu Kukatla wrote:
>>>>>> Aggre1-noc interconnect node on QCS615 has QoS registers located
>>>>>> inside a block whose interface is clock-gated. For that node,
>>>>>> driver must enable the corresponding clock(s) before accessing
>>>>>> the registers. Add the 'clocks' property so the driver can obtain
>>>>>> and enable the required clock(s).
>>>>>>
>>>>>> Only interconnects that have clock‑gated QoS register interface
>>>>>> use this property; it is not applicable to all interconnect nodes.
>>>>>>
>>>>>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
>>>>>> ---
>>>
>>> [...]
>>>
>>>>>> +  - if:
>>>>>> +      properties:
>>>>>> +        compatible:
>>>>>> +          contains:
>>>>>> +            enum:
>>>>>> +              - qcom,qcs615-aggre1-noc
>>>>>> +    then:
>>>>>> +      properties:
>>>>>> +        clocks:
>>>>>> +          items:
>>>>>> +            - description: aggre UFS PHY AXI clock
>>>>>> +            - description: aggre USB2 SEC AXI clock
>>>>>> +            - description: aggre USB3 PRIM AXI clock
>>>>>
>>>>> Should we also include the IPA clock here?
>>>>>
>>>>
>>>> Thanks for the review!
>>>>
>>>> For QCS615, the IPA clock is already enabled by the bootloader (xBL) and
>>>> kept on during the boot‑up stage. Because of this, we do not need to
>>>> explicitly enable the IPA clock in the interconnect driver when
>>>> accessing the QoS registers.
>>>
>>> Would we need to re-enable it to re-program the hardware if say the
>>> icc module is loaded after unused clk cleanup or after a cx collapse?
>>>
>>
>> IPA clock is not managed by GCC clock controller driver, so
>> clk_disable_unused does not disable it.
> 
> The clk_disable_unused is not limited to the GCC. The clock is managed
> by the clk-rpmh, so clk_disable_unused applies to it too. 
> 

clk_disable_unused()/clk_disable_unused_subtree() does not disable RPMh
managed clocks, so it does not apply to IPA clock.

>> As a result, the icc provider
>> does not need to re enable an IPA clock for QoS access after unused clk
>> cleanup. And QCS615 does *not* support Cx collapse.
> 
> Does lack of CX collapse apply to SM6150?
> 

SM6150, QCS615, and Talos are all names referring to the same underlying
SoC family.

Thanks,
Odelu

Re: [PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS

[Dmitry Baryshkov]

On Fri, Feb 06, 2026 at 10:28:15AM +0530, Odelu Kukatla wrote:
> 
> 
> On 2/5/2026 3:59 PM, Dmitry Baryshkov wrote:
> > On Thu, Feb 05, 2026 at 03:10:31PM +0530, Odelu Kukatla wrote:
> >>
> >>
> >> On 2/5/2026 2:31 PM, Konrad Dybcio wrote:
> >>> On 2/5/26 7:06 AM, Odelu Kukatla wrote:
> >>>>
> >>>>
> >>>> On 2/2/2026 4:33 PM, Konrad Dybcio wrote:
> >>>>> On 2/2/26 8:05 AM, Odelu Kukatla wrote:
> >>>>>> Aggre1-noc interconnect node on QCS615 has QoS registers located
> >>>>>> inside a block whose interface is clock-gated. For that node,
> >>>>>> driver must enable the corresponding clock(s) before accessing
> >>>>>> the registers. Add the 'clocks' property so the driver can obtain
> >>>>>> and enable the required clock(s).
> >>>>>>
> >>>>>> Only interconnects that have clock‑gated QoS register interface
> >>>>>> use this property; it is not applicable to all interconnect nodes.
> >>>>>>
> >>>>>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
> >>>>>> ---
> >>>
> >>> [...]
> >>>
> >>>>>> +  - if:
> >>>>>> +      properties:
> >>>>>> +        compatible:
> >>>>>> +          contains:
> >>>>>> +            enum:
> >>>>>> +              - qcom,qcs615-aggre1-noc
> >>>>>> +    then:
> >>>>>> +      properties:
> >>>>>> +        clocks:
> >>>>>> +          items:
> >>>>>> +            - description: aggre UFS PHY AXI clock
> >>>>>> +            - description: aggre USB2 SEC AXI clock
> >>>>>> +            - description: aggre USB3 PRIM AXI clock
> >>>>>
> >>>>> Should we also include the IPA clock here?
> >>>>>
> >>>>
> >>>> Thanks for the review!
> >>>>
> >>>> For QCS615, the IPA clock is already enabled by the bootloader (xBL) and
> >>>> kept on during the boot‑up stage. Because of this, we do not need to
> >>>> explicitly enable the IPA clock in the interconnect driver when
> >>>> accessing the QoS registers.
> >>>
> >>> Would we need to re-enable it to re-program the hardware if say the
> >>> icc module is loaded after unused clk cleanup or after a cx collapse?
> >>>
> >>
> >> IPA clock is not managed by GCC clock controller driver, so
> >> clk_disable_unused does not disable it.
> > 
> > The clk_disable_unused is not limited to the GCC. The clock is managed
> > by the clk-rpmh, so clk_disable_unused applies to it too. 
> > 
> 
> clk_disable_unused()/clk_disable_unused_subtree() does not disable RPMh
> managed clocks, so it does not apply to IPA clock.

You are describing the current behaviour of one OS. The DTS should be
describing the hardware. Other platforms describe IPA clock used by the
aggre NoC nodes.

> 
> >> As a result, the icc provider
> >> does not need to re enable an IPA clock for QoS access after unused clk
> >> cleanup. And QCS615 does *not* support Cx collapse.
> > 
> > Does lack of CX collapse apply to SM6150?
> > 
> 
> SM6150, QCS615, and Talos are all names referring to the same underlying
> SoC family.

Ack, I was making sure that lack of CX collapse isn't related to IoT vs
mobile case.

-- 
With best wishes
Dmitry

Re: [PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS

[Odelu Kukatla]

On 2/6/2026 12:21 PM, Dmitry Baryshkov wrote:
> On Fri, Feb 06, 2026 at 10:28:15AM +0530, Odelu Kukatla wrote:
>>
>>
>> On 2/5/2026 3:59 PM, Dmitry Baryshkov wrote:
>>> On Thu, Feb 05, 2026 at 03:10:31PM +0530, Odelu Kukatla wrote:
>>>>
>>>>
>>>> On 2/5/2026 2:31 PM, Konrad Dybcio wrote:
>>>>> On 2/5/26 7:06 AM, Odelu Kukatla wrote:
>>>>>>
>>>>>>
>>>>>> On 2/2/2026 4:33 PM, Konrad Dybcio wrote:
>>>>>>> On 2/2/26 8:05 AM, Odelu Kukatla wrote:
>>>>>>>> Aggre1-noc interconnect node on QCS615 has QoS registers located
>>>>>>>> inside a block whose interface is clock-gated. For that node,
>>>>>>>> driver must enable the corresponding clock(s) before accessing
>>>>>>>> the registers. Add the 'clocks' property so the driver can obtain
>>>>>>>> and enable the required clock(s).
>>>>>>>>
>>>>>>>> Only interconnects that have clock‑gated QoS register interface
>>>>>>>> use this property; it is not applicable to all interconnect nodes.
>>>>>>>>
>>>>>>>> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
>>>>>>>> ---
>>>>>
>>>>> [...]
>>>>>
>>>>>>>> +  - if:
>>>>>>>> +      properties:
>>>>>>>> +        compatible:
>>>>>>>> +          contains:
>>>>>>>> +            enum:
>>>>>>>> +              - qcom,qcs615-aggre1-noc
>>>>>>>> +    then:
>>>>>>>> +      properties:
>>>>>>>> +        clocks:
>>>>>>>> +          items:
>>>>>>>> +            - description: aggre UFS PHY AXI clock
>>>>>>>> +            - description: aggre USB2 SEC AXI clock
>>>>>>>> +            - description: aggre USB3 PRIM AXI clock
>>>>>>>
>>>>>>> Should we also include the IPA clock here?
>>>>>>>
>>>>>>
>>>>>> Thanks for the review!
>>>>>>
>>>>>> For QCS615, the IPA clock is already enabled by the bootloader (xBL) and
>>>>>> kept on during the boot‑up stage. Because of this, we do not need to
>>>>>> explicitly enable the IPA clock in the interconnect driver when
>>>>>> accessing the QoS registers.
>>>>>
>>>>> Would we need to re-enable it to re-program the hardware if say the
>>>>> icc module is loaded after unused clk cleanup or after a cx collapse?
>>>>>
>>>>
>>>> IPA clock is not managed by GCC clock controller driver, so
>>>> clk_disable_unused does not disable it.
>>>
>>> The clk_disable_unused is not limited to the GCC. The clock is managed
>>> by the clk-rpmh, so clk_disable_unused applies to it too. 
>>>
>>
>> clk_disable_unused()/clk_disable_unused_subtree() does not disable RPMh
>> managed clocks, so it does not apply to IPA clock.
> 
> You are describing the current behaviour of one OS. The DTS should be
> describing the hardware. Other platforms describe IPA clock used by the
> aggre NoC nodes.
> 

I will update the bindings and the device tree to include the IPA clock
for the Aggre1 NoC node to ensure the driver handles it correctly,
aligning with other platforms. I will send out V2 with these changes.

Thanks,
Odelu
>>
>>>> As a result, the icc provider
>>>> does not need to re enable an IPA clock for QoS access after unused clk
>>>> cleanup. And QCS615 does *not* support Cx collapse.
>>>
>>> Does lack of CX collapse apply to SM6150?
>>>
>>
>> SM6150, QCS615, and Talos are all names referring to the same underlying
>> SoC family.
> 
> Ack, I was making sure that lack of CX collapse isn't related to IoT vs
> mobile case.
>