* [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition
@ 2025-09-05 10:40 Luca Weiss
2025-09-05 10:40 ` [PATCH v3 1/7] dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware Luca Weiss
` (7 more replies)
0 siblings, 8 replies; 16+ messages in thread
From: Luca Weiss @ 2025-09-05 10:40 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Manivannan Sadhasivam, Herbert Xu, David S. Miller,
Vinod Koul, Thomas Gleixner, Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto, Luca Weiss,
Konrad Dybcio
Document various bits of the Milos SoC in the dt-bindings, which don't
really need any other changes.
Then we can add the dtsi for the Milos SoC and finally add a dts for
the newly announced The Fairphone (Gen. 6) smartphone.
Dependencies:
* The dt-bindings should not have any dependencies on any other patches.
* The qcom dts bits depend on most other Milos patchsets I have sent in
conjuction with this one. The exact ones are specified in the b4 deps.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes in v3:
- Rebase on linux-next, drop patches already applied
- Pick up tags
- Drop simple-framebuffer to drop dependency on interconnect patchset,
will add back later
- #interrupt-cells = <4> for intc
- Move protected-clocks to dts
- usb_1: reg size and assigned-clock-rates update
- tsens: reg size & interrupt fixes
- thermal trips cleanup based on review comments
- Link to v2: https://lore.kernel.org/r/20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com
Changes in v2:
- Rebrand SM7635 to Milos as requested: https://lore.kernel.org/linux-arm-msm/aGMI1Zv6D+K+vWZL@hu-bjorande-lv.qualcomm.com/
- Disable pm8550vs instances by default
- Enable gpi_dma by default, sort pinctrl, update gpio-reserved-ranges
style, update USB2.0 comment, newlines before status, remove dummy
panel for simpledrm
- Link to v1: https://lore.kernel.org/r/20250625-sm7635-fp6-initial-v1-0-d9cd322eac1b@fairphone.com
---
Luca Weiss (7):
dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware
dt-bindings: crypto: qcom,prng: document Milos
dt-bindings: qcom,pdc: document the Milos Power Domain Controller
dt-bindings: arm: qcom: Add Milos and The Fairphone (Gen. 6)
arm64: dts: qcom: pm8550vs: Disable different PMIC SIDs by default
arm64: dts: qcom: Add initial Milos dtsi
arm64: dts: qcom: Add The Fairphone (Gen. 6)
Documentation/devicetree/bindings/arm/qcom.yaml | 5 +
.../bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 +
.../devicetree/bindings/crypto/qcom,prng.yaml | 1 +
.../bindings/interrupt-controller/qcom,pdc.yaml | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 790 ++++++
arch/arm64/boot/dts/qcom/milos.dtsi | 2633 ++++++++++++++++++++
arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 8 +
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 16 +
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 16 +
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 16 +
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 16 +
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 16 +
.../dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 16 +
arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 16 +
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 16 +
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 16 +
17 files changed, 3585 insertions(+)
---
base-commit: 87a9e300217e33b2388b9c1ffe99ec454eb6e983
change-id: 20250623-sm7635-fp6-initial-15e40fef53cd
prerequisite-change-id: 20250620-sm7635-remoteprocs-149da64084b8:v4
prerequisite-patch-id: 33c2e4cd2d8e7b9c253b86f6f3c42e4602d16b7d
prerequisite-patch-id: 0688b95e4ac7b2f042023a7cb09e0d8cb7929bb6
prerequisite-patch-id: d7a06ece910e7844c60b910fe8eed30ad2458f34
prerequisite-patch-id: 9105660b1ac9a8cd5834cc82e42dc3aa4e64a029
prerequisite-patch-id: 49135534a379bbbc76b5bc9db9de2d2ab9d387c5
prerequisite-patch-id: ec7c10dc254b52f55557f3000e563c7512a67d48
prerequisite-patch-id: 4c1e65349589e4f90a0977e1cd9524275ffb4bca
Best regards,
--
Luca Weiss <luca.weiss@fairphone.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/7] dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware
2025-09-05 10:40 [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Luca Weiss
@ 2025-09-05 10:40 ` Luca Weiss
2025-09-08 6:56 ` Viresh Kumar
2025-09-05 10:40 ` [PATCH v3 2/7] dt-bindings: crypto: qcom,prng: document Milos Luca Weiss
` (6 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Luca Weiss @ 2025-09-05 10:40 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Manivannan Sadhasivam, Herbert Xu, David S. Miller,
Vinod Koul, Thomas Gleixner, Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto, Luca Weiss
Document the CPUFREQ Hardware on the Milos SoC.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
index 2d42fc3d8ef811368c990977173f41b26535e0c8..22eeaef14f557d615b06ec13e71daf86018fcdc9 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -35,6 +35,7 @@ properties:
- description: v2 of CPUFREQ HW (EPSS)
items:
- enum:
+ - qcom,milos-cpufreq-epss
- qcom,qcs8300-cpufreq-epss
- qcom,qdu1000-cpufreq-epss
- qcom,sa8255p-cpufreq-epss
@@ -169,6 +170,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,milos-cpufreq-epss
- qcom,qcs8300-cpufreq-epss
- qcom,sc7280-cpufreq-epss
- qcom,sm8250-cpufreq-epss
--
2.51.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/7] dt-bindings: crypto: qcom,prng: document Milos
2025-09-05 10:40 [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Luca Weiss
2025-09-05 10:40 ` [PATCH v3 1/7] dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware Luca Weiss
@ 2025-09-05 10:40 ` Luca Weiss
2025-11-04 1:05 ` Bjorn Andersson
2025-09-05 10:40 ` [PATCH v3 3/7] dt-bindings: qcom,pdc: document the Milos Power Domain Controller Luca Weiss
` (5 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Luca Weiss @ 2025-09-05 10:40 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Manivannan Sadhasivam, Herbert Xu, David S. Miller,
Vinod Koul, Thomas Gleixner, Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto, Luca Weiss
Document Milos SoC compatible for the True Random Number Generator.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
index ed7e16bd11d33c16d0adf02c38419dbaee87ac48..0fdef054a1a30c363e0d99518351fb18124904f0 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
@@ -20,6 +20,7 @@ properties:
- qcom,ipq5332-trng
- qcom,ipq5424-trng
- qcom,ipq9574-trng
+ - qcom,milos-trng
- qcom,qcs615-trng
- qcom,qcs8300-trng
- qcom,sa8255p-trng
--
2.51.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/7] dt-bindings: qcom,pdc: document the Milos Power Domain Controller
2025-09-05 10:40 [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Luca Weiss
2025-09-05 10:40 ` [PATCH v3 1/7] dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware Luca Weiss
2025-09-05 10:40 ` [PATCH v3 2/7] dt-bindings: crypto: qcom,prng: document Milos Luca Weiss
@ 2025-09-05 10:40 ` Luca Weiss
2025-11-04 1:05 ` Bjorn Andersson
2025-09-05 10:40 ` [PATCH v3 4/7] dt-bindings: arm: qcom: Add Milos and The Fairphone (Gen. 6) Luca Weiss
` (4 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Luca Weiss @ 2025-09-05 10:40 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Manivannan Sadhasivam, Herbert Xu, David S. Miller,
Vinod Koul, Thomas Gleixner, Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto, Luca Weiss
Document the Power Domain Controller on the Milos SoC.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
index f06b40f88778929579ef9b3b3206f075e140ba96..3f90917a5a4dd9d068ec472565f5009690ea2c5b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
@@ -26,6 +26,7 @@ properties:
compatible:
items:
- enum:
+ - qcom,milos-pdc
- qcom,qcs615-pdc
- qcom,qcs8300-pdc
- qcom,qdu1000-pdc
--
2.51.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 4/7] dt-bindings: arm: qcom: Add Milos and The Fairphone (Gen. 6)
2025-09-05 10:40 [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Luca Weiss
` (2 preceding siblings ...)
2025-09-05 10:40 ` [PATCH v3 3/7] dt-bindings: qcom,pdc: document the Milos Power Domain Controller Luca Weiss
@ 2025-09-05 10:40 ` Luca Weiss
2025-09-05 10:40 ` [PATCH v3 5/7] arm64: dts: qcom: pm8550vs: Disable different PMIC SIDs by default Luca Weiss
` (3 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Luca Weiss @ 2025-09-05 10:40 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Manivannan Sadhasivam, Herbert Xu, David S. Miller,
Vinod Koul, Thomas Gleixner, Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto, Luca Weiss
Document the Milos-based The Fairphone (Gen. 6) smartphone.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 0110be27c4f6602b25aa4feb742bfe62e4a40d51..b4ea462062bfe1ccfb34d22deb1d2407443430d5 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -61,6 +61,11 @@ properties:
- qcom,apq8084-sbc
- const: qcom,apq8084
+ - items:
+ - enum:
+ - fairphone,fp6
+ - const: qcom,milos
+
- items:
- enum:
- microsoft,dempsey
--
2.51.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 5/7] arm64: dts: qcom: pm8550vs: Disable different PMIC SIDs by default
2025-09-05 10:40 [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Luca Weiss
` (3 preceding siblings ...)
2025-09-05 10:40 ` [PATCH v3 4/7] dt-bindings: arm: qcom: Add Milos and The Fairphone (Gen. 6) Luca Weiss
@ 2025-09-05 10:40 ` Luca Weiss
2025-09-05 10:40 ` [PATCH v3 6/7] arm64: dts: qcom: Add initial Milos dtsi Luca Weiss
` (2 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Luca Weiss @ 2025-09-05 10:40 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Manivannan Sadhasivam, Herbert Xu, David S. Miller,
Vinod Koul, Thomas Gleixner, Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto, Luca Weiss,
Konrad Dybcio
Keep the different PMIC definitions in pm8550vs.dtsi disabled by
default, and only enable them in boards explicitly.
This allows to support boards better which only have pm8550vs_c, like
the Milos/SM7635-based Fairphone (Gen. 6).
Note: I assume that at least some of these devices with PM8550VS also
don't have _c, _d, _e and _g, but this patch is keeping the resulting
devicetree the same as before this change, disabling them on boards that
don't actually have those is out of scope for this patch.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 8 ++++++++
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 16 ++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 16 ++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 16 ++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 16 ++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 16 ++++++++++++++++
.../boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 16 ++++++++++++++++
arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 16 ++++++++++++++++
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 16 ++++++++++++++++
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 16 ++++++++++++++++
10 files changed, 152 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
index 6426b431616bde2d960780be2bed4c623af246c2..7b5898c263ad8a687e8c914fbb0072c58799b6b2 100644
--- a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi
@@ -98,6 +98,8 @@ pm8550vs_c: pmic@2 {
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+
pm8550vs_c_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
@@ -122,6 +124,8 @@ pm8550vs_d: pmic@3 {
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+
pm8550vs_d_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
@@ -146,6 +150,8 @@ pm8550vs_e: pmic@4 {
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+
pm8550vs_e_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
@@ -170,6 +176,8 @@ pm8550vs_g: pmic@6 {
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+
pm8550vs_g_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
index e6ac529e6b7216ac4b9e10900c5ddc9a06c9011c..e6ebb643203b62ba0050d11930576023207a2e35 100644
--- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
@@ -366,6 +366,22 @@ &pm8550b_eusb2_repeater {
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&sleep_clk {
clock-frequency = <32764>;
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index b5d7f0cd443a18b167c94e450b5b9412897b2ba2..0c070e7e927c3a8612dbe1fb5c202f8dc2323438 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -1107,6 +1107,22 @@ &pm8550b_eusb2_repeater {
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&pon_pwrkey {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 38f2928f23cc3c1905ceea182270ce882d61eed7..10b7434bb30d707ab9139a060a93210c4a3ec463 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -789,6 +789,22 @@ &pm8550b_eusb2_repeater {
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&qupv3_id_0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index a3f4200a1145d8633944de46dfe3221a13c8ba7c..c562a9b52a609f60dfb3a97db1dba8d6dda6aae2 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -957,6 +957,22 @@ &pm8550b_eusb2_repeater {
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&pon_pwrkey {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
index b4ef40ae2cd956d2c0a1e46d6428aaa6e5d9c4ee..81c02ee27fe998a489d6a3fa67c946987a0ca88c 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
@@ -533,6 +533,22 @@ volume_up_n: volume-up-n-state {
};
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&pon_pwrkey {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
index d90dc7b37c4a74cbfb03c929646fda3381413084..0e6ed6fce614706590ab37eb96c1077622d0d532 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
@@ -661,6 +661,22 @@ focus_n: focus-n-state {
};
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&pm8550vs_g_gpios {
cam_pwr_a_cs: cam-pwr-a-cs-state {
pins = "gpio4";
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index d4e5c95e93395b84292366a6ad8bc1ee7d7c362b..c8f8d492f4c3997232759478c45b916ec1b8ad88 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -1046,6 +1046,22 @@ &pm8550b_eusb2_repeater {
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&pmk8550_rtc {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index c67bbace27439ad67cfb247a88aec633f93f5a6d..bb688a5d21c2d0c8b9fd4ff29e8d85ef9e271883 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -692,6 +692,22 @@ &pm8550b_eusb2_repeater {
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&qupv3_id_1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index d71031cb26e2ecb1bf5c4e8b200e68f2d3b5d3a4..e47b5ad8a9a3a2680406c467531bc896cd1cff81 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -1002,6 +1002,22 @@ &pm8550b_eusb2_repeater {
vdd3-supply = <&vreg_l5b_3p1>;
};
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pm8550vs_d {
+ status = "okay";
+};
+
+&pm8550vs_e {
+ status = "okay";
+};
+
+&pm8550vs_g {
+ status = "okay";
+};
+
&pmk8550_rtc {
status = "okay";
};
--
2.51.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 6/7] arm64: dts: qcom: Add initial Milos dtsi
2025-09-05 10:40 [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Luca Weiss
` (4 preceding siblings ...)
2025-09-05 10:40 ` [PATCH v3 5/7] arm64: dts: qcom: pm8550vs: Disable different PMIC SIDs by default Luca Weiss
@ 2025-09-05 10:40 ` Luca Weiss
2025-09-05 10:40 ` [PATCH v3 7/7] arm64: dts: qcom: Add The Fairphone (Gen. 6) Luca Weiss
2025-11-03 12:14 ` [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Konrad Dybcio
7 siblings, 0 replies; 16+ messages in thread
From: Luca Weiss @ 2025-09-05 10:40 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Manivannan Sadhasivam, Herbert Xu, David S. Miller,
Vinod Koul, Thomas Gleixner, Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto, Luca Weiss
Add a devicetree description for the Milos SoC, which is for example
Snapdragon 7s Gen 3 (SM7635).
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/milos.dtsi | 2633 +++++++++++++++++++++++++++++++++++
1 file changed, 2633 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..e1a51d43943ff4706c1a2722cae71afbceeed73d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -0,0 +1,2633 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#include <dt-bindings/clock/qcom,milos-camcc.h>
+#include <dt-bindings/clock/qcom,milos-dispcc.h>
+#include <dt-bindings/clock/qcom,milos-gcc.h>
+#include <dt-bindings/clock/qcom,milos-gpucc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,milos-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <76800000>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32764>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x0 0x0>;
+
+ clocks = <&cpufreq_hw 0>;
+
+ power-domains = <&cpu_pd0>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+
+ qcom,freq-domain = <&cpufreq_hw 0>;
+
+ #cooling-cells = <2>;
+
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ };
+ };
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x0 0x100>;
+
+ clocks = <&cpufreq_hw 0>;
+
+ power-domains = <&cpu_pd1>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+
+ qcom,freq-domain = <&cpufreq_hw 0>;
+
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x0 0x200>;
+
+ clocks = <&cpufreq_hw 0>;
+
+ power-domains = <&cpu_pd2>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+
+ qcom,freq-domain = <&cpufreq_hw 0>;
+
+ #cooling-cells = <2>;
+
+ l2_2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x0 0x300>;
+
+ clocks = <&cpufreq_hw 0>;
+
+ power-domains = <&cpu_pd3>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_2>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+
+ qcom,freq-domain = <&cpufreq_hw 0>;
+
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x400>;
+
+ clocks = <&cpufreq_hw 1>;
+
+ power-domains = <&cpu_pd4>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_4>;
+ capacity-dmips-mhz = <1670>;
+ dynamic-power-coefficient = <264>;
+
+ qcom,freq-domain = <&cpufreq_hw 1>;
+
+ #cooling-cells = <2>;
+
+ l2_4: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x500>;
+
+ clocks = <&cpufreq_hw 1>;
+
+ power-domains = <&cpu_pd5>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_5>;
+ capacity-dmips-mhz = <1670>;
+ dynamic-power-coefficient = <264>;
+
+ qcom,freq-domain = <&cpufreq_hw 1>;
+
+ #cooling-cells = <2>;
+
+ l2_5: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x600>;
+
+ clocks = <&cpufreq_hw 1>;
+
+ power-domains = <&cpu_pd6>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_6>;
+ capacity-dmips-mhz = <1670>;
+ dynamic-power-coefficient = <264>;
+
+ qcom,freq-domain = <&cpufreq_hw 1>;
+
+ #cooling-cells = <2>;
+
+ l2_6: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x0 0x700>;
+
+ clocks = <&cpufreq_hw 2>;
+
+ power-domains = <&cpu_pd7>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&l2_7>;
+ capacity-dmips-mhz = <1670>;
+ dynamic-power-coefficient = <287>;
+
+ qcom,freq-domain = <&cpufreq_hw 2>;
+
+ #cooling-cells = <2>;
+
+ l2_7: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+
+ core1 {
+ cpu = <&cpu5>;
+ };
+
+ core2 {
+ cpu = <&cpu6>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ silver_cpu_sleep_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "pc";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <250>;
+ exit-latency-us = <700>;
+ min-residency-us = <5200>;
+ local-timer-stop;
+ };
+
+ silver_cpu_sleep_1: cpu-sleep-0-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "silver-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <550>;
+ exit-latency-us = <750>;
+ min-residency-us = <6700>;
+ local-timer-stop;
+ };
+
+ gold_cpu_sleep_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "silver-power-collapse";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <400>;
+ exit-latency-us = <900>;
+ min-residency-us = <5511>;
+ local-timer-stop;
+ };
+
+ gold_cpu_sleep_1: cpu-sleep-1-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <600>;
+ exit-latency-us = <1300>;
+ min-residency-us = <8136>;
+ local-timer-stop;
+ };
+
+ gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-plus-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <600>;
+ exit-latency-us = <1500>;
+ min-residency-us = <8551>;
+ local-timer-stop;
+ };
+ };
+
+ domain-idle-states {
+ cluster_sleep_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <750>;
+ exit-latency-us = <2350>;
+ min-residency-us = <9144>;
+ };
+
+ cluster_sleep_1: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x41003344>;
+ entry-latency-us = <2800>;
+ exit-latency-us = <4400>;
+ min-residency-us = <10150>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-milos", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x19000>;
+ };
+ };
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,milos-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,milos-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0 0 0>;
+ };
+
+ pmu-a520 {
+ compatible = "arm,cortex-a520-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
+ };
+
+ pmu-a720 {
+ compatible = "arm,cortex-a720-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ cpu_pd0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>;
+ };
+
+ cpu_pd1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>;
+ };
+
+ cpu_pd2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>;
+ };
+
+ cpu_pd3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>;
+ };
+
+ cpu_pd4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>;
+ };
+
+ cpu_pd5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>;
+ };
+
+ cpu_pd6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>;
+ };
+
+ cpu_pd7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&gold_plus_cpu_sleep_0>;
+ };
+
+ cluster_pd: power-domain-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gunyah_hyp_mem: gunyah-hyp-region@80000000 {
+ reg = <0x0 0x80000000 0x0 0xe00000>;
+ no-map;
+ };
+
+ xbl_sc_mem: xbl-sc-region@81800000 {
+ reg = <0x0 0x81800000 0x0 0x40000>;
+ no-map;
+ };
+
+ cpucp_fw_mem: cpucp-fw-region@81840000 {
+ reg = <0x0 0x81840000 0x0 0x1c0000>;
+ no-map;
+ };
+
+ xbl_dtlog_mem: xbl-dtlog-region@81a00000 {
+ reg = <0x0 0x81a00000 0x0 0x40000>;
+ no-map;
+ };
+
+ xbl_ramdump_mem: xbl-ramdump-region@81a40000 {
+ reg = <0x0 0x81a40000 0x0 0x1c0000>;
+ no-map;
+ };
+
+ aop_image_mem: aop-image-region@81c00000 {
+ reg = <0x0 0x81c00000 0x0 0x60000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_config_mem: aop-config-region@81c80000 {
+ reg = <0x0 0x81c80000 0x0 0x20000>;
+ no-map;
+ };
+
+ tme_crash_dump_mem: tme-crash-dump-region@81ca0000 {
+ reg = <0x0 0x81ca0000 0x0 0x40000>;
+ no-map;
+ };
+
+ tme_log_mem: tme-log-region@81ce0000 {
+ reg = <0x0 0x81ce0000 0x0 0x4000>;
+ no-map;
+ };
+
+ uefi_log_mem: uefi-log-region@81ce4000 {
+ reg = <0x0 0x81ce4000 0x0 0x10000>;
+ no-map;
+ };
+
+ chipinfo_mem: chipinfo-region@81cf4000 {
+ reg = <0x0 0x81cf4000 0x0 0x1000>;
+ no-map;
+ };
+
+ secdata_apss_mem: secdata-apss-region@81cff000 {
+ reg = <0x0 0x81cff000 0x0 0x1000>;
+ no-map;
+ };
+
+ smem_mem: smem-region@81d00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x81d00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ adsp_mhi_mem: adsp-mhi-region@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x20000>;
+ no-map;
+ };
+
+ pvm_fw_mem: pvm-fw-region@824a0000 {
+ reg = <0x0 0x824a0000 0x0 0x100000>;
+ no-map;
+ };
+
+ hyp_mem_database_mem: hyp-mem-database-region@825a0000 {
+ reg = <0x0 0x825a0000 0x0 0x60000>;
+ no-map;
+ };
+
+ global_sync_mem: global-sync-region@82600000 {
+ reg = <0x0 0x82600000 0x0 0x100000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat-region@82700000 {
+ reg = <0x0 0x82700000 0x0 0x100000>;
+ no-map;
+ };
+
+ qdss_apps_mem: qdss-apps-region@82800000 {
+ reg = <0x0 0x82800000 0x0 0x2000000>;
+ reusable;
+ };
+
+ mpss_mem: mpss-region@8ac00000 {
+ reg = <0x0 0x8ac00000 0x0 0xe600000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb-region@99200000 {
+ reg = <0x0 0x99200000 0x0 0x80000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb-region@99280000 {
+ reg = <0x0 0x99280000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi-region@99300000 {
+ reg = <0x0 0x99300000 0x0 0x2800000>;
+ no-map;
+ };
+
+ wpss_mem: wpss-region@9bb00000 {
+ reg = <0x0 0x9bb00000 0x0 0x1900000>;
+ no-map;
+ };
+
+ video_mem: video-region@9d400000 {
+ reg = <0x0 0x9d400000 0x0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp-region@9db00000 {
+ reg = <0x0 0x9db00000 0x0 0xf00000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9ea00000 {
+ reg = <0x0 0x9ea00000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw-region@9ea80000 {
+ reg = <0x0 0x9ea80000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi-region@9ea90000 {
+ reg = <0x0 0x9ea90000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_microcode_mem: gpu-microcode-region@9ea9a000 {
+ reg = <0x0 0x9ea9a000 0x0 0x2000>;
+ no-map;
+ };
+
+ camera_mem: camera-region@9eb00000 {
+ reg = <0x0 0x9eb00000 0x0 0x800000>;
+ no-map;
+ };
+
+ wlan_msa_mem: wlan-msa-region@a6400000 {
+ reg = <0x0 0xa6400000 0x0 0xc00000>;
+ no-map;
+ };
+
+ cpusys_vm_mem: cpusys-vm-region@e0600000 {
+ reg = <0x0 0xe0600000 0x0 0x400000>;
+ no-map;
+ };
+
+ rmtfs_mem: rmtfs@e1f00000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0xe1f00000 0x0 0x600000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
+ };
+
+ qtee_mem: qtee-region@e8900000 {
+ reg = <0x0 0xe8900000 0x0 0x500000>;
+ no-map;
+ };
+
+ tags_mem: tags-region@e8e00000 {
+ reg = <0x0 0xe8e00000 0x0 0x700000>;
+ no-map;
+ };
+
+ trusted_apps_mem: trusted-apps-region@e9500000 {
+ reg = <0x0 0xe9500000 0x0 0x1200000>;
+ no-map;
+ };
+ };
+
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ smp2p_adsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_adsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ smp2p_cdsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-modem {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ smp2p_modem_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_modem_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_ipa_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_ipa_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-wpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <13>;
+
+ smp2p_wpss_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_wpss_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_wlan_out: wlan-ap-to-wpss {
+ qcom,entry-name = "wlan";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_wlan_in: wlan-wpss-to-ap {
+ qcom,entry-name = "wlan";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ ranges = <0 0 0 0 0x10 0>;
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,milos-gcc";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <0>, /* pcie_0_pipe_clk */
+ <0>, /* pcie_1_pipe_clk */
+ <0>, /* ufs_phy_rx_symbol_0_clk */
+ <0>, /* ufs_phy_rx_symbol_1_clk */
+ <0>, /* ufs_phy_tx_symbol_0_clk */
+ <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ ipcc: mailbox@405000 {
+ compatible = "qcom,milos-ipcc", "qcom,ipcc";
+ reg = <0x0 0x00405000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ #mbox-cells = <2>;
+ };
+
+ gpi_dma1: dma-controller@800000 {
+ compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00800000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x3f>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x36 0x0>;
+ dma-coherent;
+ };
+
+ qupv3_id_1: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x008c0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core";
+
+ iommus = <&apps_smmu 0x23 0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c7: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart11: serial@890000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00890000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart11_default>, <&qup_uart11_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ gpi_dma0: dma-controller@a00000 {
+ compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00a00000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x3e>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x576 0x0>;
+ dma-coherent;
+ };
+
+ qupv3_id_0: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core";
+
+ iommus = <&apps_smmu 0x563 0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ spi0: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c1: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart5: serial@a94000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart5_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ rng: rng@10c3000 {
+ compatible = "qcom,milos-trng", "qcom,trng";
+ reg = <0x0 0x010c3000 0x0 0x1000>;
+ };
+
+ mmss_noc: interconnect@1400000 {
+ compatible = "qcom,milos-mmss-noc";
+ reg = <0x0 0x01400000 0x0 0xdb800>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,milos-cnoc-main";
+ reg = <0x0 0x01500000 0x0 0x14400>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ cnoc_cfg: interconnect@1600000 {
+ compatible = "qcom,milos-cnoc-cfg";
+ reg = <0x0 0x01600000 0x0 0x6e00>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,milos-system-noc";
+ reg = <0x0 0x01680000 0x0 0x40000>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ pcie_anoc: interconnect@16c0000 {
+ compatible = "qcom,milos-pcie-anoc";
+ reg = <0x0 0x016c0000 0x0 0x12400>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,milos-aggre1-noc";
+ reg = <0x0 0x016e0000 0x0 0x16400>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ compatible = "qcom,milos-aggre2-noc";
+ reg = <0x0 0x01700000 0x0 0x1f400>;
+ #interconnect-cells = <2>;
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x20000>;
+
+ #hwlock-cells = <1>;
+ };
+
+ tcsr: clock-controller@1fc0000 {
+ compatible = "qcom,milos-tcsr", "syscon";
+ reg = <0x0 0x01fc0000 0x0 0xa0000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ remoteproc_adsp: remoteproc@3000000 {
+ compatible = "qcom,milos-adsp-pas";
+ reg = <0x0 0x03000000 0x0 0x10000>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
+ power-domain-names = "lcx",
+ "lmx";
+
+ interconnects = <&lpass_ag_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "lpass";
+ qcom,remote-pid = <2>;
+ };
+ };
+
+ lpass_ag_noc: interconnect@3c40000 {
+ compatible = "qcom,milos-lpass-ag-noc";
+ reg = <0x0 0x03c40000 0x0 0x17200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,milos-gpucc";
+ reg = <0x0 0x03d90000 0x0 0x9800>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,milos-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>;
+ clock-names = "hlos",
+ "bus",
+ "iface",
+ "ahb";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ dma-coherent;
+ };
+
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,milos-mpss-pas";
+ reg = <0x0 0x04080000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>,
+ <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MSS>;
+ power-domain-names = "cx",
+ "mss";
+
+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&mpss_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_modem_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "mpss";
+ qcom,remote-pid = <1>;
+ };
+ };
+
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,milos-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ iommus = <&apps_smmu 0x540 0>;
+
+ bus-width = <4>;
+
+ qcom,dll-config = <0x0007442c>;
+ qcom,ddr-config = <0x80040868>;
+
+ dma-coherent;
+
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,milos-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x088e3000 0x0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ status = "disabled";
+ };
+
+ remoteproc_wpss: remoteproc@8a00000 {
+ compatible = "qcom,milos-wpss-pas";
+ reg = <0x0 0x08a00000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 579 IRQ_TYPE_EDGE_RISING 0>,
+ <&smp2p_wpss_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_wpss_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_wpss_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_wpss_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_wpss_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+
+ memory-region = <&wpss_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_wpss_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "wpss";
+ qcom,remote-pid = <13>;
+ };
+ };
+
+ usb_1: usb@a600000 {
+ compatible = "qcom,milos-dwc3", "qcom,snps-dwc3";
+ reg = <0x0 0x0a600000 0x0 0xfc000>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ iommus = <&apps_smmu 0x40 0x0>;
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_cfg SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,is-utmi-l1-suspend;
+ snps,parkmode-disable-ss-quirk;
+ tx-fifo-resize;
+ dma-coherent;
+ usb-role-switch;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+ };
+ };
+
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,milos-videocc";
+ reg = <0x0 0x0aaf0000 0x0 0x10000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&gcc GCC_VIDEO_AHB_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ camcc: clock-controller@adb0000 {
+ compatible = "qcom,milos-camcc";
+ reg = <0x0 0x0adb0000 0x0 0x40000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&gcc GCC_CAMERA_AHB_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,milos-dispcc";
+ reg = <0x0 0x0af00000 0x0 0x20000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+ <0>, /* dsi0_phy_pll_out_byteclk */
+ <0>, /* dsi0_phy_pll_out_dsiclk */
+ <0>, /* dp0_phy_pll_link_clk */
+ <0>; /* dp0_phy_pll_vco_div_clk */
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,milos-pdc", "qcom,pdc";
+ reg = <0x0 0x0b220000 0x0 0x30000>,
+ <0x0 0x174000f0 0x0 0x64>;
+ interrupt-parent = <&intc>;
+
+ qcom,pdc-ranges = <0 480 40>, <40 140 11>, <51 527 47>,
+ <98 609 31>, <129 63 1>, <130 716 12>,
+ <142 251 5>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
+ tsens0: thermal-sensor@c228000 {
+ compatible = "qcom,milos-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c228000 0x0 0x1000>,
+ <0x0 0x0c222000 0x0 0x1000>;
+
+ interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <15>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c229000 {
+ compatible = "qcom,milos-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c229000 0x0 0x1000>,
+ <0x0 0x0c223000 0x0 0x1000>;
+
+ interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <14>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,milos-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0x0 0x0c300000 0x0 0x400>;
+
+ interrupt-parent = <&ipcc>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
+ sram@c3f0000 {
+ compatible = "qcom,rpmh-stats";
+ reg = <0x0 0x0c3f0000 0x0 0x400>;
+ };
+
+ spmi_bus: spmi@c400000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0 0x0c400000 0x0 0x3000>,
+ <0x0 0x0c500000 0x0 0x400000>,
+ <0x0 0x0c440000 0x0 0x80000>,
+ <0x0 0x0c4c0000 0x0 0x10000>,
+ <0x0 0x0c42d000 0x0 0x4000>;
+ reg-names = "core",
+ "chnls",
+ "obsrvr",
+ "intr",
+ "cnfg";
+
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ qcom,bus-id = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,milos-tlmm";
+ reg = <0x0 0x0f100000 0x0 0x300000>;
+
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-ranges = <&tlmm 0 0 168>;
+
+ wakeup-parent = <&pdc>;
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio4", "gpio5";
+ function = "qup0_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio15", "gpio16";
+ function = "qup0_se3";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio32", "gpio33";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio3";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart5_default: qup-uart5-default-state {
+ /* TX, RX */
+ pins = "gpio25", "gpio26";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart11_default: qup-uart11-default-state {
+ /* TX, RX */
+ pins = "gpio50", "gpio51";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart11_cts_rts: qup-uart11-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio48", "gpio49";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "gpio62";
+ function = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio61";
+ function = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio58", "gpio57", "gpio35", "gpio34";
+ function = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "gpio62";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio61";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio58", "gpio57", "gpio35", "gpio34";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>;
+ dma-coherent;
+ };
+
+ intc: interrupt-controller@17100000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x17100000 0x0 0x10000>,
+ <0x0 0x17180000 0x0 0x200000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ #interrupt-cells = <4>;
+ interrupt-controller;
+
+ #redistributor-regions = <1>;
+ redistributor-stride = <0 0x40000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+
+ gic_its: msi-controller@17140000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x17140000 0x0 0x20000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ timer@17420000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x17420000 0x0 0x1000>;
+
+ ranges = <0 0 0 0x20000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ frame@17421000 {
+ reg = <0x17421000 0x1000>,
+ <0x17422000 0x1000>;
+
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <0>;
+ };
+
+ frame@17423000 {
+ reg = <0x17423000 0x1000>;
+
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <1>;
+
+ status = "disabled";
+ };
+
+ frame@17425000 {
+ reg = <0x17425000 0x1000>;
+
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <2>;
+
+ status = "disabled";
+ };
+
+ frame@17427000 {
+ reg = <0x17427000 0x1000>;
+
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <3>;
+
+ status = "disabled";
+ };
+
+ frame@17429000 {
+ reg = <0x17429000 0x1000>;
+
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <4>;
+
+ status = "disabled";
+ };
+
+ frame@1742b000 {
+ reg = <0x1742b000 0x1000>;
+
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <5>;
+
+ status = "disabled";
+ };
+
+ frame@1742d000 {
+ reg = <0x1742d000 0x1000>;
+
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ frame-number = <6>;
+
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@17a00000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x17a00000 0x0 0x10000>,
+ <0x0 0x17a10000 0x0 0x10000>,
+ <0x0 0x17a20000 0x0 0x10000>;
+ reg-names = "drv-0",
+ "drv-1",
+ "drv-2";
+
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ power-domains = <&cluster_pd>;
+
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
+ <WAKE_TCS 2>, <CONTROL_TCS 0>;
+
+ label = "apps_rsc";
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,milos-rpmh-clk";
+
+ clocks = <&xo_board>;
+ clock-names = "xo";
+
+ #clock-cells = <1>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,milos-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp-16 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_low_svs_d1: opp-56 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ rpmhpd_opp_low_svs: opp-64 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp-128 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp-192 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp-256 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp-320 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_turbo: opp-384 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp-416 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+ };
+
+ cpufreq_hw: cpufreq@17d91000 {
+ compatible = "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss";
+ reg = <0x0 0x17d91000 0x0 0x1000>,
+ <0x0 0x17d92000 0x0 0x1000>,
+ <0x0 0x17d93000 0x0 0x1000>;
+ reg-names = "freq-domain0",
+ "freq-domain1",
+ "freq-domain2";
+
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "dcvsh-irq-0",
+ "dcvsh-irq-1",
+ "dcvsh-irq-2";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPLL0>;
+ clock-names = "xo",
+ "alternate";
+
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
+
+ gem_noc: interconnect@24100000 {
+ compatible = "qcom,milos-gem-noc";
+ reg = <0x0 0x24100000 0x0 0xff080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ nsp_noc: interconnect@320c0000 {
+ compatible = "qcom,milos-nsp-noc";
+ reg = <0x0 0x320c0000 0x0 0xe080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ remoteproc_cdsp: remoteproc@32300000 {
+ compatible = "qcom,milos-cdsp-pas";
+ reg = <0x0 0x32300000 0x0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>,
+ <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MX>;
+ power-domain-names = "cx",
+ "mx";
+
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_cdsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "cdsp";
+ qcom,remote-pid = <5>;
+ };
+ };
+ };
+
+ thermal-zones {
+ aoss0-thermal {
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ aoss0-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ aoss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpuss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ cpuss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu4-left-thermal {
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ cpu4-left-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu4-right-thermal {
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ cpu4-right-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-left-thermal {
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ cpu5-left-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-right-thermal {
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ cpu5-right-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-left-thermal {
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cpu6-left-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-right-thermal {
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpu6-right-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-left-thermal {
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpu7-left-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-right-thermal {
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu7-right-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-thermal {
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ cpu0-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-thermal {
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ cpu1-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-thermal {
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ cpu2-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu3-thermal {
+ thermal-sensors = <&tsens0 14>;
+
+ trips {
+ cpu3-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss1-thermal {
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ aoss1-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ aoss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx0-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ nsphvx0-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ nsphvx0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx1-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ nsphmx1-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ nsphmx1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx0-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ nsphmx0-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ nsphmx0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss0-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ gpu0_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ gpuss0-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss1-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ gpu1_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ gpuss1-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ video-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ video-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-thermal {
+ polling-delay-passive = <10>;
+
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ ddr-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ ddr-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera0-thermal {
+ thermal-sensors = <&tsens1 9>;
+
+ trips {
+ camera0-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ camera0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem0-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&tsens1 10>;
+
+ trips {
+ modem0-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ modem0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem1-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&tsens1 11>;
+
+ trips {
+ modem1-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ modem1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem2-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&tsens1 12>;
+
+ trips {
+ modem2-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ modem2-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem3-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&tsens1 13>;
+
+ trips {
+ modem3-hot {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ modem3-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 7/7] arm64: dts: qcom: Add The Fairphone (Gen. 6)
2025-09-05 10:40 [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Luca Weiss
` (5 preceding siblings ...)
2025-09-05 10:40 ` [PATCH v3 6/7] arm64: dts: qcom: Add initial Milos dtsi Luca Weiss
@ 2025-09-05 10:40 ` Luca Weiss
2025-11-03 12:14 ` [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Konrad Dybcio
7 siblings, 0 replies; 16+ messages in thread
From: Luca Weiss @ 2025-09-05 10:40 UTC (permalink / raw)
To: Rafael J. Wysocki, Viresh Kumar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Manivannan Sadhasivam, Herbert Xu, David S. Miller,
Vinod Koul, Thomas Gleixner, Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto, Luca Weiss
Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based
on the Milos/SM7635 SoC.
Supported functionality as of this initial submission:
* Debug UART
* Regulators (PM7550, PM8550VS, PMR735B, PM8008)
* Remoteprocs (ADSP, CDSP, MPSS, WPSS)
* Power Button, Volume Keys, Switch
* PMIC-GLINK (Charger, Fuel gauge, USB-C mode switching)
* Camera flash/torch LED
* SD card
* USB
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 790 +++++++++++++++++++++++
2 files changed, 791 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 0a7c308dec365263bbb7aa5f5cd306dbeacfd3f1..a4223770b755461821c7688cda6fde7dc3ae555d 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb
dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb
+dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
new file mode 100644
index 0000000000000000000000000000000000000000..52895dd9e4fa117aef6822df230ebf644e5f02ba
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
@@ -0,0 +1,790 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+/dts-v1/;
+
+#define PMIV0104_SID 7
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "milos.dtsi"
+#include "pm7550.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmiv0104.dtsi" /* PMIV0108 */
+#include "pmk8550.dtsi" /* PMK7635 */
+#include "pmr735b.dtsi"
+
+/ {
+ model = "The Fairphone (Gen. 6)";
+ compatible = "fairphone,fp6", "qcom,milos";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart5;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&pm7550_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ switch {
+ label = "Switch";
+ gpios = <&tlmm 107 GPIO_ACTIVE_HIGH>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_MUTE_DEVICE>;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,milos-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 131 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+ };
+ };
+ };
+
+ vreg_ff_afvdd_2p8: regulator-ff-afvdd-2p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "ff_afvdd_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 93 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_bob>;
+ };
+
+ vreg_uw_afvdd_2p8: regulator-uw-afvdd-2p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "uw_afvdd_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_bob>;
+ };
+
+ vreg_uw_dvdd: regulator-uw-dvdd {
+ compatible = "regulator-fixed";
+ regulator-name = "uw_dvdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 28 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_s1b>;
+ };
+
+ vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "ois_avdd0_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_bob>;
+ };
+
+ vreg_ois_vdd: regulator-ois-vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "ois_vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ vreg_oled_dvdd_1p2: regulator-oled-dvdd-1p2 {
+ compatible = "regulator-fixed";
+ regulator-name = "oled_dvdd_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ gpio = <&tlmm 54 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vreg_s2b>;
+
+ regulator-boot-on;
+ };
+
+ vreg_s1j: regulator-pm3001a-s1j {
+ compatible = "regulator-fixed";
+ regulator-name = "pm3001a_s1j";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ startup-delay-us = <1000>;
+
+ gpio = <&pmr735b_gpios 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+
+ pinctrl-0 = <&s1j_enable_default>;
+ pinctrl-names = "default";
+ };
+
+ vreg_vtof_ldo_3p3: regulator-vtof-ldo-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtof_ldo_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100>;
+
+ gpio = <&tlmm 76 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ thermal-zones {
+ pm8008-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pm8008>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7550-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1b>;
+ vdd-l2-l3-supply = <&vreg_s3b>;
+ vdd-l4-l5-supply = <&vreg_s2b>;
+ vdd-l6-supply = <&vreg_s2b>;
+ vdd-l7-supply = <&vreg_s1b>;
+ vdd-l8-supply = <&vreg_s1b>;
+ vdd-l9-l10-supply = <&vreg_s1b>;
+ vdd-l11-supply = <&vreg_s1b>;
+ vdd-l12-l14-supply = <&vreg_bob>;
+ vdd-l13-l16-supply = <&vreg_bob>;
+ vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "b";
+
+ vreg_s1b: smps1 {
+ regulator-name = "vreg_s1b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2080000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2b: smps2 {
+ regulator-name = "vreg_s2b";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1408000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3b: smps3 {
+ regulator-name = "vreg_s3b";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <1040000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b: ldo2 {
+ regulator-name = "vreg_l2b";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3b: ldo3 {
+ regulator-name = "vreg_l3b";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b: ldo4 {
+ regulator-name = "vreg_l4b";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b: ldo5 {
+ regulator-name = "vreg_l5b";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b: ldo7 {
+ regulator-name = "vreg_l7b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b: ldo8 {
+ regulator-name = "vreg_l8b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b: ldo9 {
+ regulator-name = "vreg_l9b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b: ldo10 {
+ regulator-name = "vreg_l10b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b: ldo11 {
+ regulator-name = "vreg_l11b";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b: ldo12 {
+ regulator-name = "vreg_l12b";
+ /*
+ * Skip voltage voting for UFS VCC.
+ */
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b: ldo13 {
+ regulator-name = "vreg_l13b";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b: ldo14 {
+ regulator-name = "vreg_l14b";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b: ldo15 {
+ regulator-name = "vreg_l15b";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b: ldo16 {
+ regulator-name = "vreg_l16b";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b: ldo17 {
+ regulator-name = "vreg_l17b";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b: ldo18 {
+ regulator-name = "vreg_l18b";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19b: ldo19 {
+ regulator-name = "vreg_l19b";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l20b: ldo20 {
+ regulator-name = "vreg_l20b";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l21b: ldo21 {
+ regulator-name = "vreg_l21b";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l22b: ldo22 {
+ regulator-name = "vreg_l22b";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l23b: ldo23 {
+ regulator-name = "vreg_l23b";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3b>;
+ vdd-l3-supply = <&vreg_s3b>;
+
+ qcom,pmic-id = "c";
+
+ vreg_l2c: ldo2 {
+ regulator-name = "vreg_l2c";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <650000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmr735b-rpmh-regulators";
+
+ vdd-l1-l2-supply= <&vreg_s3b>;
+ vdd-l3-supply= <&vreg_s3b>;
+ vdd-l4-supply= <&vreg_s1b>;
+ vdd-l5-supply= <&vreg_s2b>;
+ vdd-l6-supply= <&vreg_s2b>;
+ vdd-l7-l8-supply= <&vreg_s2b>;
+ vdd-l9-supply= <&vreg_s3b>;
+ vdd-l10-supply= <&vreg_s1b>;
+ vdd-l11-supply= <&vreg_s3b>;
+ vdd-l12-supply= <&vreg_s3b>;
+
+ qcom,pmic-id = "f";
+
+ vreg_l1f: ldo1 {
+ regulator-name = "vreg_l1f";
+ regulator-min-microvolt = <852000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f: ldo2 {
+ regulator-name = "vreg_l2f";
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f: ldo3 {
+ regulator-name = "vreg_l3f";
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4f: ldo4 {
+ regulator-name = "vreg_l4f";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5f: ldo5 {
+ regulator-name = "vreg_l5f";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6f: ldo6 {
+ regulator-name = "vreg_l6f";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7f: ldo7 {
+ regulator-name = "vreg_l7f";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8f: ldo8 {
+ regulator-name = "vreg_l8f";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9f: ldo9 {
+ regulator-name = "vreg_l9f";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10f: ldo10 {
+ regulator-name = "vreg_l10f";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11f: ldo11 {
+ regulator-name = "vreg_l11f";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <864000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_PCIE_1_AUX_CLK>, <GCC_PCIE_1_AUX_CLK_SRC>,
+ <GCC_PCIE_1_CFG_AHB_CLK>, <GCC_PCIE_1_MSTR_AXI_CLK>,
+ <GCC_PCIE_1_PHY_RCHNG_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,
+ <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,
+ <GCC_PCIE_1_PIPE_DIV2_CLK>, <GCC_PCIE_1_PIPE_DIV2_CLK_SRC>,
+ <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
+};
+
+&i2c1 {
+ /* Samsung NFC @ 0x27 */
+
+ status = "okay";
+};
+
+&i2c3 {
+ /* AW88261FCR amplifier (top) @ 0x34 */
+ /* AW88261FCR amplifier (bottom) @ 0x35 */
+
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+
+ pm8008: pmic@8 {
+ compatible = "qcom,pm8008";
+ reg = <0x8>;
+
+ interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&pmr735b_gpios 3 GPIO_ACTIVE_LOW>;
+
+ vdd-l1-l2-supply = <&vreg_s2b>;
+ vdd-l3-l4-supply = <&vreg_bob>;
+ vdd-l5-supply = <&vreg_bob>;
+ vdd-l6-supply = <&vreg_s1b>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_n_default>;
+ pinctrl-names = "default";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8008 0 0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ #thermal-sensor-cells = <0>;
+
+ regulators {
+ vreg_l1p: ldo1 {
+ regulator-name = "vreg_l1p";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l2p: ldo2 {
+ regulator-name = "vreg_l2p";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1144000>;
+ };
+
+ vreg_l3p: ldo3 {
+ regulator-name = "vreg_l3p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vreg_l4p: ldo4 {
+ regulator-name = "vreg_l4p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l5p: ldo5 {
+ regulator-name = "vreg_l5p";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l6p: ldo6 {
+ regulator-name = "vreg_l6p";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1896000>;
+ };
+
+ vreg_l7p: ldo7 {
+ regulator-name = "vreg_l7p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3400000>;
+ };
+ };
+ };
+
+ /* VL53L3 ToF @ 0x29 */
+ /* AW86938FCR vibrator @ 0x5a */
+};
+
+&pm8550vs_c {
+ status = "okay";
+};
+
+&pmiv0104_eusb2_repeater {
+ vdd18-supply = <&vreg_l7b>;
+ vdd3-supply = <&vreg_l17b>;
+
+ qcom,tune-res-fsdif = /bits/ 8 <0x5>;
+ qcom,tune-usb2-amplitude = /bits/ 8 <0x8>;
+ qcom,tune-usb2-disc-thres = /bits/ 8 <0x7>;
+ qcom,tune-usb2-preem = /bits/ 8 <0x6>;
+};
+
+&pmr735b_gpios {
+ s1j_enable_default: s1j-enable-default-state {
+ pins = "gpio1";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <0>;
+ bias-disable;
+ output-low;
+ };
+
+ pm8008_reset_n_default: pm8008-reset-n-default-state {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-pull-down;
+ };
+};
+
+&pm7550_gpios {
+ volume_up_default: volume-up-default-state {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <1>;
+ bias-pull-up;
+ };
+};
+
+&pm7550_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <350000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <400000>;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/milos/fairphone/fp6/adsp.mbn",
+ "qcom/milos/fairphone/fp6/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/milos/fairphone/fp6/cdsp.mbn",
+ "qcom/milos/fairphone/fp6/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/milos/fairphone/fp6/modem.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_wpss {
+ firmware-name = "qcom/milos/fairphone/fp6/wpss.mbn";
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vreg_l13b>;
+ vqmmc-supply = <&vreg_l23b>;
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
+&spi0 {
+ /* Eswin EPH8621 touchscreen @ 0 */
+};
+
+&tlmm {
+ gpio-reserved-ranges = <8 4>, /* Fingerprint SPI */
+ <13 1>, /* NC */
+ <63 2>; /* WLAN UART */
+
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio65";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pm8008_int_default: pm8008-int-default-state {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usb_1 {
+ dr_mode = "otg";
+
+ /* USB 2.0 only, HW does not support USB 3.x */
+ qcom,select-utmi-as-pipe-clk;
+
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l2b>;
+ vdda12-supply = <&vreg_l4b>;
+
+ phys = <&pmiv0104_eusb2_repeater>;
+
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/7] dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware
2025-09-05 10:40 ` [PATCH v3 1/7] dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware Luca Weiss
@ 2025-09-08 6:56 ` Viresh Kumar
0 siblings, 0 replies; 16+ messages in thread
From: Viresh Kumar @ 2025-09-08 6:56 UTC (permalink / raw)
To: Luca Weiss
Cc: Rafael J. Wysocki, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Herbert Xu, David S. Miller, Vinod Koul,
Thomas Gleixner, Bjorn Andersson, Konrad Dybcio,
~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto
On 05-09-25, 12:40, Luca Weiss wrote:
> Document the CPUFREQ Hardware on the Milos SoC.
>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition
2025-09-05 10:40 [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Luca Weiss
` (6 preceding siblings ...)
2025-09-05 10:40 ` [PATCH v3 7/7] arm64: dts: qcom: Add The Fairphone (Gen. 6) Luca Weiss
@ 2025-11-03 12:14 ` Konrad Dybcio
2025-11-03 12:17 ` Luca Weiss
7 siblings, 1 reply; 16+ messages in thread
From: Konrad Dybcio @ 2025-11-03 12:14 UTC (permalink / raw)
To: Luca Weiss, Rafael J. Wysocki, Viresh Kumar, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Herbert Xu, David S. Miller, Vinod Koul, Thomas Gleixner,
Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto
On 9/5/25 12:40 PM, Luca Weiss wrote:
> Document various bits of the Milos SoC in the dt-bindings, which don't
> really need any other changes.
>
> Then we can add the dtsi for the Milos SoC and finally add a dts for
> the newly announced The Fairphone (Gen. 6) smartphone.
>
> Dependencies:
> * The dt-bindings should not have any dependencies on any other patches.
> * The qcom dts bits depend on most other Milos patchsets I have sent in
> conjuction with this one. The exact ones are specified in the b4 deps.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
FWIW this looks good.. where are we with regards to the dependencies?
Are we waiting for anything else than the PMIV0104 (as part of glymur/
kaanapali)?
Konrad
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition
2025-11-03 12:14 ` [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Konrad Dybcio
@ 2025-11-03 12:17 ` Luca Weiss
2025-11-03 12:23 ` Konrad Dybcio
0 siblings, 1 reply; 16+ messages in thread
From: Luca Weiss @ 2025-11-03 12:17 UTC (permalink / raw)
To: Konrad Dybcio, Luca Weiss, Rafael J. Wysocki, Viresh Kumar,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Herbert Xu, David S. Miller, Vinod Koul,
Thomas Gleixner, Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto
On Mon Nov 3, 2025 at 1:14 PM CET, Konrad Dybcio wrote:
> On 9/5/25 12:40 PM, Luca Weiss wrote:
>> Document various bits of the Milos SoC in the dt-bindings, which don't
>> really need any other changes.
>>
>> Then we can add the dtsi for the Milos SoC and finally add a dts for
>> the newly announced The Fairphone (Gen. 6) smartphone.
>>
>> Dependencies:
>> * The dt-bindings should not have any dependencies on any other patches.
>> * The qcom dts bits depend on most other Milos patchsets I have sent in
>> conjuction with this one. The exact ones are specified in the b4 deps.
>>
>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>> ---
>
> FWIW this looks good.. where are we with regards to the dependencies?
>
> Are we waiting for anything else than the PMIV0104 (as part of glymur/
> kaanapali)?
Hi,
From my side, I'm not aware of any patches that have any unresolved
comments, so I'm essentially just waiting for the correct maintainers to
pick up the variety of dt-bindings patches in this series, and the
PMIV0104 and PM7550 series.
Any advice to make this actually proceed would be appreciated since most
have been waiting for quite a while.
Regards
Luca
>
> Konrad
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition
2025-11-03 12:17 ` Luca Weiss
@ 2025-11-03 12:23 ` Konrad Dybcio
2025-11-03 12:24 ` Konrad Dybcio
0 siblings, 1 reply; 16+ messages in thread
From: Konrad Dybcio @ 2025-11-03 12:23 UTC (permalink / raw)
To: Luca Weiss, Rafael J. Wysocki, Viresh Kumar, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Herbert Xu, David S. Miller, Vinod Koul, Thomas Gleixner,
Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto
On 11/3/25 1:17 PM, Luca Weiss wrote:
> On Mon Nov 3, 2025 at 1:14 PM CET, Konrad Dybcio wrote:
>> On 9/5/25 12:40 PM, Luca Weiss wrote:
>>> Document various bits of the Milos SoC in the dt-bindings, which don't
>>> really need any other changes.
>>>
>>> Then we can add the dtsi for the Milos SoC and finally add a dts for
>>> the newly announced The Fairphone (Gen. 6) smartphone.
>>>
>>> Dependencies:
>>> * The dt-bindings should not have any dependencies on any other patches.
>>> * The qcom dts bits depend on most other Milos patchsets I have sent in
>>> conjuction with this one. The exact ones are specified in the b4 deps.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>
>> FWIW this looks good.. where are we with regards to the dependencies?
>>
>> Are we waiting for anything else than the PMIV0104 (as part of glymur/
>> kaanapali)?
>
> Hi,
>
> From my side, I'm not aware of any patches that have any unresolved
> comments, so I'm essentially just waiting for the correct maintainers to
> pick up the variety of dt-bindings patches in this series, and the
> PMIV0104 and PM7550 series.
>
> Any advice to make this actually proceed would be appreciated since most
> have been waiting for quite a while.
Apparently I misremembered, kaanapali actually uses PMH0101 and PMH0110
and PMH0104, whereas glymur uses pmh0101, pmcx0102, pmh0110 and pmh0104
(it is not easy indeed)
so it looks like PMIV0104 only showed up with your series.. and I'm not
opposed to it, let me leave some review tags there, and I suppose I'll
just ask you to rebase this series on next & make sure the bindings
checker is happy
Konrad
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition
2025-11-03 12:23 ` Konrad Dybcio
@ 2025-11-03 12:24 ` Konrad Dybcio
2025-11-03 12:27 ` Luca Weiss
0 siblings, 1 reply; 16+ messages in thread
From: Konrad Dybcio @ 2025-11-03 12:24 UTC (permalink / raw)
To: Luca Weiss, Rafael J. Wysocki, Viresh Kumar, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Herbert Xu, David S. Miller, Vinod Koul, Thomas Gleixner,
Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto
On 11/3/25 1:23 PM, Konrad Dybcio wrote:
> On 11/3/25 1:17 PM, Luca Weiss wrote:
>> On Mon Nov 3, 2025 at 1:14 PM CET, Konrad Dybcio wrote:
>>> On 9/5/25 12:40 PM, Luca Weiss wrote:
>>>> Document various bits of the Milos SoC in the dt-bindings, which don't
>>>> really need any other changes.
>>>>
>>>> Then we can add the dtsi for the Milos SoC and finally add a dts for
>>>> the newly announced The Fairphone (Gen. 6) smartphone.
>>>>
>>>> Dependencies:
>>>> * The dt-bindings should not have any dependencies on any other patches.
>>>> * The qcom dts bits depend on most other Milos patchsets I have sent in
>>>> conjuction with this one. The exact ones are specified in the b4 deps.
>>>>
>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>>> ---
>>>
>>> FWIW this looks good.. where are we with regards to the dependencies?
>>>
>>> Are we waiting for anything else than the PMIV0104 (as part of glymur/
>>> kaanapali)?
>>
>> Hi,
>>
>> From my side, I'm not aware of any patches that have any unresolved
>> comments, so I'm essentially just waiting for the correct maintainers to
>> pick up the variety of dt-bindings patches in this series, and the
>> PMIV0104 and PM7550 series.
>>
>> Any advice to make this actually proceed would be appreciated since most
>> have been waiting for quite a while.
>
> Apparently I misremembered, kaanapali actually uses PMH0101 and PMH0110
> and PMH0104, whereas glymur uses pmh0101, pmcx0102, pmh0110 and pmh0104
>
> (it is not easy indeed)
>
> so it looks like PMIV0104 only showed up with your series.. and I'm not
> opposed to it, let me leave some review tags there, and I suppose I'll
> just ask you to rebase this series on next & make sure the bindings
> checker is happy
Well I apparently already left the review tags there.. please resend
all of them (2 pmics + this one) as a single v4
Konrad
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition
2025-11-03 12:24 ` Konrad Dybcio
@ 2025-11-03 12:27 ` Luca Weiss
0 siblings, 0 replies; 16+ messages in thread
From: Luca Weiss @ 2025-11-03 12:27 UTC (permalink / raw)
To: Konrad Dybcio, Luca Weiss, Rafael J. Wysocki, Viresh Kumar,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Manivannan Sadhasivam, Herbert Xu, David S. Miller, Vinod Koul,
Thomas Gleixner, Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto
On Mon Nov 3, 2025 at 1:24 PM CET, Konrad Dybcio wrote:
> On 11/3/25 1:23 PM, Konrad Dybcio wrote:
>> On 11/3/25 1:17 PM, Luca Weiss wrote:
>>> On Mon Nov 3, 2025 at 1:14 PM CET, Konrad Dybcio wrote:
>>>> On 9/5/25 12:40 PM, Luca Weiss wrote:
>>>>> Document various bits of the Milos SoC in the dt-bindings, which don't
>>>>> really need any other changes.
>>>>>
>>>>> Then we can add the dtsi for the Milos SoC and finally add a dts for
>>>>> the newly announced The Fairphone (Gen. 6) smartphone.
>>>>>
>>>>> Dependencies:
>>>>> * The dt-bindings should not have any dependencies on any other patches.
>>>>> * The qcom dts bits depend on most other Milos patchsets I have sent in
>>>>> conjuction with this one. The exact ones are specified in the b4 deps.
>>>>>
>>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>>>> ---
>>>>
>>>> FWIW this looks good.. where are we with regards to the dependencies?
>>>>
>>>> Are we waiting for anything else than the PMIV0104 (as part of glymur/
>>>> kaanapali)?
>>>
>>> Hi,
>>>
>>> From my side, I'm not aware of any patches that have any unresolved
>>> comments, so I'm essentially just waiting for the correct maintainers to
>>> pick up the variety of dt-bindings patches in this series, and the
>>> PMIV0104 and PM7550 series.
>>>
>>> Any advice to make this actually proceed would be appreciated since most
>>> have been waiting for quite a while.
>>
>> Apparently I misremembered, kaanapali actually uses PMH0101 and PMH0110
>> and PMH0104, whereas glymur uses pmh0101, pmcx0102, pmh0110 and pmh0104
>>
>> (it is not easy indeed)
>>
>> so it looks like PMIV0104 only showed up with your series.. and I'm not
>> opposed to it, let me leave some review tags there, and I suppose I'll
>> just ask you to rebase this series on next & make sure the bindings
>> checker is happy
>
> Well I apparently already left the review tags there.. please resend
> all of them (2 pmics + this one) as a single v4
Will this help with anything though? Most/all dt-bindings patches have
been unmodified since v2 and haven't been picked up since 13 July...
I can try if you really think it could help...
Regards
Luca
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/7] dt-bindings: crypto: qcom,prng: document Milos
2025-09-05 10:40 ` [PATCH v3 2/7] dt-bindings: crypto: qcom,prng: document Milos Luca Weiss
@ 2025-11-04 1:05 ` Bjorn Andersson
0 siblings, 0 replies; 16+ messages in thread
From: Bjorn Andersson @ 2025-11-04 1:05 UTC (permalink / raw)
To: Luca Weiss
Cc: Rafael J. Wysocki, Viresh Kumar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Manivannan Sadhasivam, Herbert Xu, David S. Miller,
Vinod Koul, Thomas Gleixner, Konrad Dybcio,
~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto
On Fri, Sep 05, 2025 at 12:40:33PM +0200, Luca Weiss wrote:
> Document Milos SoC compatible for the True Random Number Generator.
>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
> index ed7e16bd11d33c16d0adf02c38419dbaee87ac48..0fdef054a1a30c363e0d99518351fb18124904f0 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
> @@ -20,6 +20,7 @@ properties:
> - qcom,ipq5332-trng
> - qcom,ipq5424-trng
> - qcom,ipq9574-trng
> + - qcom,milos-trng
> - qcom,qcs615-trng
> - qcom,qcs8300-trng
> - qcom,sa8255p-trng
>
> --
> 2.51.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/7] dt-bindings: qcom,pdc: document the Milos Power Domain Controller
2025-09-05 10:40 ` [PATCH v3 3/7] dt-bindings: qcom,pdc: document the Milos Power Domain Controller Luca Weiss
@ 2025-11-04 1:05 ` Bjorn Andersson
0 siblings, 0 replies; 16+ messages in thread
From: Bjorn Andersson @ 2025-11-04 1:05 UTC (permalink / raw)
To: Luca Weiss
Cc: Rafael J. Wysocki, Viresh Kumar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Manivannan Sadhasivam, Herbert Xu, David S. Miller,
Vinod Koul, Thomas Gleixner, Konrad Dybcio,
~postmarketos/upstreaming, phone-devel, linux-pm, devicetree,
linux-kernel, linux-arm-msm, linux-crypto
On Fri, Sep 05, 2025 at 12:40:34PM +0200, Luca Weiss wrote:
> Document the Power Domain Controller on the Milos SoC.
>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
> index f06b40f88778929579ef9b3b3206f075e140ba96..3f90917a5a4dd9d068ec472565f5009690ea2c5b 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
> @@ -26,6 +26,7 @@ properties:
> compatible:
> items:
> - enum:
> + - qcom,milos-pdc
> - qcom,qcs615-pdc
> - qcom,qcs8300-pdc
> - qcom,qdu1000-pdc
>
> --
> 2.51.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2025-11-04 1:02 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-05 10:40 [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Luca Weiss
2025-09-05 10:40 ` [PATCH v3 1/7] dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware Luca Weiss
2025-09-08 6:56 ` Viresh Kumar
2025-09-05 10:40 ` [PATCH v3 2/7] dt-bindings: crypto: qcom,prng: document Milos Luca Weiss
2025-11-04 1:05 ` Bjorn Andersson
2025-09-05 10:40 ` [PATCH v3 3/7] dt-bindings: qcom,pdc: document the Milos Power Domain Controller Luca Weiss
2025-11-04 1:05 ` Bjorn Andersson
2025-09-05 10:40 ` [PATCH v3 4/7] dt-bindings: arm: qcom: Add Milos and The Fairphone (Gen. 6) Luca Weiss
2025-09-05 10:40 ` [PATCH v3 5/7] arm64: dts: qcom: pm8550vs: Disable different PMIC SIDs by default Luca Weiss
2025-09-05 10:40 ` [PATCH v3 6/7] arm64: dts: qcom: Add initial Milos dtsi Luca Weiss
2025-09-05 10:40 ` [PATCH v3 7/7] arm64: dts: qcom: Add The Fairphone (Gen. 6) Luca Weiss
2025-11-03 12:14 ` [PATCH v3 0/7] Various dt-bindings for Milos and The Fairphone (Gen. 6) addition Konrad Dybcio
2025-11-03 12:17 ` Luca Weiss
2025-11-03 12:23 ` Konrad Dybcio
2025-11-03 12:24 ` Konrad Dybcio
2025-11-03 12:27 ` Luca Weiss
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