Linux ARM-MSM sub-architecture
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From: Yuanjie Yang <quic_yuanjiey@quicinc.com>
To: Krzysztof Kozlowski <krzk@kernel.org>, <ulf.hansson@linaro.org>,
	<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<bhupesh.sharma@linaro.org>, <andersson@kernel.org>,
	<konradybcio@kernel.org>
Cc: <linux-mmc@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
	<quic_tingweiz@quicinc.com>, <quic_yuanjiey@quicinc.com>
Subject: Re: [PATCH v3 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2
Date: Mon, 25 Nov 2024 16:52:31 +0800	[thread overview]
Message-ID: <Z0Q6z8c3SeXsFNQv@cse-cd02-lnx.ap.qualcomm.com> (raw)
In-Reply-To: <ddedecca-4241-4a5b-876e-a2724d361e74@kernel.org>

On Mon, Nov 25, 2024 at 09:16:02AM +0100, Krzysztof Kozlowski wrote:
> On 25/11/2024 09:06, Yuanjie Yang wrote:
> >>>>>>> +
> >>>>>>> +			resets = <&gcc GCC_SDCC1_BCR>;
> >>>>>>> +
> >>>>>>> +			power-domains = <&rpmhpd RPMHPD_CX>;
> >>>>>>> +			operating-points-v2 = <&sdhc1_opp_table>;
> >>>>>>> +			iommus = <&apps_smmu 0x02c0 0x0>;
> >>>>>>> +			interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
> >>>>>>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> >>>>>>> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> >>>>>>> +					 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
> >>>>>>> +			interconnect-names = "sdhc-ddr",
> >>>>>>> +					     "cpu-sdhc";
> >>>>>>> +
> >>>>>>> +			bus-width = <8>;
> >>>>>>> +			qcom,dll-config = <0x000f642c>;
> >>>>>>> +			qcom,ddr-config = <0x80040868>;
> >>>>>>> +			supports-cqe;
> >>>>>>> +			dma-coherent;
> >>>>>>> +			mmc-ddr-1_8v;
> >>>>>>> +			mmc-hs200-1_8v;
> >>>>>>> +			mmc-hs400-1_8v;
> >>>>>>> +			mmc-hs400-enhanced-strobe;
> >>>>>>
> >>>>>> These are properties of memory, not SoC. If the node is disabled, means
> >>>>>> memory is not attached to the SoC, right?
> >>>>>>
> >>>>>>> +			status = "disabled";
> >>>>> Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc,
> >>>>> they are memory configurations that need to be written to the ioaddr.
> >>>>> And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config,
> >>>>> they indicate the bus speed at which the host contoller can operate.
> >>>>> If the node is disabled, which means Soc don't support these properties.
> >>>> No, that is not the meaning of node is disabled. When node is disabled,
> >>>> it means board does not have attached memory.
> >>>>
> >>>> Move the memory related properties  to the board.
> >>>
> >>> Thanks, Ok I understand, I will move the memory related
> >>> properties(qcom,dll-config and qcom,ddr-config) to the
> >>> board dts in next version.
> >>
> >> What? Why are you talking about these properties? My comment was not
> >> under these!
> > Thanks, Sorry, I may have misunderstood your meaning.
> > Do you mean I need move memory realted properties(bus-width, dma-coherent)
> > to the board dts?
> > When this node's status is okay, then board can set these memory config.
> > I will fix it in next version.
> 
> Keep all discussions public. Where was my comment? Under dma-coherent?
> No. Each comment is in very specific place. I asked about memory
> specific properties.
> 
> I also rephrased it differently already, but maybe not clear enough: you
> cannot have here properties which are not properties of the SoC.
> 
> I am not going to discuss it more in private. Read the netiquette.
> 
> https://people.kernel.org/tglx/notes-about-netiquette

Thanks, Sorry, I accidentally sent the email just now; I didn't mean to send
it privately.

Ok, I agree with your idea. properties which are not of Soc should move
to board dts.

I double check my dts, dtsi. I think I should move properties(bus-width,
mmc-ddr-1_8v, mmc-hs200-1_8v, mmc-hs400-1_8v, mmc-hs400-enhanced-strobe)
to board dts, these properties are just to config Soc. Do you agree my
option?

Thanks again for your time to point out my mistake.

> Best regards,
> Krzysztof

Thanks,
Yuanjie



  parent reply	other threads:[~2024-11-25  8:52 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-22  6:50 [PATCH v3 0/2] Enable SDHC1 and SDHC2 on QCS615 Yuanjie Yang
2024-11-22  6:51 ` [PATCH v3 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 Yuanjie Yang
2024-11-22  7:04   ` Krzysztof Kozlowski
2024-11-22  8:40     ` Yuanjie Yang
2024-11-22 12:35       ` Krzysztof Kozlowski
2024-11-25  2:20         ` Yuanjie Yang
2024-11-25  7:35           ` Krzysztof Kozlowski
     [not found]             ` <Z0Qv8lh1I7yeS4W+@cse-cd02-lnx.ap.qualcomm.com>
     [not found]               ` <ddedecca-4241-4a5b-876e-a2724d361e74@kernel.org>
2024-11-25  8:52                 ` Yuanjie Yang [this message]
2024-11-25 12:50           ` Konrad Dybcio
2024-11-25 13:13   ` Konrad Dybcio
2024-11-26  0:07     ` Dmitry Baryshkov
2024-11-26  9:26       ` Krzysztof Kozlowski
2024-11-28 20:51         ` Konrad Dybcio
2024-11-26  9:07     ` Yuanjie Yang
2024-11-26  9:11       ` Yuanjie Yang
2024-11-22  6:51 ` [PATCH v3 2/2] arm64: dts: qcom: qcs615-ride: enable " Yuanjie Yang

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