[DPU PATCH v3] Higher values of pclk can exceed 32 bits when multiplied by a factor.

[DPU PATCH v3] Higher values of pclk can exceed 32 bits when multiplied by a factor.

[Abhinav Kumar]

Make the pclk_rate u64 to accommodate higher pixel clock
rates.

Changes in v3:
 - Rebased on top of https://patchwork.kernel.org/patch/10348865/

Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index b9f2ef9..596959c 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -669,7 +669,8 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
 	u8 lanes = msm_host->lanes;
 	u32 bpp = dsi_get_bpp(msm_host->format);
-	u32 pclk_rate;
+	u64 pclk_rate;
+	u64 pclk_bpp;
 
 	if (!mode) {
 		pr_err("%s: mode not set\n", __func__);
@@ -689,13 +690,15 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
 	if (is_dual_dsi)
 		pclk_rate /= 2;
 
+	pclk_bpp = pclk_rate * bpp;
 	if (lanes > 0) {
-		msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
+		do_div(pclk_bpp, (8 * lanes));
 	} else {
 		pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
-		msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
+		do_div(pclk_bpp, 8);
 	}
 	msm_host->pixel_clk_rate = pclk_rate;
+	msm_host->byte_clk_rate = pclk_bpp;
 
 	DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
 				msm_host->byte_clk_rate);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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Re: [DPU PATCH v3] Higher values of pclk can exceed 32 bits when multiplied by a factor.

[Jani Nikula]

On Fri, 01 Jun 2018, Abhinav Kumar <abhinavk@codeaurora.org> wrote:
> Make the pclk_rate u64 to accommodate higher pixel clock
> rates.
>
> Changes in v3:
>  - Rebased on top of https://patchwork.kernel.org/patch/10348865/
>
> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>

Please have a look at the output of

$ git log --pretty=%s -- drivers/gpu/drm/msm/dsi/dsi_host.c

to give you an idea how to prefix your commit subject.


Thanks,
Jani.


> ---
>  drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index b9f2ef9..596959c 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -669,7 +669,8 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
>  	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
>  	u8 lanes = msm_host->lanes;
>  	u32 bpp = dsi_get_bpp(msm_host->format);
> -	u32 pclk_rate;
> +	u64 pclk_rate;
> +	u64 pclk_bpp;
>  
>  	if (!mode) {
>  		pr_err("%s: mode not set\n", __func__);
> @@ -689,13 +690,15 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
>  	if (is_dual_dsi)
>  		pclk_rate /= 2;
>  
> +	pclk_bpp = pclk_rate * bpp;
>  	if (lanes > 0) {
> -		msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
> +		do_div(pclk_bpp, (8 * lanes));
>  	} else {
>  		pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
> -		msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
> +		do_div(pclk_bpp, 8);
>  	}
>  	msm_host->pixel_clk_rate = pclk_rate;
> +	msm_host->byte_clk_rate = pclk_bpp;
>  
>  	DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
>  				msm_host->byte_clk_rate);

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [DPU PATCH v3] Higher values of pclk can exceed 32 bits when multiplied by a factor.

[abhinavk]

Hi Jani

thanks for pointing it out.

I have fixed it and uploaded v4.

Abhinav
On 2018-06-07 05:19, Jani Nikula wrote:
> On Fri, 01 Jun 2018, Abhinav Kumar <abhinavk@codeaurora.org> wrote:
>> Make the pclk_rate u64 to accommodate higher pixel clock
>> rates.
>> 
>> Changes in v3:
>>  - Rebased on top of https://patchwork.kernel.org/patch/10348865/
>> 
>> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> 
> Please have a look at the output of
> 
> $ git log --pretty=%s -- drivers/gpu/drm/msm/dsi/dsi_host.c
> 
> to give you an idea how to prefix your commit subject.
> 
> 
> Thanks,
> Jani.
> 
> 
>> ---
>>  drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++++++---
>>  1 file changed, 6 insertions(+), 3 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
>> b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> index b9f2ef9..596959c 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> @@ -669,7 +669,8 @@ static int dsi_calc_clk_rate(struct msm_dsi_host 
>> *msm_host, bool is_dual_dsi)
>>  	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
>>  	u8 lanes = msm_host->lanes;
>>  	u32 bpp = dsi_get_bpp(msm_host->format);
>> -	u32 pclk_rate;
>> +	u64 pclk_rate;
>> +	u64 pclk_bpp;
>> 
>>  	if (!mode) {
>>  		pr_err("%s: mode not set\n", __func__);
>> @@ -689,13 +690,15 @@ static int dsi_calc_clk_rate(struct msm_dsi_host 
>> *msm_host, bool is_dual_dsi)
>>  	if (is_dual_dsi)
>>  		pclk_rate /= 2;
>> 
>> +	pclk_bpp = pclk_rate * bpp;
>>  	if (lanes > 0) {
>> -		msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
>> +		do_div(pclk_bpp, (8 * lanes));
>>  	} else {
>>  		pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
>> -		msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
>> +		do_div(pclk_bpp, 8);
>>  	}
>>  	msm_host->pixel_clk_rate = pclk_rate;
>> +	msm_host->byte_clk_rate = pclk_bpp;
>> 
>>  	DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
>>  				msm_host->byte_clk_rate);
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