Linux ARM-MSM sub-architecture
 help / color / mirror / Atom feed
From: Brian Norris <briannorris@chromium.org>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH 3/5] PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller
Date: Wed, 3 Dec 2025 17:51:06 -0800	[thread overview]
Message-ID: <aTDpCpLUzxnAmvt6@google.com> (raw)
In-Reply-To: <20251109-remove_cap-v1-3-2208f46f4dc2@oss.qualcomm.com>

Hi,

On Sun, Nov 09, 2025 at 10:59:42PM -0800, Qiang Yu wrote:
> Some platforms may not support ITS (Interrupt Translation Service) and
> MBI (Message Based Interrupt), or there are not enough available empty SPI
> lines for MBI, in which case the msi-map and msi-parent property will not
> be provided in device tree node. For those cases, the DWC PCIe driver
> defaults to using the iMSI-RX module as MSI controller. However, due to
> DWC IP design, iMSI-RX cannot generate MSI interrupts for Root Ports even
> when MSI is properly configured and supported as iMSI-RX will only monitor
> and intercept incoming MSI TLPs from PCIe link, but the memory write
> generated by Root Port are internal system bus transactions instead of
> PCIe TLPs, so they are ignored.
> 
> This leads to interrupts such as PME, AER from the Root Port not received
> on the host and the users have to resort to workarounds such as passing
> "pcie_pme=nomsi" cmdline parameter.
> 
> To ensure reliable interrupt handling, remove MSI and MSI-X capabilities
> from Root Ports when using iMSI-RX as MSI controller, which is indicated
> by has_msi_ctrl == true. This forces a fallback to INTx interrupts,

But "has_msi_ctrl == false" does not necessarily mean it's using an
external MSI controller, does it? It could just mean that there's some
per-SoC customization needed via the .msi_init() hook.

In practice, that's only pci-keystone.c though, and it's not really
clear if that's some modified version of iMSI-RX, or something else
entirely. At any rate, I suppose it's best to only tweak the things we
know about -- unmodified DWC iMSI-RX support.

> eliminating the need for manual kernel command line workarounds.
> 
> With this behavior:
> - Platforms with ITS/MBI support use ITS/MBI MSI for interrupts from all
>   components.
> - Platforms without ITS/MBI support fall back to INTx for Root Ports and
>   use iMSI-RX for other PCI devices.
> 
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 20c9333bcb1c4812e2fd96047a49944574df1e6f..3724aa7f9b356bfba33a6515e2c62a3170aef1e9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -1083,6 +1083,16 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
>  
>  	dw_pcie_dbi_ro_wr_dis(pci);
>  
> +	/*
> +	 * If iMSI-RX module is used as the MSI controller, remove MSI and
> +	 * MSI-X capabilities from PCIe Root Ports to ensure fallback to INTx
> +	 * interrupt handling.
> +	 */

Personally, I'd suggest including more of the "why?" in this comment, as
the "why?" is pretty perplexing to an uninitiated reader.

Maybe:

	/*
	 * The iMSI-RX module does not support MSI or MSI-X generated by
	 * the root port. If iMSI-RX is used as the MSI controller,
	 * remove the MSI and MSI-X capabilities to fall back to INTx
	 * instead.
	 */

> +	if (pp->has_msi_ctrl) {
> +		dw_pcie_remove_capability(pci, PCI_CAP_ID_MSI);
> +		dw_pcie_remove_capability(pci, PCI_CAP_ID_MSIX);

Removing the capability structure is a neat idea. I had prototyped
solving this problem by adding a new PCI_MSI_FLAGS_* quirk, but that was
a lot more invasive. I like this idea instead!

This looks good to me, although maybe the comment could be updated. Feel
free to carry my:

Reviewed-by: Brian Norris <briannorris@chromium.org>

I'd also note, not all devices currently actually define their INTx
interrupts (such as ... my current test devices :( ), and so
pcie_init_service_irqs() / portdrv.c may fail entirely, since it can't
really provide any services if there are no IRQs for those services.
That does have at least one bad side effect: that the port won't be
configured for runtime PM and won't ever enter D3.

I wonder if we should allow pcie_port_device_register() to succeed even
if it ends up with an empty 'capabilities' / no services.

Brian

> +	}
> +
>  	return 0;
>  }
>  EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
> 
> -- 
> 2.34.1
> 
> 

  parent reply	other threads:[~2025-12-04  1:51 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-10  6:59 [PATCH 0/5] PCI: Remove unsupported or incomplete PCIe Capabilities Qiang Yu
2025-11-10  6:59 ` [PATCH 1/5] PCI: Add preceding capability position support and update drivers Qiang Yu
2025-11-10  6:59 ` [PATCH 2/5] PCI: dwc: Add new APIs to remove standard and extended Capability Qiang Yu
2025-12-23  7:24   ` Niklas Cassel
2025-12-24  6:20     ` Qiang Yu
2025-12-26 21:07   ` Bjorn Helgaas
2025-12-27  5:10     ` Manivannan Sadhasivam
2025-12-28  7:49     ` Qiang Yu
2026-01-09  7:59     ` Qiang Yu
2025-11-10  6:59 ` [PATCH 3/5] PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller Qiang Yu
2025-11-20 11:18   ` Manivannan Sadhasivam
2025-11-20 14:06   ` Shawn Lin
2025-11-20 17:00     ` Manivannan Sadhasivam
2025-11-21  4:04       ` Shawn Lin
2025-11-21  7:56         ` Qiang Yu
2025-11-28  9:57         ` Qiang Yu
2025-11-28 10:02           ` Shawn Lin
2025-12-04  1:27           ` Brian Norris
2025-12-26 21:25       ` Bjorn Helgaas
2025-12-27  4:58         ` Manivannan Sadhasivam
2025-12-04  1:51   ` Brian Norris [this message]
2025-12-18  7:31     ` Manivannan Sadhasivam
2025-12-26 21:31   ` Bjorn Helgaas
2025-12-27  5:21     ` Manivannan Sadhasivam
2025-12-28  7:02       ` Qiang Yu
2025-11-10  6:59 ` [PATCH 4/5] PCI: qcom: Remove MSI-X Capability for Root Ports Qiang Yu
2025-11-10  6:59 ` [PATCH 5/5] PCI: qcom: Remove DPC Extended Capability Qiang Yu
2025-12-18  7:35 ` [PATCH 0/5] PCI: Remove unsupported or incomplete PCIe Capabilities Manivannan Sadhasivam

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=aTDpCpLUzxnAmvt6@google.com \
    --to=briannorris@chromium.org \
    --cc=bhelgaas@google.com \
    --cc=jingoohan1@gmail.com \
    --cc=kwilczynski@kernel.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lpieralisi@kernel.org \
    --cc=mani@kernel.org \
    --cc=qiang.yu@oss.qualcomm.com \
    --cc=robh@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox