Re: [PATCH 3/5] PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller

[Bjorn Helgaas <helgaas@kernel.org>]

On Thu, Nov 20, 2025 at 10:30:41PM +0530, Manivannan Sadhasivam wrote:
> On Thu, Nov 20, 2025 at 10:06:03PM +0800, Shawn Lin wrote:
> > 在 2025/11/10 星期一 14:59, Qiang Yu 写道:
> > > Some platforms may not support ITS (Interrupt Translation Service) and
> > > MBI (Message Based Interrupt), or there are not enough available empty SPI
> > > lines for MBI, in which case the msi-map and msi-parent property will not
> > > be provided in device tree node. For those cases, the DWC PCIe driver
> > > defaults to using the iMSI-RX module as MSI controller. However, due to
> > > DWC IP design, iMSI-RX cannot generate MSI interrupts for Root Ports even
> > > when MSI is properly configured and supported as iMSI-RX will only monitor
> > > and intercept incoming MSI TLPs from PCIe link, but the memory write
> > > generated by Root Port are internal system bus transactions instead of
> > > PCIe TLPs, so they are ignored.

> > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > @@ -1083,6 +1083,16 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
> > >   	dw_pcie_dbi_ro_wr_dis(pci);
> > > +	/*
> > > +	 * If iMSI-RX module is used as the MSI controller, remove MSI and
> > > +	 * MSI-X capabilities from PCIe Root Ports to ensure fallback to INTx
> > > +	 * interrupt handling.
> > > +	 */
> > > +	if (pp->has_msi_ctrl) {
> > 
> > Isn't has_msi_ctrl means you have something like GIC-ITS
> > support instead of iMSI module? Am I missing anything?
> 
> It is the other way around. Presence of this flag means, iMSI-RX is
> used. But I think the driver should clear the CAPs irrespective of
> this flag.

I didn't see any response to this.  Is there a case where we want to
preserve these capabilities?  To ask another way, is there some
platform where DWC-based Root Ports can generate MSIs themselves?

> > > +		dw_pcie_remove_capability(pci, PCI_CAP_ID_MSI);
> > > +		dw_pcie_remove_capability(pci, PCI_CAP_ID_MSIX);