* [PATCH] interconnect: qcom: sm8650: enable QoS configuration
@ 2025-04-07 15:16 Neil Armstrong
2025-04-14 17:08 ` Georgi Djakov
2025-05-19 8:23 ` Pengyu Luo
0 siblings, 2 replies; 6+ messages in thread
From: Neil Armstrong @ 2025-04-07 15:16 UTC (permalink / raw)
To: Georgi Djakov; +Cc: linux-arm-msm, linux-pm, linux-kernel, Neil Armstrong
Enable QoS configuration for master ports with predefined values
for priority and urgency forwarding.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/interconnect/qcom/sm8650.c | 327 +++++++++++++++++++++++++++++++++++++
1 file changed, 327 insertions(+)
diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c
index 20ac5bc5e1fbafe74800ad6f22839bac006ca7db..f6911891503a7ed65be8bc37ed600e87d4cfcc42 100644
--- a/drivers/interconnect/qcom/sm8650.c
+++ b/drivers/interconnect/qcom/sm8650.c
@@ -17,20 +17,45 @@
#include "icc-rpmh.h"
#include "sm8650.h"
+static const struct regmap_config icc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .fast_io = true,
+};
+
+static struct qcom_icc_qosbox qhm_qspi_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xc000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
.id = SM8650_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
+ .qosbox = &qhm_qspi_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A1NOC_SNOC },
};
+static struct qcom_icc_qosbox qhm_qup1_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xd000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
.id = SM8650_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
+ .qosbox = &qhm_qup1_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A1NOC_SNOC },
};
@@ -44,65 +69,128 @@ static struct qcom_icc_node qxm_qup02 = {
.links = { SM8650_SLAVE_A1NOC_SNOC },
};
+static struct qcom_icc_qosbox xm_sdc4_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xe000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
.id = SM8650_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_sdc4_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A1NOC_SNOC },
};
+static struct qcom_icc_qosbox xm_ufs_mem_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xf000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
.id = SM8650_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 16,
+ .qosbox = &xm_ufs_mem_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A1NOC_SNOC },
};
+static struct qcom_icc_qosbox xm_usb3_0_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x10000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
.id = SM8650_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_usb3_0_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A1NOC_SNOC },
};
+static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x12000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.id = SM8650_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
+ .qosbox = &qhm_qdss_bam_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A2NOC_SNOC },
};
+static struct qcom_icc_qosbox qhm_qup2_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x13000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
.id = SM8650_MASTER_QUP_2,
.channels = 1,
.buswidth = 4,
+ .qosbox = &qhm_qup2_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A2NOC_SNOC },
};
+static struct qcom_icc_qosbox qxm_crypto_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x15000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
.id = SM8650_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qxm_crypto_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A2NOC_SNOC },
};
+static struct qcom_icc_qosbox qxm_ipa_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x16000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
.id = SM8650_MASTER_IPA,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qxm_ipa_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A2NOC_SNOC },
};
@@ -116,29 +204,56 @@ static struct qcom_icc_node qxm_sp = {
.links = { SM8650_SLAVE_A2NOC_SNOC },
};
+static struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x17000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
.id = SM8650_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_qdss_etr_0_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A2NOC_SNOC },
};
+static struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x18000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
.id = SM8650_MASTER_QDSS_ETR_1,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_qdss_etr_1_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A2NOC_SNOC },
};
+static struct qcom_icc_qosbox xm_sdc2_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x19000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
.id = SM8650_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_sdc2_qos,
.num_links = 1,
.links = { SM8650_SLAVE_A2NOC_SNOC },
};
@@ -223,29 +338,56 @@ static struct qcom_icc_node qnm_gemnoc_pcie = {
.links = { SM8650_SLAVE_PCIE_0, SM8650_SLAVE_PCIE_1 },
};
+static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xbf000 },
+ .prio = 1,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+};
+
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
.id = SM8650_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
+ .qosbox = &alm_gpu_tcu_qos,
.num_links = 2,
.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
};
+static struct qcom_icc_qosbox alm_sys_tcu_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xc1000 },
+ .prio = 6,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+};
+
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
.id = SM8650_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
+ .qosbox = &alm_sys_tcu_qos,
.num_links = 2,
.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
};
+static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xc5000 },
+ .prio = 1,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+};
+
static struct qcom_icc_node alm_ubwc_p_tcu = {
.name = "alm_ubwc_p_tcu",
.id = SM8650_MASTER_UBWC_P_TCU,
.channels = 1,
.buswidth = 8,
+ .qosbox = &alm_ubwc_p_tcu_qos,
.num_links = 2,
.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
};
@@ -260,20 +402,38 @@ static struct qcom_icc_node chm_apps = {
SM8650_SLAVE_MEM_NOC_PCIE_SNOC },
};
+static struct qcom_icc_qosbox qnm_gpu_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x31000, 0x71000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+};
+
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
.id = SM8650_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_gpu_qos,
.num_links = 2,
.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
};
+static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xb5000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_lpass_gemnoc = {
.name = "qnm_lpass_gemnoc",
.id = SM8650_MASTER_LPASS_GEM_NOC,
.channels = 1,
.buswidth = 16,
+ .qosbox = &qnm_lpass_gemnoc_qos,
.num_links = 3,
.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,
SM8650_SLAVE_MEM_NOC_PCIE_SNOC },
@@ -289,67 +449,130 @@ static struct qcom_icc_node qnm_mdsp = {
SM8650_SLAVE_MEM_NOC_PCIE_SNOC },
};
+static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x33000, 0x73000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
.id = SM8650_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_mnoc_hf_qos,
.num_links = 2,
.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
};
+static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x35000, 0x75000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
.id = SM8650_MASTER_MNOC_SF_MEM_NOC,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_mnoc_sf_qos,
.num_links = 2,
.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
};
+static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x37000, 0x77000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+};
+
static struct qcom_icc_node qnm_nsp_gemnoc = {
.name = "qnm_nsp_gemnoc",
.id = SM8650_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_nsp_gemnoc_qos,
.num_links = 3,
.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,
SM8650_SLAVE_MEM_NOC_PCIE_SNOC },
};
+static struct qcom_icc_qosbox qnm_pcie_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xb7000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
.id = SM8650_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
+ .qosbox = &qnm_pcie_qos,
.num_links = 2,
.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC },
};
+static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xbb000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
.id = SM8650_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
+ .qosbox = &qnm_snoc_sf_qos,
.num_links = 3,
.links = { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC,
SM8650_SLAVE_MEM_NOC_PCIE_SNOC },
};
+static struct qcom_icc_qosbox qnm_ubwc_p_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xc3000 },
+ .prio = 1,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 1,
+};
+
static struct qcom_icc_node qnm_ubwc_p = {
.name = "qnm_ubwc_p",
.id = SM8650_MASTER_UBWC_P,
.channels = 1,
.buswidth = 32,
+ .qosbox = &qnm_ubwc_p_qos,
.num_links = 1,
.links = { SM8650_SLAVE_LLCC },
};
+static struct qcom_icc_qosbox xm_gic_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xb9000 },
+ .prio = 4,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+};
+
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
.id = SM8650_MASTER_GIC,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_gic_qos,
.num_links = 1,
.links = { SM8650_SLAVE_LLCC },
};
@@ -390,38 +613,74 @@ static struct qcom_icc_node llcc_mc = {
.links = { SM8650_SLAVE_EBI1 },
};
+static struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x28000, 0x29000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
.id = SM8650_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_camnoc_hf_qos,
.num_links = 1,
.links = { SM8650_SLAVE_MNOC_HF_MEM_NOC },
};
+static struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x2a000 },
+ .prio = 4,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
.id = SM8650_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qnm_camnoc_icp_qos,
.num_links = 1,
.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
};
+static struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x2b000, 0x2c000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
.id = SM8650_MASTER_CAMNOC_SF,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_camnoc_sf_qos,
.num_links = 1,
.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
};
+static struct qcom_icc_qosbox qnm_mdp_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x2d000, 0x2e000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_mdp = {
.name = "qnm_mdp",
.id = SM8650_MASTER_MDP,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_mdp_qos,
.num_links = 1,
.links = { SM8650_SLAVE_MNOC_HF_MEM_NOC },
};
@@ -435,38 +694,74 @@ static struct qcom_icc_node qnm_vapss_hcp = {
.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
};
+static struct qcom_icc_qosbox qnm_video_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x30000, 0x31000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_video = {
.name = "qnm_video",
.id = SM8650_MASTER_VIDEO,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_video_qos,
.num_links = 1,
.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
};
+static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x32000 },
+ .prio = 4,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_video_cv_cpu = {
.name = "qnm_video_cv_cpu",
.id = SM8650_MASTER_VIDEO_CV_PROC,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qnm_video_cv_cpu_qos,
.num_links = 1,
.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
};
+static struct qcom_icc_qosbox qnm_video_cvp_qos = {
+ .num_ports = 2,
+ .port_offsets = { 0x33000, 0x34000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
.id = SM8650_MASTER_VIDEO_PROC,
.channels = 2,
.buswidth = 32,
+ .qosbox = &qnm_video_cvp_qos,
.num_links = 1,
.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
};
+static struct qcom_icc_qosbox qnm_video_v_cpu_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0x35000 },
+ .prio = 4,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
.id = SM8650_MASTER_VIDEO_V_PROC,
.channels = 1,
.buswidth = 8,
+ .qosbox = &qnm_video_v_cpu_qos,
.num_links = 1,
.links = { SM8650_SLAVE_MNOC_SF_MEM_NOC },
};
@@ -498,20 +793,38 @@ static struct qcom_icc_node qsm_pcie_anoc_cfg = {
.links = { SM8650_SLAVE_SERVICE_PCIE_ANOC },
};
+static struct qcom_icc_qosbox xm_pcie3_0_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xb000 },
+ .prio = 3,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
.id = SM8650_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
+ .qosbox = &xm_pcie3_0_qos,
.num_links = 1,
.links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC },
};
+static struct qcom_icc_qosbox xm_pcie3_1_qos = {
+ .num_ports = 1,
+ .port_offsets = { 0xc000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 0,
+};
+
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
.id = SM8650_MASTER_PCIE_1,
.channels = 1,
.buswidth = 16,
+ .qosbox = &xm_pcie3_1_qos,
.num_links = 1,
.links = { SM8650_SLAVE_ANOC_PCIE_GEM_NOC },
};
@@ -1325,6 +1638,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_aggre1_noc = {
+ .config = &icc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
};
@@ -1346,6 +1660,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_aggre2_noc = {
+ .config = &icc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
@@ -1368,6 +1683,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8650_clk_virt = {
+ .config = &icc_regmap_config,
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
@@ -1429,6 +1745,7 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_config_noc = {
+ .config = &icc_regmap_config,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -1456,6 +1773,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[] = {
};
static const struct qcom_icc_desc sm8650_cnoc_main = {
+ .config = &icc_regmap_config,
.nodes = cnoc_main_nodes,
.num_nodes = ARRAY_SIZE(cnoc_main_nodes),
.bcms = cnoc_main_bcms,
@@ -1488,6 +1806,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_gem_noc = {
+ .config = &icc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -1500,6 +1819,7 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_lpass_ag_noc = {
+ .config = &icc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
};
@@ -1514,6 +1834,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc = {
+ .config = &icc_regmap_config,
.nodes = lpass_lpiaon_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
.bcms = lpass_lpiaon_noc_bcms,
@@ -1526,6 +1847,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_lpass_lpicx_noc = {
+ .config = &icc_regmap_config,
.nodes = lpass_lpicx_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
};
@@ -1541,6 +1863,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = {
};
static const struct qcom_icc_desc sm8650_mc_virt = {
+ .config = &icc_regmap_config,
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
@@ -1569,6 +1892,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_mmss_noc = {
+ .config = &icc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -1585,6 +1909,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_nsp_noc = {
+ .config = &icc_regmap_config,
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
@@ -1604,6 +1929,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_pcie_anoc = {
+ .config = &icc_regmap_config,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -1623,6 +1949,7 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
};
static const struct qcom_icc_desc sm8650_system_noc = {
+ .config = &icc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
---
base-commit: 2bdde620f7f2bff2ff1cb7dc166859eaa0c78a7c
change-id: 20250407-topic-sm8650-upstream-icc-qos-ebc5bee4896d
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] interconnect: qcom: sm8650: enable QoS configuration
2025-04-07 15:16 [PATCH] interconnect: qcom: sm8650: enable QoS configuration Neil Armstrong
@ 2025-04-14 17:08 ` Georgi Djakov
2025-04-15 8:17 ` Neil Armstrong
2025-05-19 8:23 ` Pengyu Luo
1 sibling, 1 reply; 6+ messages in thread
From: Georgi Djakov @ 2025-04-14 17:08 UTC (permalink / raw)
To: Neil Armstrong; +Cc: linux-arm-msm, linux-pm, linux-kernel
On 7.04.25 18:16, Neil Armstrong wrote:
> Enable QoS configuration for master ports with predefined values
> for priority and urgency forwarding.
>
Hi Neil,
Thanks for the patch! It looks fine, but i noticed that there should be also
QoS configuration for the qnm_apss_noc node, but it's missing from the driver.
Do you know if skipping it was intentional?
Thanks,
Georgi
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> drivers/interconnect/qcom/sm8650.c | 327 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 327 insertions(+)
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] interconnect: qcom: sm8650: enable QoS configuration
2025-04-14 17:08 ` Georgi Djakov
@ 2025-04-15 8:17 ` Neil Armstrong
2025-04-15 8:42 ` Georgi Djakov
0 siblings, 1 reply; 6+ messages in thread
From: Neil Armstrong @ 2025-04-15 8:17 UTC (permalink / raw)
To: Georgi Djakov; +Cc: linux-arm-msm, linux-pm, linux-kernel
On 14/04/2025 19:08, Georgi Djakov wrote:
> On 7.04.25 18:16, Neil Armstrong wrote:
>> Enable QoS configuration for master ports with predefined values
>> for priority and urgency forwarding.
>>
>
> Hi Neil,
>
> Thanks for the patch! It looks fine, but i noticed that there should be also
> QoS configuration for the qnm_apss_noc node, but it's missing from the driver.
> Do you know if skipping it was intentional?
The qnm_apss_noc node is not present in the upstream driver, I wanted to add it
in a second time. Or I can do it first as you prefer
Neil
>
> Thanks,
> Georgi
>
>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> drivers/interconnect/qcom/sm8650.c | 327 +++++++++++++++++++++++++++++++++++++
>> 1 file changed, 327 insertions(+)
>>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] interconnect: qcom: sm8650: enable QoS configuration
2025-04-15 8:17 ` Neil Armstrong
@ 2025-04-15 8:42 ` Georgi Djakov
0 siblings, 0 replies; 6+ messages in thread
From: Georgi Djakov @ 2025-04-15 8:42 UTC (permalink / raw)
To: neil.armstrong; +Cc: linux-arm-msm, linux-pm, linux-kernel
On 15.04.25 11:17, Neil Armstrong wrote:
> On 14/04/2025 19:08, Georgi Djakov wrote:
>> On 7.04.25 18:16, Neil Armstrong wrote:
>>> Enable QoS configuration for master ports with predefined values
>>> for priority and urgency forwarding.
>>>
>>
>> Hi Neil,
>>
>> Thanks for the patch! It looks fine, but i noticed that there should be also
>> QoS configuration for the qnm_apss_noc node, but it's missing from the driver.
>> Do you know if skipping it was intentional?
>
> The qnm_apss_noc node is not present in the upstream driver, I wanted to add it
> in a second time. Or I can do it first as you prefer
I was just wondering if there is any specific reason for not adding it or was
it just missed. A follow-up patch is fine.
Thanks,
Georgi
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] interconnect: qcom: sm8650: enable QoS configuration
2025-04-07 15:16 [PATCH] interconnect: qcom: sm8650: enable QoS configuration Neil Armstrong
2025-04-14 17:08 ` Georgi Djakov
@ 2025-05-19 8:23 ` Pengyu Luo
2025-05-19 13:30 ` neil.armstrong
1 sibling, 1 reply; 6+ messages in thread
From: Pengyu Luo @ 2025-05-19 8:23 UTC (permalink / raw)
To: neil.armstrong; +Cc: djakov, linux-arm-msm, linux-kernel, linux-pm
On Mon, 07 Apr 2025 17:16:47 +0200 Neil Armstrong <neil.armstrong@linaro.org> wrote:
> Enable QoS configuration for master ports with predefined values
> for priority and urgency forwarding.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
[...]
> +static const struct regmap_config icc_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .fast_io = true,
> +};
[...]
> static const struct qcom_icc_desc sm8650_mc_virt = {
> + .config = &icc_regmap_config,
> .nodes = mc_virt_nodes,
> .num_nodes = ARRAY_SIZE(mc_virt_nodes),
> .bcms = mc_virt_bcms,
Hi, Neil. It seems that the config for clk_virt, mc_virt is not working
on some devices. My device Oneplus Pad 2(pineappleP variant, mtp based,
but without modem) shown the following.
Apr 30 01:56:16 oneplus-caihong kernel: qnoc-sm8650 interconnect-0: error -EINVAL: invalid resource (null)
Apr 30 01:56:16 oneplus-caihong kernel: qnoc-sm8650 interconnect-1: error -EINVAL: invalid resource (null)
Best wishes,
Pengyu
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] interconnect: qcom: sm8650: enable QoS configuration
2025-05-19 8:23 ` Pengyu Luo
@ 2025-05-19 13:30 ` neil.armstrong
0 siblings, 0 replies; 6+ messages in thread
From: neil.armstrong @ 2025-05-19 13:30 UTC (permalink / raw)
To: Pengyu Luo; +Cc: djakov, linux-arm-msm, linux-kernel, linux-pm
On 19/05/2025 10:23, Pengyu Luo wrote:
> On Mon, 07 Apr 2025 17:16:47 +0200 Neil Armstrong <neil.armstrong@linaro.org> wrote:
>> Enable QoS configuration for master ports with predefined values
>> for priority and urgency forwarding.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>
> [...]
>
>> +static const struct regmap_config icc_regmap_config = {
>> + .reg_bits = 32,
>> + .reg_stride = 4,
>> + .val_bits = 32,
>> + .fast_io = true,
>> +};
>
> [...]
>
>> static const struct qcom_icc_desc sm8650_mc_virt = {
>> + .config = &icc_regmap_config,
>> .nodes = mc_virt_nodes,
>> .num_nodes = ARRAY_SIZE(mc_virt_nodes),
>> .bcms = mc_virt_bcms,
>
> Hi, Neil. It seems that the config for clk_virt, mc_virt is not working
> on some devices. My device Oneplus Pad 2(pineappleP variant, mtp based,
> but without modem) shown the following.
>
> Apr 30 01:56:16 oneplus-caihong kernel: qnoc-sm8650 interconnect-0: error -EINVAL: invalid resource (null)
> Apr 30 01:56:16 oneplus-caihong kernel: qnoc-sm8650 interconnect-1: error -EINVAL: invalid resource (null)
Right, those doesn't have registers, let me check
Thanks,
Neil
>
> Best wishes,
> Pengyu
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-05-19 13:30 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-07 15:16 [PATCH] interconnect: qcom: sm8650: enable QoS configuration Neil Armstrong
2025-04-14 17:08 ` Georgi Djakov
2025-04-15 8:17 ` Neil Armstrong
2025-04-15 8:42 ` Georgi Djakov
2025-05-19 8:23 ` Pengyu Luo
2025-05-19 13:30 ` neil.armstrong
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox