* [PATCH] arm64: dts: qcom: Add BLSP DMAs for I2C
@ 2023-04-22 11:39 Luca Weiss
2023-04-22 12:02 ` Konrad Dybcio
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Luca Weiss @ 2023-04-22 11:39 UTC (permalink / raw)
To: ~postmarketos/upstreaming, phone-devel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss
MSM8953 has two DMA controllers for the various I2C, SPI and UART
busses. Add the nodes and configure all the I2C nodes so that the driver
can use the DMA.
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
arch/arm64/boot/dts/qcom/msm8953.dtsi | 48 +++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 602cb188a635..c9b589353918 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -1274,6 +1274,19 @@ opp-200000000 {
};
};
+ blsp1_dma: dma-controller@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07884000 0x1f000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ num-channels = <12>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,num-ees = <4>;
+ qcom,controlled-remotely;
+ };
+
uart_0: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
@@ -1292,6 +1305,8 @@ i2c_1: i2c@78b5000 {
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
+ dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_1_default>;
@@ -1310,6 +1325,8 @@ i2c_2: i2c@78b6000 {
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
+ dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_2_default>;
@@ -1328,6 +1345,9 @@ i2c_3: i2c@78b7000 {
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
+ dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
+ dma-names = "tx", "rx";
+
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_3_default>;
pinctrl-1 = <&i2c_3_sleep>;
@@ -1345,6 +1365,9 @@ i2c_4: i2c@78b8000 {
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
+ dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
+ dma-names = "tx", "rx";
+
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_4_default>;
pinctrl-1 = <&i2c_4_sleep>;
@@ -1355,6 +1378,19 @@ i2c_4: i2c@78b8000 {
status = "disabled";
};
+ blsp2_dma: dma-controller@7ac4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07ac4000 0x1f000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "bam_clk";
+ num-channels = <12>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,num-ees = <4>;
+ qcom,controlled-remotely;
+ };
+
i2c_5: i2c@7af5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af5000 0x600>;
@@ -1362,6 +1398,9 @@ i2c_5: i2c@7af5000 {
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
+ dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
+ dma-names = "tx", "rx";
+
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_5_default>;
pinctrl-1 = <&i2c_5_sleep>;
@@ -1379,6 +1418,9 @@ i2c_6: i2c@7af6000 {
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
+ dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
+ dma-names = "tx", "rx";
+
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_6_default>;
pinctrl-1 = <&i2c_6_sleep>;
@@ -1396,6 +1438,9 @@ i2c_7: i2c@7af7000 {
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
+ dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
+ dma-names = "tx", "rx";
+
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_7_default>;
pinctrl-1 = <&i2c_7_sleep>;
@@ -1413,6 +1458,9 @@ i2c_8: i2c@7af8000 {
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
+ dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
+ dma-names = "tx", "rx";
+
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_8_default>;
pinctrl-1 = <&i2c_8_sleep>;
---
base-commit: 347e9b4e41bfff51993807962eb1082f6d8ab439
change-id: 20230422-msm8953-blsp-dma-1174277859f2
Best regards,
--
Luca Weiss <luca@z3ntu.xyz>
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: dts: qcom: Add BLSP DMAs for I2C
2023-04-22 11:39 [PATCH] arm64: dts: qcom: Add BLSP DMAs for I2C Luca Weiss
@ 2023-04-22 12:02 ` Konrad Dybcio
2023-05-12 10:14 ` Alexey Minnekhanov
2023-05-25 4:54 ` Bjorn Andersson
2 siblings, 0 replies; 5+ messages in thread
From: Konrad Dybcio @ 2023-04-22 12:02 UTC (permalink / raw)
To: Luca Weiss, ~postmarketos/upstreaming, phone-devel, Andy Gross,
Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 22.04.2023 13:39, Luca Weiss wrote:
> MSM8953 has two DMA controllers for the various I2C, SPI and UART
> busses. Add the nodes and configure all the I2C nodes so that the driver
> can use the DMA.
>
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> ---Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> arch/arm64/boot/dts/qcom/msm8953.dtsi | 48 +++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
> index 602cb188a635..c9b589353918 100644
> --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
> @@ -1274,6 +1274,19 @@ opp-200000000 {
> };
> };
>
> + blsp1_dma: dma-controller@7884000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0x07884000 0x1f000>;
> + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "bam_clk";
> + num-channels = <12>;
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + qcom,num-ees = <4>;
> + qcom,controlled-remotely;
> + };
> +
> uart_0: serial@78af000 {
> compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> reg = <0x078af000 0x200>;
> @@ -1292,6 +1305,8 @@ i2c_1: i2c@78b5000 {
> clock-names = "core", "iface";
> clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
> <&gcc GCC_BLSP1_AHB_CLK>;
> + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
> + dma-names = "tx", "rx";
>
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&i2c_1_default>;
> @@ -1310,6 +1325,8 @@ i2c_2: i2c@78b6000 {
> clock-names = "core", "iface";
> clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
> <&gcc GCC_BLSP1_AHB_CLK>;
> + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
> + dma-names = "tx", "rx";
>
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&i2c_2_default>;
> @@ -1328,6 +1345,9 @@ i2c_3: i2c@78b7000 {
> clock-names = "core", "iface";
> clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
> <&gcc GCC_BLSP1_AHB_CLK>;
> + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
> + dma-names = "tx", "rx";
> +
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&i2c_3_default>;
> pinctrl-1 = <&i2c_3_sleep>;
> @@ -1345,6 +1365,9 @@ i2c_4: i2c@78b8000 {
> clock-names = "core", "iface";
> clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
> <&gcc GCC_BLSP1_AHB_CLK>;
> + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
> + dma-names = "tx", "rx";
> +
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&i2c_4_default>;
> pinctrl-1 = <&i2c_4_sleep>;
> @@ -1355,6 +1378,19 @@ i2c_4: i2c@78b8000 {
> status = "disabled";
> };
>
> + blsp2_dma: dma-controller@7ac4000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0x07ac4000 0x1f000>;
> + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP2_AHB_CLK>;
> + clock-names = "bam_clk";
> + num-channels = <12>;
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + qcom,num-ees = <4>;
> + qcom,controlled-remotely;
> + };
> +
> i2c_5: i2c@7af5000 {
> compatible = "qcom,i2c-qup-v2.2.1";
> reg = <0x07af5000 0x600>;
> @@ -1362,6 +1398,9 @@ i2c_5: i2c@7af5000 {
> clock-names = "core", "iface";
> clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
> <&gcc GCC_BLSP2_AHB_CLK>;
> + dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
> + dma-names = "tx", "rx";
> +
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&i2c_5_default>;
> pinctrl-1 = <&i2c_5_sleep>;
> @@ -1379,6 +1418,9 @@ i2c_6: i2c@7af6000 {
> clock-names = "core", "iface";
> clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
> <&gcc GCC_BLSP2_AHB_CLK>;
> + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
> + dma-names = "tx", "rx";
> +
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&i2c_6_default>;
> pinctrl-1 = <&i2c_6_sleep>;
> @@ -1396,6 +1438,9 @@ i2c_7: i2c@7af7000 {
> clock-names = "core", "iface";
> clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
> <&gcc GCC_BLSP2_AHB_CLK>;
> + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
> + dma-names = "tx", "rx";
> +
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&i2c_7_default>;
> pinctrl-1 = <&i2c_7_sleep>;
> @@ -1413,6 +1458,9 @@ i2c_8: i2c@7af8000 {
> clock-names = "core", "iface";
> clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
> <&gcc GCC_BLSP2_AHB_CLK>;
> + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
> + dma-names = "tx", "rx";
> +
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&i2c_8_default>;
> pinctrl-1 = <&i2c_8_sleep>;
>
> ---
> base-commit: 347e9b4e41bfff51993807962eb1082f6d8ab439
> change-id: 20230422-msm8953-blsp-dma-1174277859f2
>
> Best regards,
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: dts: qcom: Add BLSP DMAs for I2C
2023-04-22 11:39 [PATCH] arm64: dts: qcom: Add BLSP DMAs for I2C Luca Weiss
2023-04-22 12:02 ` Konrad Dybcio
@ 2023-05-12 10:14 ` Alexey Minnekhanov
2023-05-12 15:42 ` Luca Weiss
2023-05-25 4:54 ` Bjorn Andersson
2 siblings, 1 reply; 5+ messages in thread
From: Alexey Minnekhanov @ 2023-05-12 10:14 UTC (permalink / raw)
To: Luca Weiss, ~postmarketos/upstreaming, phone-devel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 22.04.2023 14:39, Luca Weiss wrote:
> MSM8953 has two DMA controllers for the various I2C, SPI and UART
> busses. Add the nodes and configure all the I2C nodes so that the driver
> can use the DMA.
>
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> ---
> arch/arm64/boot/dts/qcom/msm8953.dtsi | 48 +++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
Hello,
> arm64: dts: qcom: Add BLSP DMAs for I2C
to all qcom boards? Or only for msm8953? Commit title is unclear.
--
Regards
Alexey Minnekhanov
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: qcom: Add BLSP DMAs for I2C
2023-05-12 10:14 ` Alexey Minnekhanov
@ 2023-05-12 15:42 ` Luca Weiss
0 siblings, 0 replies; 5+ messages in thread
From: Luca Weiss @ 2023-05-12 15:42 UTC (permalink / raw)
To: ~postmarketos/upstreaming, phone-devel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Alexey Minnekhanov
Cc: linux-arm-msm, devicetree, linux-kernel
On Freitag, 12. Mai 2023 12:14:29 CEST Alexey Minnekhanov wrote:
> On 22.04.2023 14:39, Luca Weiss wrote:
> > MSM8953 has two DMA controllers for the various I2C, SPI and UART
> > busses. Add the nodes and configure all the I2C nodes so that the driver
> > can use the DMA.
> >
> > Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> > ---
> >
> > arch/arm64/boot/dts/qcom/msm8953.dtsi | 48
> > +++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
>
> Hello,
>
> > arm64: dts: qcom: Add BLSP DMAs for I2C
>
> to all qcom boards? Or only for msm8953? Commit title is unclear.
Right, missed "msm8953: " in the subject ;)
Thanks for catching that!
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: qcom: Add BLSP DMAs for I2C
2023-04-22 11:39 [PATCH] arm64: dts: qcom: Add BLSP DMAs for I2C Luca Weiss
2023-04-22 12:02 ` Konrad Dybcio
2023-05-12 10:14 ` Alexey Minnekhanov
@ 2023-05-25 4:54 ` Bjorn Andersson
2 siblings, 0 replies; 5+ messages in thread
From: Bjorn Andersson @ 2023-05-25 4:54 UTC (permalink / raw)
To: Krzysztof Kozlowski, Konrad Dybcio, Rob Herring, Andy Gross,
Luca Weiss, ~postmarketos/upstreaming, phone-devel
Cc: linux-kernel, linux-arm-msm, devicetree
On Sat, 22 Apr 2023 13:39:16 +0200, Luca Weiss wrote:
> MSM8953 has two DMA controllers for the various I2C, SPI and UART
> busses. Add the nodes and configure all the I2C nodes so that the driver
> can use the DMA.
>
>
Applied, thanks!
[1/1] arm64: dts: qcom: Add BLSP DMAs for I2C
commit: a5317b23fe6f26307f4c821d56d694c893887675
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-05-25 4:55 UTC | newest]
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2023-04-22 11:39 [PATCH] arm64: dts: qcom: Add BLSP DMAs for I2C Luca Weiss
2023-04-22 12:02 ` Konrad Dybcio
2023-05-12 10:14 ` Alexey Minnekhanov
2023-05-12 15:42 ` Luca Weiss
2023-05-25 4:54 ` Bjorn Andersson
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