Re: [PATCH v2 3/5] arm64: dts: qcom: agatti: add LPASS devices

[Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>]

On 2/24/26 12:28 PM, Konrad Dybcio wrote:
> On 2/23/26 2:39 PM, Srinivas Kandagatla wrote:
>> From: Alexey Klimov <alexey.klimov@linaro.org>
>>
>> The rxmacro, txmacro, vamacro, soundwire nodes, lpass clock
>> controllers are required to support audio playback and
>> audio capture on sm6115 and its derivatives.
>>
>> Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
>> ---
> 
> [...]
> 
>> +		lpass_audiocc: clock-controller@a6a9000 {
>> +			compatible = "qcom,sm6115-lpassaudiocc";
>> +			reg = <0x0 0x0a6a9000 0x0 0x1000>;
>> +			#reset-cells = <1>;
>> +		};
> 
> This should be called "qcom,sm6115-lpass-audio-csr" and should probably
> have a syscon fallback as there's a lot of various magic tunables in
> there, in addition to the CGCR bits. The clock driver can continue to
> bind to this new compatible, like we do with the SoC-side TCSR on e.g.
> 8550 and the tcsrcc-sm8550 driver.
Are you expecting this to be a reset-controller interface or just syscon
so that drivers can poke into this register space.

The reason to take the full address space here and represent the HW
control bits as reset controller is that we have room for adding these
various magic tunables with some standard interface when required in
this driver.

I could have done the way as you suggested with syscon and let the
drivers poke the whatever values it want, but that is not scalable and
clutters the interfaces and encourage to use the way it was done in
downstream.



This is same for all the Qualcomm SoCs, why sm6115 has to do this change
alone? And its going to break the Device tree abi.

Sorry but I can not do the changes that you suggested here.

I would suggest that we use the existing mechanism which is more future
proof.


Please suggest otherwise, I would like to move on with enabling audio on
UNO Q platform.


--srini

> 
> [...]
> 
>> +		lpasscc: clock-controller@a7ec000 {
>> +			compatible = "qcom,sm6115-lpasscc";
>> +			reg = <0x0 0x0a7e0000 0x0 0x12000>;
>> +			#reset-cells = <1>;
>> +		};
> 
> All the same, except "qcom,sm6115-lpass-tcsr"
> 
> I'm once again sorry for not getting this right n years ago, but I did not
> have the sufficient documentation back then


> 
> Konrad