[PATCH v3 0/9] Enable CPR for IPQ9574

[PATCH v3 0/9] Enable CPR for IPQ9574

[Varadarajan Narayanan]

This series tries to enable CPR on IPQ9574, that implements
CPRv4. Since [1] is older, faced few minor issues. Those are
addressed in [2].

dt_binding_check and dtbs_check passed.

Depends:
	[1] https://lore.kernel.org/lkml/20230217-topic-cpr3h-v14-0-9fd23241493d@linaro.org/T/
	[2] https://github.com/quic-varada/cpr/tree/4de50be55a89eb29ab0d40d3fcfe9aa7a9ccf910

v3: Fix patch authorship for 2 patches
    Include CPR3 file changes done to Konrad's patches in https://github.com/quic-varada/cpr/commits/konrad/
    Change url for [2] to skip the cpr3 file changes

v2: Fix Signed-off-by order in 2 patches
    Update constraints in qcom,cpr3.yaml
    Add rbcpr_clk_src registration
    Add Reviewed-by to one of the patches
    Not adding Acked-by as the file has changed
Praveenkumar I (2):
  pmdomain: qcom: rpmpd: Add IPQ9574 power domains
  soc: qcom: cpr3: Add IPQ9574 definitions

Varadarajan Narayanan (7):
  soc: qcom: cpr3: Fix 'acc_desc' usage
  cpufreq: qcom-nvmem: Add genpd names to match_data_kryo
  dt-bindings: power: rpmpd: Add IPQ9574 power domains
  dt-bindings: soc: qcom: cpr3: Add bindings for IPQ9574
  dt-bindings: clock: Add CPR clock defines for IPQ9574
  clk: qcom: gcc-ipq9574: Add CPR clock definition
  dts: arm64: qcom: ipq9574: Enable CPR

 .../devicetree/bindings/power/qcom,rpmpd.yaml |   1 +
 .../bindings/soc/qcom/qcom,cpr3.yaml          |  35 +++
 arch/arm64/boot/dts/qcom/ipq9574.dtsi         | 269 ++++++++++++++++--
 drivers/clk/qcom/gcc-ipq9574.c                |  39 +++
 drivers/cpufreq/qcom-cpufreq-nvmem.c          |   1 +
 drivers/pmdomain/qcom/cpr3.c                  | 145 +++++++++-
 drivers/pmdomain/qcom/rpmpd.c                 |  19 ++
 include/dt-bindings/clock/qcom,ipq9574-gcc.h  |   2 +
 include/dt-bindings/power/qcom-rpmpd.h        |   3 +
 9 files changed, 493 insertions(+), 21 deletions(-)

-- 
2.34.1

[PATCH v3 1/9] soc: qcom: cpr3: Fix 'acc_desc' usage

[Varadarajan Narayanan]

cpr3 code assumes that 'acc_desc' is available for SoCs
implementing CPR version 4 or less. However, IPQ9574 SoC
implements CPRv4 without ACC. This causes NULL pointer accesses
resulting in crashes. Hence, check is 'acc_desc' is populated
before using it.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 drivers/pmdomain/qcom/cpr3.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c
index c7790a71e74f..c28028be50d8 100644
--- a/drivers/pmdomain/qcom/cpr3.c
+++ b/drivers/pmdomain/qcom/cpr3.c
@@ -2399,12 +2399,12 @@ static int cpr_pd_attach_dev(struct generic_pm_domain *domain,
 		if (ret)
 			goto exit;
 
-		if (acc_desc->config)
+		if (acc_desc && acc_desc->config)
 			regmap_multi_reg_write(drv->tcsr, acc_desc->config,
 					       acc_desc->num_regs_per_fuse);
 
 		/* Enable ACC if required */
-		if (acc_desc->enable_mask)
+		if (acc_desc && acc_desc->enable_mask)
 			regmap_update_bits(drv->tcsr, acc_desc->enable_reg,
 					   acc_desc->enable_mask,
 					   acc_desc->enable_mask);
@@ -2676,7 +2676,7 @@ static int cpr_probe(struct platform_device *pdev)
 	desc = data->cpr_desc;
 
 	/* CPRh disallows MEM-ACC access from the HLOS */
-	if (!data->acc_desc && desc->cpr_type < CTRL_TYPE_CPRH)
+	if (!data->acc_desc && desc->cpr_type < CTRL_TYPE_CPR4)
 		return -EINVAL;
 
 	drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
@@ -2703,7 +2703,7 @@ static int cpr_probe(struct platform_device *pdev)
 
 	mutex_init(&drv->lock);
 
-	if (desc->cpr_type < CTRL_TYPE_CPRH) {
+	if (desc->cpr_type < CTRL_TYPE_CPR4) {
 		np = of_parse_phandle(dev->of_node, "qcom,acc", 0);
 		if (!np)
 			return -ENODEV;
-- 
2.34.1

[PATCH v3 2/9] cpufreq: qcom-nvmem: Add genpd names to match_data_kryo

[Varadarajan Narayanan]

This is used for tying up the cpu@N nodes with the power domains.
Without this, 'cat /sys/kernel/debug/qcom_cpr3/thread0'
crashes with NULL pointer access.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 939702dfa73f..5e6525c7788c 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -399,6 +399,7 @@ static const char *generic_genpd_names[] = { "perf", NULL };
 
 static const struct qcom_cpufreq_match_data match_data_kryo = {
 	.get_version = qcom_cpufreq_kryo_name_version,
+	.genpd_names = generic_genpd_names,
 };
 
 static const struct qcom_cpufreq_match_data match_data_krait = {
-- 
2.34.1

[PATCH v3 3/9] dt-bindings: power: rpmpd: Add IPQ9574 power domains

[Varadarajan Narayanan]

Add the compatibles and indexes for the rpmpd in IPQ9574.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Add Reviewed-by
---
 Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
 include/dt-bindings/power/qcom-rpmpd.h                  | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
index 929b7ef9c1bc..e20ba25fa094 100644
--- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
@@ -17,6 +17,7 @@ properties:
   compatible:
     oneOf:
       - enum:
+          - qcom,ipq9574-rpmpd
           - qcom,mdm9607-rpmpd
           - qcom,msm8226-rpmpd
           - qcom,msm8909-rpmpd
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index 608087fb9a3d..0538370bfbb4 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -402,6 +402,9 @@
 #define QCM2290_VDD_LPI_CX	6
 #define QCM2290_VDD_LPI_MX	7
 
+/* IPQ9574 Power Domains */
+#define IPQ9574_VDDAPC		0
+
 /* RPM SMD Power Domain performance levels */
 #define RPM_SMD_LEVEL_RETENTION       16
 #define RPM_SMD_LEVEL_RETENTION_PLUS  32
-- 
2.34.1

[PATCH v3 4/9] dt-bindings: soc: qcom: cpr3: Add bindings for IPQ9574

[Varadarajan Narayanan]

Add the bindings for the IPQ9574 CPR3 driver to the documentation.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Constrained nvmem-cells and the other variant.
    Removed unnecessary blank line.
---
 .../bindings/soc/qcom/qcom,cpr3.yaml          | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
index acf2e294866b..f72addaa0ca2 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
@@ -24,6 +24,7 @@ properties:
       - const: qcom,cpr4
       - items:
           - enum:
+              - qcom,ipq9574-cprh
               - qcom,msm8998-cprh
               - qcom,sdm630-cprh
           - const: qcom,cprh
@@ -52,9 +53,11 @@ properties:
 
   nvmem-cells:
     description: Cells containing the fuse corners and revision data
+    minItems: 17
     maxItems: 32
 
   nvmem-cell-names:
+    minItems: 17
     maxItems: 32
 
   operating-points-v2: true
@@ -74,6 +77,36 @@ required:
 additionalProperties: false
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq9574-cprh
+    then:
+      properties:
+        nvmem-cells:
+          maxItems: 17
+        nvmem-cell-names:
+          items:
+            - const: cpr_speed_bin
+            - const: cpr_fuse_revision
+            - const: cpr0_quotient1
+            - const: cpr0_quotient2
+            - const: cpr0_quotient3
+            - const: cpr0_quotient4
+            - const: cpr0_quotient_offset2
+            - const: cpr0_quotient_offset3
+            - const: cpr0_quotient_offset4
+            - const: cpr0_init_voltage1
+            - const: cpr0_init_voltage2
+            - const: cpr0_init_voltage3
+            - const: cpr0_init_voltage4
+            - const: cpr0_ring_osc1
+            - const: cpr0_ring_osc2
+            - const: cpr0_ring_osc3
+            - const: cpr0_ring_osc4
+
   - if:
       properties:
         compatible:
@@ -82,6 +115,8 @@ allOf:
               - qcom,msm8998-cprh
     then:
       properties:
+        nvmem-cells:
+          minItems: 32
         nvmem-cell-names:
           items:
             - const: cpr_speed_bin
-- 
2.34.1

[PATCH v3 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains

[Varadarajan Narayanan]

From: Praveenkumar I <quic_ipkumar@quicinc.com>

Add the APC power domain definitions used in IPQ9574.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v3: Fix patch author
v2: Fix Signed-off-by order
---
 drivers/pmdomain/qcom/rpmpd.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/pmdomain/qcom/rpmpd.c b/drivers/pmdomain/qcom/rpmpd.c
index 5e6280b4cf70..947d6a9c3897 100644
--- a/drivers/pmdomain/qcom/rpmpd.c
+++ b/drivers/pmdomain/qcom/rpmpd.c
@@ -38,6 +38,7 @@ static struct qcom_smd_rpm *rpmpd_smd_rpm;
 #define KEY_FLOOR_CORNER	0x636676   /* vfc */
 #define KEY_FLOOR_LEVEL		0x6c6676   /* vfl */
 #define KEY_LEVEL		0x6c766c76 /* vlvl */
+#define RPM_KEY_UV		0x00007675 /* "uv" */
 
 #define MAX_CORNER_RPMPD_STATE	6
 
@@ -644,6 +645,23 @@ static const struct rpmpd_desc mdm9607_desc = {
 	.max_state = RPM_SMD_LEVEL_TURBO,
 };
 
+static struct rpmpd apc_s1_lvl = {
+	.pd = { .name = "apc", },
+	.res_type = RPMPD_SMPA,
+	.res_id = 1,
+	.key = RPM_KEY_UV,
+};
+
+static struct rpmpd *ipq9574_rpmpds[] = {
+	[IPQ9574_VDDAPC] =	&apc_s1_lvl,
+};
+
+static const struct rpmpd_desc ipq9574_desc = {
+	.rpmpds = ipq9574_rpmpds,
+	.num_pds = ARRAY_SIZE(ipq9574_rpmpds),
+	.max_state = RPM_SMD_LEVEL_TURBO_HIGH,
+};
+
 static struct rpmpd *msm8226_rpmpds[] = {
 	[MSM8226_VDDCX] =	&cx_s1a_corner,
 	[MSM8226_VDDCX_AO] =	&cx_s1a_corner_ao,
@@ -931,6 +949,7 @@ static const struct rpmpd_desc qcm2290_desc = {
 };
 
 static const struct of_device_id rpmpd_match_table[] = {
+	{ .compatible = "qcom,ipq9574-rpmpd", .data = &ipq9574_desc },
 	{ .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc },
 	{ .compatible = "qcom,msm8226-rpmpd", .data = &msm8226_desc },
 	{ .compatible = "qcom,msm8909-rpmpd", .data = &msm8916_desc },
-- 
2.34.1

[PATCH v3 6/9] dt-bindings: clock: Add CPR clock defines for IPQ9574

[Varadarajan Narayanan]

Add defines for the CPR block present in IPQ9574.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Add GCC_RBCPR_CLK_SRC define.
    Not adding 'Acked-by: Krzysztof Kozlowski' as the file changed.
---
 include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 52123c5a09fa..4c65de04cb7b 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -220,4 +220,6 @@
 #define GCC_PCIE1_PIPE_CLK				211
 #define GCC_PCIE2_PIPE_CLK				212
 #define GCC_PCIE3_PIPE_CLK				213
+#define GCC_RBCPR_CLK_SRC				214
+#define GCC_RBCPR_CLK					215
 #endif
-- 
2.34.1

[PATCH v3 7/9] clk: qcom: gcc-ipq9574: Add CPR clock definition

[Varadarajan Narayanan]

Add the CPR clock definition needed for enabling access to
CPR register space.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 drivers/clk/qcom/gcc-ipq9574.c | 39 ++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index e1dc74d04ed1..eac557937fd3 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -3994,6 +3994,43 @@ static struct clk_branch gcc_xo_div4_clk = {
 	},
 };
 
+static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 rbcpr_clk_src = {
+	.cmd_rcgr = 0x48044,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = gcc_xo_map,
+	.freq_tbl = ftbl_gp1_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "rbcpr_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4,
+		.num_parents = ARRAY_SIZE(gcc_xo_map),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_rbcpr_clk = {
+	.halt_reg = 0x48008,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x48008,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_rbcpr_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+				&rbcpr_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_hw *gcc_ipq9574_hws[] = {
 	&gpll0_out_main_div2.hw,
 	&gcc_xo_div4_clk_src.hw,
@@ -4219,6 +4256,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
 	[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
 	[GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
 	[GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
+	[GCC_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
+	[GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr,
 };
 
 static const struct qcom_reset_map gcc_ipq9574_resets[] = {
-- 
2.34.1

[PATCH v3 8/9] soc: qcom: cpr3: Add IPQ9574 definitions

[Varadarajan Narayanan]

From: Praveenkumar I <quic_ipkumar@quicinc.com>

Add thread, scaling factor, CPR descriptor defines to enable CPR
on IPQ9574.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v3: Fix patch author
    Included below information in cover letter
v2: Fix Signed-off-by order
Depends:
	[1] https://lore.kernel.org/lkml/20230217-topic-cpr3h-v14-0-9fd23241493d@linaro.org/T/
	[2] https://github.com/quic-varada/cpr/commits/konrad/
---
 drivers/pmdomain/qcom/cpr3.c | 137 +++++++++++++++++++++++++++++++++++
 1 file changed, 137 insertions(+)

diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c
index c28028be50d8..66c8a4bd9adc 100644
--- a/drivers/pmdomain/qcom/cpr3.c
+++ b/drivers/pmdomain/qcom/cpr3.c
@@ -2056,6 +2056,142 @@ static const struct cpr_acc_desc msm8998_cpr_acc_desc = {
 	.cpr_desc = &msm8998_cpr_desc,
 };
 
+static const int ipq9574_silver_scaling_factor[][CPR3_RO_COUNT] = {
+	/* Fuse Corner 0 */
+	{
+		2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+		2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+	},
+	/* Fuse Corner 1 */
+	{
+		2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+		2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+	},
+	/* Fuse Corner 2 */
+	{
+		2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+		2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+	},
+	/* Fuse Corner 3 */
+	{
+		2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949,
+		2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332
+	},
+};
+
+static const struct cpr_thread_desc ipq9574_thread_silver = {
+	.controller_id = 0,
+	.hw_tid = 0,
+	.ro_scaling_factor = ipq9574_silver_scaling_factor,
+	.sensor_range_start = 0,
+	.sensor_range_end = 6,
+	.init_voltage_step = 10000,
+	.init_voltage_width = 6,
+	.step_quot_init_min = 0,
+	.step_quot_init_max = 15,
+	.num_fuse_corners = 4,
+	.fuse_corner_data = (struct fuse_corner_data[]){
+		/* fuse corner 0 */
+		{
+			.ref_uV = 725000,
+			.max_uV = 725000,
+			.min_uV = 725000,
+			.range_uV = 0,
+			.volt_cloop_adjust = 0,
+			.volt_oloop_adjust = 0,
+			.max_volt_scale = 4,
+			.max_quot_scale = 10,
+			.quot_offset = 0,
+			.quot_scale = 1,
+			.quot_adjust = 0,
+			.quot_offset_scale = 5,
+			.quot_offset_adjust = 0,
+		},
+		/* fuse corner 1 */
+		{
+			.ref_uV = 862500,
+			.max_uV = 862500,
+			.min_uV = 725000,
+			.range_uV = 0,
+			.volt_cloop_adjust = 0,
+			.volt_oloop_adjust = 0,
+			.max_volt_scale = 500,
+			.max_quot_scale = 800,
+			.quot_offset = 0,
+			.quot_scale = 1,
+			.quot_adjust = 0,
+			.quot_offset_scale = 5,
+			.quot_offset_adjust = 0,
+		},
+		/* fuse corner 2 */
+		{
+			.ref_uV = 987500,
+			.max_uV = 987500,
+			.min_uV = 787500,
+			.range_uV = 0,
+			.volt_cloop_adjust = 0,
+			.volt_oloop_adjust = 0,
+			.max_volt_scale = 280,
+			.max_quot_scale = 650,
+			.quot_offset = 0,
+			.quot_scale = 1,
+			.quot_adjust = 0,
+			.quot_offset_scale = 5,
+			.quot_offset_adjust = 0,
+
+		},
+		/* fuse corner 3 */
+		{
+			.ref_uV = 1062500,
+			.max_uV = 1062500,
+			.min_uV = 850000,
+			.range_uV = 0,
+			.volt_cloop_adjust = 0,
+			.volt_oloop_adjust = 0,
+			.max_volt_scale = 430,
+			.max_quot_scale = 800,
+			.quot_offset = 0,
+			.quot_scale = 1,
+			.quot_adjust = 0,
+			.quot_offset_scale = 5,
+			.quot_offset_adjust = 0,
+		},
+	},
+};
+
+static const struct cpr_desc ipq9574_cpr_desc = {
+	.cpr_type = CTRL_TYPE_CPR4,
+	.num_threads = 1,
+	.apm_threshold = 850000,
+	.apm_crossover = 880000,
+	.apm_hysteresis = 0,
+	.cpr_base_voltage = 700000,
+	.cpr_max_voltage = 1100000,
+	.timer_delay_us = 5000,
+	.timer_cons_up = 0,
+	.timer_cons_down = 0,
+	.up_threshold = 2,
+	.down_threshold = 2,
+	.idle_clocks = 15,
+	.count_mode = CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN,
+	.count_repeat = 1,
+	.gcnt_us = 1,
+	.vreg_step_fixed = 12500,
+	.vreg_step_up_limit = 1,
+	.vreg_step_down_limit = 1,
+	.vdd_settle_time_us = 34,
+	.corner_settle_time_us = 6,
+	.reduce_to_corner_uV = true,
+	.hw_closed_loop_en = false,
+	.threads = (const struct cpr_thread_desc *[]) {
+		&ipq9574_thread_silver,
+	},
+};
+
+static const struct cpr_acc_desc ipq9574_cpr_acc_desc = {
+	.cpr_desc = &ipq9574_cpr_desc,
+};
+
 static const int sdm630_gold_scaling_factor[][CPR3_RO_COUNT] = {
 	/* Same RO factors for all fuse corners */
 	{
@@ -2828,6 +2964,7 @@ static void cpr_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id cpr3_match_table[] = {
+	{ .compatible = "qcom,ipq9574-cprh", .data = &ipq9574_cpr_acc_desc },
 	{ .compatible = "qcom,msm8998-cprh", .data = &msm8998_cpr_acc_desc },
 	{ .compatible = "qcom,sdm630-cprh", .data = &sdm630_cpr_acc_desc },
 	{ }
-- 
2.34.1

[PATCH v3 9/9] dts: arm64: qcom: ipq9574: Enable CPR

[Varadarajan Narayanan]

* Add CPR, RPMPD, OPP table nodes as applicable to IPQ9574 to
  enable CPR functionality on IPQ9574.

* Bootloader set frequency 792MHz is added to the OPP table to
  the avoid unknown frequency warning message at boot time.

* Remove 1.2GHz as it is not supported in any of the IPQ9574 SKUs.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v2: Update commit log. No code change.
---
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 269 ++++++++++++++++++++++++--
 1 file changed, 252 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 04ba09a9156c..439ee5accc47 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -42,8 +43,9 @@ CPU0: cpu@0 {
 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&ipq9574_s1>;
 			#cooling-cells = <2>;
+			power-domains = <&apc_cprh 0>;
+			power-domain-names = "perf";
 		};
 
 		CPU1: cpu@1 {
@@ -55,8 +57,9 @@ CPU1: cpu@1 {
 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&ipq9574_s1>;
 			#cooling-cells = <2>;
+			power-domains = <&apc_cprh 0>;
+			power-domain-names = "perf";
 		};
 
 		CPU2: cpu@2 {
@@ -68,8 +71,9 @@ CPU2: cpu@2 {
 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&ipq9574_s1>;
 			#cooling-cells = <2>;
+			power-domains = <&apc_cprh 0>;
+			power-domain-names = "perf";
 		};
 
 		CPU3: cpu@3 {
@@ -81,8 +85,9 @@ CPU3: cpu@3 {
 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu_opp_table>;
-			cpu-supply = <&ipq9574_s1>;
 			#cooling-cells = <2>;
+			power-domains = <&apc_cprh 0>;
+			power-domain-names = "perf";
 		};
 
 		L2_0: l2-cache {
@@ -105,58 +110,111 @@ memory@40000000 {
 		reg = <0x0 0x40000000 0x0 0x0>;
 	};
 
+	cprh_opp_table: opp-table-cprh {
+		compatible = "operating-points-v2-qcom-level";
+
+		cprh_opp0: opp-0 {
+			opp-level = <1>;
+			qcom,opp-fuse-level = <1>;
+			qcom,opp-cloop-vadj = <0>;
+			qcom,opp-oloop-vadj = <0>;
+		};
+
+		cprh_opp1: opp-1 {
+			opp-level = <2>;
+			qcom,opp-fuse-level = <1>;
+			qcom,opp-cloop-vadj = <0>;
+			qcom,opp-oloop-vadj = <0>;
+		};
+
+		cprh_opp2: opp-2 {
+			opp-level = <3>;
+			qcom,opp-fuse-level = <1>;
+			qcom,opp-cloop-vadj = <0>;
+			qcom,opp-oloop-vadj = <0>;
+		};
+
+		cprh_opp3: opp-3 {
+			opp-level = <4>;
+			qcom,opp-fuse-level = <2>;
+			qcom,opp-cloop-vadj = <0>;
+			qcom,opp-oloop-vadj = <0>;
+		};
+
+		cprh_opp4: opp-4 {
+			opp-level = <5>;
+			qcom,opp-fuse-level = <2>;
+			qcom,opp-cloop-vadj = <0>;
+			qcom,opp-oloop-vadj = <0>;
+		};
+
+		cprh_opp5: opp-5 {
+			opp-level = <6>;
+			qcom,opp-fuse-level = <3>;
+			qcom,opp-cloop-vadj = <0>;
+			qcom,opp-oloop-vadj = <0>;
+		};
+
+		cprh_opp6: opp-6 {
+			opp-level = <7>;
+			qcom,opp-fuse-level = <4>;
+			qcom,opp-cloop-vadj = <0>;
+			qcom,opp-oloop-vadj = <0>;
+		};
+	};
+
 	cpu_opp_table: opp-table-cpu {
 		compatible = "operating-points-v2-kryo-cpu";
 		opp-shared;
 		nvmem-cells = <&cpu_speed_bin>;
 
+		opp-792000000 {
+			opp-hz = /bits/ 64 <792000000>;
+			opp-supported-hw = <0x0>;
+			clock-latency-ns = <200000>;
+			required-opps = <&cprh_opp0>;
+		};
+
 		opp-936000000 {
 			opp-hz = /bits/ 64 <936000000>;
-			opp-microvolt = <725000>;
 			opp-supported-hw = <0xf>;
 			clock-latency-ns = <200000>;
+			required-opps = <&cprh_opp1>;
 		};
 
 		opp-1104000000 {
 			opp-hz = /bits/ 64 <1104000000>;
-			opp-microvolt = <787500>;
-			opp-supported-hw = <0xf>;
-			clock-latency-ns = <200000>;
-		};
-
-		opp-1200000000 {
-			opp-hz = /bits/ 64 <1200000000>;
-			opp-microvolt = <862500>;
 			opp-supported-hw = <0xf>;
 			clock-latency-ns = <200000>;
+			required-opps = <&cprh_opp2>;
 		};
 
 		opp-1416000000 {
 			opp-hz = /bits/ 64 <1416000000>;
-			opp-microvolt = <862500>;
 			opp-supported-hw = <0x7>;
 			clock-latency-ns = <200000>;
+			required-opps = <&cprh_opp3>;
 		};
 
 		opp-1488000000 {
 			opp-hz = /bits/ 64 <1488000000>;
-			opp-microvolt = <925000>;
 			opp-supported-hw = <0x7>;
 			clock-latency-ns = <200000>;
+			required-opps = <&cprh_opp4>;
 		};
 
 		opp-1800000000 {
 			opp-hz = /bits/ 64 <1800000000>;
-			opp-microvolt = <987500>;
 			opp-supported-hw = <0x5>;
 			clock-latency-ns = <200000>;
+			required-opps = <&cprh_opp5>;
 		};
 
 		opp-2208000000 {
 			opp-hz = /bits/ 64 <2208000000>;
-			opp-microvolt = <1062500>;
 			opp-supported-hw = <0x1>;
 			clock-latency-ns = <200000>;
+			required-opps = <&cprh_opp6>;
 		};
 	};
 
@@ -182,6 +240,40 @@ glink-edge {
 			rpm_requests: rpm-requests {
 				compatible = "qcom,rpm-ipq9574";
 				qcom,glink-channels = "rpm_requests";
+
+				rpmpd: power-controller {
+					compatible = "qcom,ipq9574-rpmpd";
+					#power-domain-cells = <1>;
+					operating-points-v2 = <&rpmpd_opp_table>;
+
+					rpmpd_opp_table: opp-table {
+						compatible = "operating-points-v2";
+
+						rpmpd_opp_svs: opp1 {
+							opp-level = <RPM_SMD_LEVEL_SVS>;
+						};
+
+						rpmpd_opp_svs_plus: opp2 {
+							opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+						};
+
+						rpmpd_opp_nom: opp3 {
+							opp-level = <RPM_SMD_LEVEL_NOM>;
+						};
+
+						rpmpd_opp_nom_plus: opp4 {
+							opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+						};
+
+						rpmpd_opp_turbo: opp5 {
+							opp-level = <RPM_SMD_LEVEL_TURBO>;
+						};
+
+						rpmpd_opp_turbo_high: opp6 {
+							opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
+						};
+					};
+				};
 			};
 		};
 	};
@@ -252,6 +344,95 @@ cpu_speed_bin: cpu-speed-bin@15 {
 				reg = <0x15 0x2>;
 				bits = <7 2>;
 			};
+
+			cpr_efuse_speedbin: speedbin@5 {
+				reg = <0x5 0x8>;
+				bits = <0 3>;
+			};
+
+			cpr_fuse_revision: cpr-fusing-rev@7 {
+				reg = <0x7 0x8>;
+				bits = <1 5>;
+			};
+
+			/* CPR Ring Oscillator: Power Cluster */
+			cpr_ro_sel0_pwrcl: rosel0-pwrcl@358 {	/* ROSEL_SVS */
+				reg = <0x358 0x1>;
+				bits = <4 4>;
+			};
+
+			cpr_ro_sel1_pwrcl: rosel1-pwrcl@358 {	/* ROSEL_NOM */
+				reg = <0x358 0x1>;
+				bits = <0 4>;
+			};
+
+			cpr_ro_sel2_pwrcl: rosel2-pwrcl@350 {	/* ROSEL_TUR */
+				reg = <0x350 0x1>;
+				bits = <4 4>;
+			};
+
+			cpr_ro_sel3_pwrcl: rosel3-pwrcl@350 {	/* ROSEL_STUR */
+				reg = <0x350 0x1>;
+				bits = <0 4>;
+			};
+
+			/* CPR Init Voltage: Power Cluster */
+			cpr_init_voltage0_pwrcl: ivolt0-pwrcl@343 {	/* VOLT_SVS */
+				reg = <0x343 0x1>;
+				bits = <0 6>;
+			};
+
+			cpr_init_voltage1_pwrcl: ivolt1-pwrcl@342 {	/* VOLT_NOM */
+				reg = <0x342 0x1>;
+				bits = <2 6>;
+			};
+
+			cpr_init_voltage2_pwrcl: ivolt2-pwrcl@341 {	/* VOLT_TUR */
+				reg = <0x341 0x2>;
+				bits = <4 6>;
+			};
+
+			cpr_init_voltage3_pwrcl: ivolt3-pwrcl@340 {	/* VOLT_STUR */
+				reg = <0x340 0x2>;
+				bits = <6 6>;
+			};
+
+			/* CPR Target Quotients: Power Cluster */
+			cpr_quot0_pwrcl: quot0-pwrcl@354 {	/* QUOT_VMIN_SVS */
+				reg = <0x354 0x2>;
+				bits = <0 12>;
+			};
+
+			cpr_quot1_pwrcl: quot1-pwrcl@352 {	/* QUOT_VMIN_NOM */
+				reg = <0x352 0x2>;
+				bits = <4 12>;
+			};
+
+			cpr_quot2_pwrcl: quot2-pwrcl@351 {	/* QUOT_VMIN_TUR */
+				reg = <0x351 0x2>;
+				bits = <0 12>;
+			};
+
+			cpr_quot3_pwrcl: quot3-pwrcl@355 {	/* QUOT_VMIN_STUR */
+				reg = <0x355 0x2>;
+				bits = <4 12>;
+			};
+
+			/* CPR Quotient Offsets: Power Cluster */
+			cpr_quot_offset1_pwrcl: qoff1-pwrcl@34e {	/* QUOT_OFFSET_NOM_SVS */
+				reg = <0x34e 0x1>;
+				bits = <0 8>;
+			};
+
+			cpr_quot_offset2_pwrcl: qoff2-pwrcl@34d {	/* QUOT_OFFSET_TUR_NOM */
+				reg = <0x34d 0x1>;
+				bits = <0 8>;
+			};
+
+			cpr_quot_offset3_pwrcl: qoff0-pwrcl@34c {	/* QUOT_OFFSET_STUR_TUR */
+				reg = <0x34c 0x1>;
+				bits = <0 8>;
+			};
 		};
 
 		cryptobam: dma-controller@704000 {
@@ -639,6 +820,60 @@ usb_0_dwc3: usb@8a00000 {
 			};
 		};
 
+		apc_cprh: power-controller@b018000 {
+			compatible = "qcom,ipq9574-cprh", "qcom,cprh";
+			reg = <0x0b018000 0x4000>,
+			      <0x00048000 0x4000>;
+
+			clocks = <&gcc GCC_RBCPR_CLK>;
+
+			interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
+			vdd-supply = <&ipq9574_s1>;
+
+			/* Set the CPR clock here, it needs to match XO */
+			assigned-clocks = <&gcc GCC_RBCPR_CLK>;
+			assigned-clock-rates = <24000000>;
+
+			operating-points-v2 = <&cprh_opp_table>;
+			power-domains = <&rpmpd IPQ9574_VDDAPC>;
+			#power-domain-cells = <1>;
+
+			nvmem-cells = <&cpr_efuse_speedbin>,
+				      <&cpr_fuse_revision>,
+				      <&cpr_quot0_pwrcl>,
+				      <&cpr_quot1_pwrcl>,
+				      <&cpr_quot2_pwrcl>,
+				      <&cpr_quot3_pwrcl>,
+				      <&cpr_quot_offset1_pwrcl>,
+				      <&cpr_quot_offset2_pwrcl>,
+				      <&cpr_quot_offset3_pwrcl>,
+				      <&cpr_init_voltage0_pwrcl>,
+				      <&cpr_init_voltage1_pwrcl>,
+				      <&cpr_init_voltage2_pwrcl>,
+				      <&cpr_init_voltage3_pwrcl>,
+				      <&cpr_ro_sel0_pwrcl>,
+				      <&cpr_ro_sel1_pwrcl>,
+				      <&cpr_ro_sel2_pwrcl>,
+				      <&cpr_ro_sel3_pwrcl>;
+			nvmem-cell-names = "cpr_speed_bin",
+					   "cpr_fuse_revision",
+					   "cpr0_quotient1",
+					   "cpr0_quotient2",
+					   "cpr0_quotient3",
+					   "cpr0_quotient4",
+					   "cpr0_quotient_offset2",
+					   "cpr0_quotient_offset3",
+					   "cpr0_quotient_offset4",
+					   "cpr0_init_voltage1",
+					   "cpr0_init_voltage2",
+					   "cpr0_init_voltage3",
+					   "cpr0_init_voltage4",
+					   "cpr0_ring_osc1",
+					   "cpr0_ring_osc2",
+					   "cpr0_ring_osc3",
+					   "cpr0_ring_osc4";
+		};
+
 		intc: interrupt-controller@b000000 {
 			compatible = "qcom,msm-qgic2";
 			reg = <0x0b000000 0x1000>,  /* GICD */
-- 
2.34.1

Re: [PATCH v3 1/9] soc: qcom: cpr3: Fix 'acc_desc' usage

[Dmitry Baryshkov]

On Wed, Jun 26, 2024 at 04:09:54PM GMT, Varadarajan Narayanan wrote:
> cpr3 code assumes that 'acc_desc' is available for SoCs
> implementing CPR version 4 or less. However, IPQ9574 SoC
> implements CPRv4 without ACC. This causes NULL pointer accesses
> resulting in crashes. Hence, check is 'acc_desc' is populated
> before using it.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
>  drivers/pmdomain/qcom/cpr3.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c
> index c7790a71e74f..c28028be50d8 100644
> --- a/drivers/pmdomain/qcom/cpr3.c
> +++ b/drivers/pmdomain/qcom/cpr3.c
> @@ -2399,12 +2399,12 @@ static int cpr_pd_attach_dev(struct generic_pm_domain *domain,
>  		if (ret)
>  			goto exit;
>  
> -		if (acc_desc->config)
> +		if (acc_desc && acc_desc->config)
>  			regmap_multi_reg_write(drv->tcsr, acc_desc->config,
>  					       acc_desc->num_regs_per_fuse);
>  
>  		/* Enable ACC if required */
> -		if (acc_desc->enable_mask)
> +		if (acc_desc && acc_desc->enable_mask)
>  			regmap_update_bits(drv->tcsr, acc_desc->enable_reg,
>  					   acc_desc->enable_mask,
>  					   acc_desc->enable_mask);
> @@ -2676,7 +2676,7 @@ static int cpr_probe(struct platform_device *pdev)
>  	desc = data->cpr_desc;
>  
>  	/* CPRh disallows MEM-ACC access from the HLOS */
> -	if (!data->acc_desc && desc->cpr_type < CTRL_TYPE_CPRH)
> +	if (!data->acc_desc && desc->cpr_type < CTRL_TYPE_CPR4)
>  		return -EINVAL;
>  
>  	drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
> @@ -2703,7 +2703,7 @@ static int cpr_probe(struct platform_device *pdev)
>  
>  	mutex_init(&drv->lock);
>  
> -	if (desc->cpr_type < CTRL_TYPE_CPRH) {
> +	if (desc->cpr_type < CTRL_TYPE_CPR4) {

This is incorrect. This disables ACC usage for CPR4, while GFX CPR on
MSM8998 (which is CPR4) seems to use ACC.

>  		np = of_parse_phandle(dev->of_node, "qcom,acc", 0);
>  		if (!np)
>  			return -ENODEV;
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH v3 2/9] cpufreq: qcom-nvmem: Add genpd names to match_data_kryo

[Dmitry Baryshkov]

On Wed, Jun 26, 2024 at 04:09:55PM GMT, Varadarajan Narayanan wrote:
> This is used for tying up the cpu@N nodes with the power domains.
> Without this, 'cat /sys/kernel/debug/qcom_cpr3/thread0'
> crashes with NULL pointer access.

Add the interesting part of the backtrace, please.

> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
>  drivers/cpufreq/qcom-cpufreq-nvmem.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> index 939702dfa73f..5e6525c7788c 100644
> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> @@ -399,6 +399,7 @@ static const char *generic_genpd_names[] = { "perf", NULL };
>  
>  static const struct qcom_cpufreq_match_data match_data_kryo = {
>  	.get_version = qcom_cpufreq_kryo_name_version,
> +	.genpd_names = generic_genpd_names,

This forces that every Kryo SoC has "perf" genpd, which obviously isn't
corret (at least from the upstream support point of view).

>  };
>  
>  static const struct qcom_cpufreq_match_data match_data_krait = {
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH v3 5/9] pmdomain: qcom: rpmpd: Add IPQ9574 power domains

[Dmitry Baryshkov]

On Wed, Jun 26, 2024 at 04:09:58PM GMT, Varadarajan Narayanan wrote:
> From: Praveenkumar I <quic_ipkumar@quicinc.com>
> 
> Add the APC power domain definitions used in IPQ9574.
> 
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v3: Fix patch author
> v2: Fix Signed-off-by order
> ---
>  drivers/pmdomain/qcom/rpmpd.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 


Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH v3 8/9] soc: qcom: cpr3: Add IPQ9574 definitions

[Dmitry Baryshkov]

On Wed, Jun 26, 2024 at 04:10:01PM GMT, Varadarajan Narayanan wrote:
> From: Praveenkumar I <quic_ipkumar@quicinc.com>
> 
> Add thread, scaling factor, CPR descriptor defines to enable CPR
> on IPQ9574.
> 
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> v3: Fix patch author
>     Included below information in cover letter
> v2: Fix Signed-off-by order
> Depends:
> 	[1] https://lore.kernel.org/lkml/20230217-topic-cpr3h-v14-0-9fd23241493d@linaro.org/T/
> 	[2] https://github.com/quic-varada/cpr/commits/konrad/
> ---
>  drivers/pmdomain/qcom/cpr3.c | 137 +++++++++++++++++++++++++++++++++++
>  1 file changed, 137 insertions(+)
> 
> diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c
> index c28028be50d8..66c8a4bd9adc 100644
> --- a/drivers/pmdomain/qcom/cpr3.c
> +++ b/drivers/pmdomain/qcom/cpr3.c

> +
> +static const struct cpr_desc ipq9574_cpr_desc = {
> +	.cpr_type = CTRL_TYPE_CPR4,

So, is it CPR4 or CPRh?

> +	.num_threads = 1,
> +	.apm_threshold = 850000,
> +	.apm_crossover = 880000,
> +	.apm_hysteresis = 0,
> +	.cpr_base_voltage = 700000,
> +	.cpr_max_voltage = 1100000,
> +	.timer_delay_us = 5000,
> +	.timer_cons_up = 0,
> +	.timer_cons_down = 0,
> +	.up_threshold = 2,
> +	.down_threshold = 2,
> +	.idle_clocks = 15,
> +	.count_mode = CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN,
> +	.count_repeat = 1,
> +	.gcnt_us = 1,
> +	.vreg_step_fixed = 12500,
> +	.vreg_step_up_limit = 1,
> +	.vreg_step_down_limit = 1,
> +	.vdd_settle_time_us = 34,
> +	.corner_settle_time_us = 6,
> +	.reduce_to_corner_uV = true,
> +	.hw_closed_loop_en = false,
> +	.threads = (const struct cpr_thread_desc *[]) {
> +		&ipq9574_thread_silver,

If it's silver, where is gold or bronze?

> +	},
> +};
> +
> +static const struct cpr_acc_desc ipq9574_cpr_acc_desc = {
> +	.cpr_desc = &ipq9574_cpr_desc,
> +};
> +
>  static const int sdm630_gold_scaling_factor[][CPR3_RO_COUNT] = {
>  	/* Same RO factors for all fuse corners */
>  	{
> @@ -2828,6 +2964,7 @@ static void cpr_remove(struct platform_device *pdev)
>  }
>  
>  static const struct of_device_id cpr3_match_table[] = {
> +	{ .compatible = "qcom,ipq9574-cprh", .data = &ipq9574_cpr_acc_desc },
>  	{ .compatible = "qcom,msm8998-cprh", .data = &msm8998_cpr_acc_desc },
>  	{ .compatible = "qcom,sdm630-cprh", .data = &sdm630_cpr_acc_desc },
>  	{ }
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH v3 8/9] soc: qcom: cpr3: Add IPQ9574 definitions

[Varadarajan Narayanan]

On Wed, Jun 26, 2024 at 09:27:53PM +0300, Dmitry Baryshkov wrote:
> On Wed, Jun 26, 2024 at 04:10:01PM GMT, Varadarajan Narayanan wrote:
> > From: Praveenkumar I <quic_ipkumar@quicinc.com>
> >
> > Add thread, scaling factor, CPR descriptor defines to enable CPR
> > on IPQ9574.
> >
> > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > v3: Fix patch author
> >     Included below information in cover letter
> > v2: Fix Signed-off-by order
> > Depends:
> > 	[1] https://lore.kernel.org/lkml/20230217-topic-cpr3h-v14-0-9fd23241493d@linaro.org/T/
> > 	[2] https://github.com/quic-varada/cpr/commits/konrad/
> > ---
> >  drivers/pmdomain/qcom/cpr3.c | 137 +++++++++++++++++++++++++++++++++++
> >  1 file changed, 137 insertions(+)
> >
> > diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c
> > index c28028be50d8..66c8a4bd9adc 100644
> > --- a/drivers/pmdomain/qcom/cpr3.c
> > +++ b/drivers/pmdomain/qcom/cpr3.c
>
> > +
> > +static const struct cpr_desc ipq9574_cpr_desc = {
> > +	.cpr_type = CTRL_TYPE_CPR4,
>
> So, is it CPR4 or CPRh?

CPR4.

> > +	.num_threads = 1,
> > +	.apm_threshold = 850000,
> > +	.apm_crossover = 880000,
> > +	.apm_hysteresis = 0,
> > +	.cpr_base_voltage = 700000,
> > +	.cpr_max_voltage = 1100000,
> > +	.timer_delay_us = 5000,
> > +	.timer_cons_up = 0,
> > +	.timer_cons_down = 0,
> > +	.up_threshold = 2,
> > +	.down_threshold = 2,
> > +	.idle_clocks = 15,
> > +	.count_mode = CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN,
> > +	.count_repeat = 1,
> > +	.gcnt_us = 1,
> > +	.vreg_step_fixed = 12500,
> > +	.vreg_step_up_limit = 1,
> > +	.vreg_step_down_limit = 1,
> > +	.vdd_settle_time_us = 34,
> > +	.corner_settle_time_us = 6,
> > +	.reduce_to_corner_uV = true,
> > +	.hw_closed_loop_en = false,
> > +	.threads = (const struct cpr_thread_desc *[]) {
> > +		&ipq9574_thread_silver,
>
> If it's silver, where is gold or bronze?

Will rename this as "ipq9574_thread"

Thanks
Varada

> > +	},
> > +};
> > +
> > +static const struct cpr_acc_desc ipq9574_cpr_acc_desc = {
> > +	.cpr_desc = &ipq9574_cpr_desc,
> > +};
> > +
> >  static const int sdm630_gold_scaling_factor[][CPR3_RO_COUNT] = {
> >  	/* Same RO factors for all fuse corners */
> >  	{
> > @@ -2828,6 +2964,7 @@ static void cpr_remove(struct platform_device *pdev)
> >  }
> >
> >  static const struct of_device_id cpr3_match_table[] = {
> > +	{ .compatible = "qcom,ipq9574-cprh", .data = &ipq9574_cpr_acc_desc },
> >  	{ .compatible = "qcom,msm8998-cprh", .data = &msm8998_cpr_acc_desc },
> >  	{ .compatible = "qcom,sdm630-cprh", .data = &sdm630_cpr_acc_desc },
> >  	{ }
> > --
> > 2.34.1
> >
>
> --
> With best wishes
> Dmitry

Re: [PATCH v3 4/9] dt-bindings: soc: qcom: cpr3: Add bindings for IPQ9574

[Krzysztof Kozlowski]

On 26/06/2024 12:39, Varadarajan Narayanan wrote:
> Add the bindings for the IPQ9574 CPR3 driver to the documentation.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 8/9] soc: qcom: cpr3: Add IPQ9574 definitions

[Dmitry Baryshkov]

On Thu, Jun 27, 2024 at 12:53:18PM GMT, Varadarajan Narayanan wrote:
> On Wed, Jun 26, 2024 at 09:27:53PM +0300, Dmitry Baryshkov wrote:
> > On Wed, Jun 26, 2024 at 04:10:01PM GMT, Varadarajan Narayanan wrote:
> > > From: Praveenkumar I <quic_ipkumar@quicinc.com>
> > >
> > > Add thread, scaling factor, CPR descriptor defines to enable CPR
> > > on IPQ9574.
> > >
> > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > ---
> > > v3: Fix patch author
> > >     Included below information in cover letter
> > > v2: Fix Signed-off-by order
> > > Depends:
> > > 	[1] https://lore.kernel.org/lkml/20230217-topic-cpr3h-v14-0-9fd23241493d@linaro.org/T/
> > > 	[2] https://github.com/quic-varada/cpr/commits/konrad/
> > > ---
> > >  drivers/pmdomain/qcom/cpr3.c | 137 +++++++++++++++++++++++++++++++++++
> > >  1 file changed, 137 insertions(+)
> > >
> > > diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c
> > > index c28028be50d8..66c8a4bd9adc 100644
> > > --- a/drivers/pmdomain/qcom/cpr3.c
> > > +++ b/drivers/pmdomain/qcom/cpr3.c
> >
> > > +
> > > +static const struct cpr_desc ipq9574_cpr_desc = {
> > > +	.cpr_type = CTRL_TYPE_CPR4,
> >
> > So, is it CPR4 or CPRh?
> 
> CPR4.

Then why do you have cprh in the compatible?

> 
> > > +	.num_threads = 1,
> > > +	.apm_threshold = 850000,
> > > +	.apm_crossover = 880000,
> > > +	.apm_hysteresis = 0,
> > > +	.cpr_base_voltage = 700000,
> > > +	.cpr_max_voltage = 1100000,
> > > +	.timer_delay_us = 5000,
> > > +	.timer_cons_up = 0,
> > > +	.timer_cons_down = 0,
> > > +	.up_threshold = 2,
> > > +	.down_threshold = 2,
> > > +	.idle_clocks = 15,
> > > +	.count_mode = CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN,
> > > +	.count_repeat = 1,
> > > +	.gcnt_us = 1,
> > > +	.vreg_step_fixed = 12500,
> > > +	.vreg_step_up_limit = 1,
> > > +	.vreg_step_down_limit = 1,
> > > +	.vdd_settle_time_us = 34,
> > > +	.corner_settle_time_us = 6,
> > > +	.reduce_to_corner_uV = true,
> > > +	.hw_closed_loop_en = false,
> > > +	.threads = (const struct cpr_thread_desc *[]) {
> > > +		&ipq9574_thread_silver,
> >
> > If it's silver, where is gold or bronze?
> 
> Will rename this as "ipq9574_thread"
> 
> Thanks
> Varada
> 
> > > +	},
> > > +};
> > > +
> > > +static const struct cpr_acc_desc ipq9574_cpr_acc_desc = {
> > > +	.cpr_desc = &ipq9574_cpr_desc,
> > > +};
> > > +
> > >  static const int sdm630_gold_scaling_factor[][CPR3_RO_COUNT] = {
> > >  	/* Same RO factors for all fuse corners */
> > >  	{
> > > @@ -2828,6 +2964,7 @@ static void cpr_remove(struct platform_device *pdev)
> > >  }
> > >
> > >  static const struct of_device_id cpr3_match_table[] = {
> > > +	{ .compatible = "qcom,ipq9574-cprh", .data = &ipq9574_cpr_acc_desc },
> > >  	{ .compatible = "qcom,msm8998-cprh", .data = &msm8998_cpr_acc_desc },
> > >  	{ .compatible = "qcom,sdm630-cprh", .data = &sdm630_cpr_acc_desc },
> > >  	{ }
> > > --
> > > 2.34.1
> > >
> >
> > --
> > With best wishes
> > Dmitry

-- 
With best wishes
Dmitry

Re: [PATCH v3 2/9] cpufreq: qcom-nvmem: Add genpd names to match_data_kryo

[Varadarajan Narayanan]

On Wed, Jun 26, 2024 at 09:23:17PM +0300, Dmitry Baryshkov wrote:
> On Wed, Jun 26, 2024 at 04:09:55PM GMT, Varadarajan Narayanan wrote:
> > This is used for tying up the cpu@N nodes with the power domains.
> > Without this, 'cat /sys/kernel/debug/qcom_cpr3/thread0'
> > crashes with NULL pointer access.
>
> Add the interesting part of the backtrace, please.

        if (thread->drv->desc->cpr_type < CTRL_TYPE_CPRH) {
                seq_printf(s, "current_volt = %d uV\n", thread->drv->last_uV);
                seq_printf(s, "requested voltage: %d uV\n", thread->corner->last_uV);
        }

thread->corner is NULL in the second printf above.

	# cat /sys/kernel/debug/qcom_cpr3/thread0
	[   16.965241] Unable to handle kernel NULL pointer dereference at virtual address 000000000000000c
	[   16.965270] Mem abort info:
	[   16.973181]   ESR = 0x0000000096000004
	[   16.975607]   EC = 0x25: DABT (current EL), IL = 32 bits
	[   16.979425]   SET = 0, FnV = 0
	[   16.984889]   EA = 0, S1PTW = 0
	[   16.987756]   FSC = 0x04: level 0 translation fault
	[   16.990792] Data abort info:
	[   16.995652]   ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
	[   16.998779]   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
	[   17.004074]   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
	[   17.009196] user pgtable: 4k pages, 48-bit VAs, pgdp=00000000481b1000
	[   17.014579] [000000000000000c] pgd=0000000000000000, p4d=0000000000000000
	[   17.020919] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
	[   17.020921] Modules linked in:
	[   17.020926] CPU: 0 UID: 0 PID: 118 Comm: cat Not tainted 6.10.0-rc4-next-20240620-00020-g125eb3184fc1-dirty #9
	[   17.020931] Hardware name: Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7 (DT)
	[   17.020933] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
	[   17.020936] pc : cpr3_debug_info_show+0x3a0/0x3ac
	[   17.020945] lr : cpr3_debug_info_show+0x390/0x3ac
	[   17.020948] sp : ffff800086293b90
	[   17.020949] x29: ffff800086293b90 x28: ffff0000034ae038 x27: 0000000000400cc0
	[   17.020953] x26: 000000007ffff000 x25: ffff0000034ae028 x24: 0000000000000000
	[   17.020957] x23: ffff800086293c80 x22: ffff000002399880 x21: ffff000002a8fa80
	[   17.020960] x20: ffff0000034ae000 x19: 0000000000000000 x18: ffffffffffffffff
	[   17.020964] x17: 0000000000000000 x16: 0000000000000000 x15: ffff800086293a40
	[   17.020967] x14: ffff000002913000 x13: ffff00000291200f x12: 0000000000000000
	[   17.020970] x11: 0000000000000000 x10: 0000000000000000 x9 : ffff0000034a9000
	[   17.020973] x8 : 000000000a567520 x7 : 0000000000000001 x6 : 000000000a567520
	[   17.020976] x5 : ffff000002912014 x4 : ffff800080e1f3a5 x3 : 0000000000000014
	[   17.020979] x2 : 0000000000000000 x1 : ffff800080e1f848 x0 : ffff0000034ae000
	[   17.020983] Call trace:
	[   17.020984]  cpr3_debug_info_show+0x3a0/0x3ac
	[   17.020987]  seq_read_iter+0xe0/0x45c
	[   17.020993]  seq_read+0xec/0x130
	[   17.020996]  full_proxy_read+0x60/0xb4
	[   17.020999]  vfs_read+0xc0/0x31c
	[   17.021003]  ksys_read+0x70/0x104
	[   17.021006]  __arm64_sys_read+0x1c/0x28
	[   17.021008]  invoke_syscall+0x48/0x114
	[   17.021014]  el0_svc_common+0x3c/0xe8
	[   17.021017]  do_el0_svc+0x20/0x2c
	[   17.021020]  el0_svc+0x34/0xd8
	[   17.021024]  el0t_64_sync_handler+0x120/0x12c
	[   17.021027]  el0t_64_sync+0x190/0x194
	[   17.021031] Code: f94012c2 aa1403e0 b0004701 91212021 (b9400c42)
	[   17.021033] ---[ end trace 0000000000000000 ]---
	Segmentation fault

> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> >  drivers/cpufreq/qcom-cpufreq-nvmem.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > index 939702dfa73f..5e6525c7788c 100644
> > --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > @@ -399,6 +399,7 @@ static const char *generic_genpd_names[] = { "perf", NULL };
> >
> >  static const struct qcom_cpufreq_match_data match_data_kryo = {
> >  	.get_version = qcom_cpufreq_kryo_name_version,
> > +	.genpd_names = generic_genpd_names,
>
> This forces that every Kryo SoC has "perf" genpd, which obviously isn't
> corret (at least from the upstream support point of view).

While trying to get the above backtrace, randomly during boot
I see the following BUG too.

	[    1.562847] ------------[ cut here ]------------
	[    1.574342] kernel BUG at drivers/cpufreq/cpufreq.c:1542!
	[    1.579203] Internal error: Oops - BUG: 00000000f2000800 [#1] PREEMPT SMP
	[    1.579209] Modules linked in:
	[    1.579217] CPU: 2 UID: 0 PID: 11 Comm: kworker/u16:0 Not tainted 6.10.0-rc4-next-20240620-00020-g125eb3184fc1-dirty #10
	[    1.579227] Hardware name: Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7 (DT)
	[    1.579232] Workqueue: events_unbound deferred_probe_work_func
	[    1.579249] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
	[    1.579257] pc : cpufreq_online+0x938/0x954
	[    1.579271] lr : cpufreq_online+0x788/0x954
	[    1.579281] sp : ffff8000817c3520
	[    1.579283] x29: ffff8000817c3520 x28: ffff0000029efa50 x27: 0000000000000001
	[    1.579294] x26: 0000000000000001 x25: ffff8000814d8da0 x24: 0000000000000000
	[    1.579303] x23: ffff0000029ef9d0 x22: ffff800081735000 x21: 0000000000000000
	[    1.579312] x20: 00000000000c15c0 x19: ffff0000029ef800 x18: ffff00000183481c
	[    1.579321] x17: ffff8000818a3638 x16: 0000000000000000 x15: ffff8000818a3670
	[    1.579330] x14: 0000000000000003 x13: ffff00000192b140 x12: ffff8000814d8c58
	[    1.579338] x11: ffff00000192b140 x10: 00000000000009b0 x9 : ffff8000817c3240
	[    1.579347] x8 : ffff00000192bad0 x7 : 0000000000000001 x6 : ffff8000814d8da0
	[    1.579355] x5 : ffff8000812c32d0 x4 : 0000000000000000 x3 : 0000000000000000
	[    1.579363] x2 : 0000000000000000 x1 : 0000000000000000 x0 : 00000000fffffff0
	[    1.579372] Call trace:
	[    1.579375]  cpufreq_online+0x938/0x954
	[    1.579386]  cpufreq_add_dev+0x80/0x98
	[    1.579395]  subsys_interface_register+0x100/0x130
	[    1.579404]  cpufreq_register_driver+0x150/0x244
	[    1.579413]  dt_cpufreq_probe+0x8c/0x440
	[    1.579420]  platform_probe+0x68/0xc8
	[    1.579430]  really_probe+0xbc/0x29c
	[    1.579438]  __driver_probe_device+0x78/0x12c
	[    1.579446]  driver_probe_device+0xd8/0x15c
	[    1.579454]  __device_attach_driver+0xb8/0x134
	[    1.579463]  bus_for_each_drv+0x84/0xe0
	[    1.579470]  __device_attach+0x9c/0x188
	[    1.579478]  device_initial_probe+0x14/0x20
	[    1.579487]  bus_probe_device+0xac/0xb0
	[    1.579494]  device_add+0x55c/0x720
	[    1.579500]  platform_device_add+0x1b8/0x244
	[    1.579510]  platform_device_register_full+0xfc/0x184
	[    1.579516]  platform_device_register_resndata.constprop.0+0x5c/0x8c
	[    1.579524]  qcom_cpufreq_probe+0x1e4/0x498
	[    1.579531]  platform_probe+0x68/0xc8
	[    1.579540]  really_probe+0xbc/0x29c
	[    1.579548]  __driver_probe_device+0x78/0x12c
	[    1.579556]  driver_probe_device+0xd8/0x15c
	[    1.579564]  __device_attach_driver+0xb8/0x134
	[    1.579573]  bus_for_each_drv+0x84/0xe0
	[    1.579580]  __device_attach+0x9c/0x188
	[    1.579588]  device_initial_probe+0x14/0x20
	[    1.579596]  bus_probe_device+0xac/0xb0
	[    1.579603]  deferred_probe_work_func+0x88/0xc0
	[    1.579611]  process_one_work+0x148/0x28c
	[    1.579623]  worker_thread+0x2e8/0x3f8
	[    1.579633]  kthread+0x110/0x114
	[    1.579641]  ret_from_fork+0x10/0x20
	[    1.579653] Code: aa1703e0 52800021 97e38ed5 17ffffea (d4210000)
	[    1.579657] ---[ end trace 0000000000000000 ]---
	[    1.851078] note: kworker/u16:0[11] exited with irqs disabled
	[    1.855791] note: kworker/u16:0[11] exited with preempt_count 1
	[    1.861586] ------------[ cut here ]------------

Randomly, the following call seems to return -EBUSY causing
the above BUG().

	ret = __cpufreq_driver_target(policy, old_freq - 1,
				      CPUFREQ_RELATION_L);

	/*
	 * Reaching here after boot in a few seconds may not
	 * mean that system will remain stable at "unknown"
	 * frequency for longer duration. Hence, a BUG_ON().
	 */
	BUG_ON(ret);

Not sure why this does not happen in every boot, and how it
is tied to genpd_names. Will debug and update.

Thanks
Varada

> >  };
> >
> >  static const struct qcom_cpufreq_match_data match_data_krait = {
> > --
> > 2.34.1
> >
>
> --
> With best wishes
> Dmitry

Re: [PATCH v3 2/9] cpufreq: qcom-nvmem: Add genpd names to match_data_kryo

[Dmitry Baryshkov]

On Fri, Jun 28, 2024 at 12:02:48PM GMT, Varadarajan Narayanan wrote:
> On Wed, Jun 26, 2024 at 09:23:17PM +0300, Dmitry Baryshkov wrote:
> > On Wed, Jun 26, 2024 at 04:09:55PM GMT, Varadarajan Narayanan wrote:
> > > This is used for tying up the cpu@N nodes with the power domains.
> > > Without this, 'cat /sys/kernel/debug/qcom_cpr3/thread0'
> > > crashes with NULL pointer access.
> >
> > Add the interesting part of the backtrace, please.
> 
>         if (thread->drv->desc->cpr_type < CTRL_TYPE_CPRH) {
>                 seq_printf(s, "current_volt = %d uV\n", thread->drv->last_uV);
>                 seq_printf(s, "requested voltage: %d uV\n", thread->corner->last_uV);
>         }
> 
> thread->corner is NULL in the second printf above.
> 
> 	# cat /sys/kernel/debug/qcom_cpr3/thread0
> 	[   16.965241] Unable to handle kernel NULL pointer dereference at virtual address 000000000000000c
> 	[   16.965270] Mem abort info:
> 	[   16.973181]   ESR = 0x0000000096000004
> 	[   16.975607]   EC = 0x25: DABT (current EL), IL = 32 bits
> 	[   16.979425]   SET = 0, FnV = 0
> 	[   16.984889]   EA = 0, S1PTW = 0
> 	[   16.987756]   FSC = 0x04: level 0 translation fault
> 	[   16.990792] Data abort info:
> 	[   16.995652]   ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
> 	[   16.998779]   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> 	[   17.004074]   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> 	[   17.009196] user pgtable: 4k pages, 48-bit VAs, pgdp=00000000481b1000
> 	[   17.014579] [000000000000000c] pgd=0000000000000000, p4d=0000000000000000
> 	[   17.020919] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
> 	[   17.020921] Modules linked in:
> 	[   17.020926] CPU: 0 UID: 0 PID: 118 Comm: cat Not tainted 6.10.0-rc4-next-20240620-00020-g125eb3184fc1-dirty #9
> 	[   17.020931] Hardware name: Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7 (DT)
> 	[   17.020933] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> 	[   17.020936] pc : cpr3_debug_info_show+0x3a0/0x3ac
> 	[   17.020945] lr : cpr3_debug_info_show+0x390/0x3ac
> 	[   17.020948] sp : ffff800086293b90
> 	[   17.020949] x29: ffff800086293b90 x28: ffff0000034ae038 x27: 0000000000400cc0
> 	[   17.020953] x26: 000000007ffff000 x25: ffff0000034ae028 x24: 0000000000000000
> 	[   17.020957] x23: ffff800086293c80 x22: ffff000002399880 x21: ffff000002a8fa80
> 	[   17.020960] x20: ffff0000034ae000 x19: 0000000000000000 x18: ffffffffffffffff
> 	[   17.020964] x17: 0000000000000000 x16: 0000000000000000 x15: ffff800086293a40
> 	[   17.020967] x14: ffff000002913000 x13: ffff00000291200f x12: 0000000000000000
> 	[   17.020970] x11: 0000000000000000 x10: 0000000000000000 x9 : ffff0000034a9000
> 	[   17.020973] x8 : 000000000a567520 x7 : 0000000000000001 x6 : 000000000a567520
> 	[   17.020976] x5 : ffff000002912014 x4 : ffff800080e1f3a5 x3 : 0000000000000014
> 	[   17.020979] x2 : 0000000000000000 x1 : ffff800080e1f848 x0 : ffff0000034ae000
> 	[   17.020983] Call trace:
> 	[   17.020984]  cpr3_debug_info_show+0x3a0/0x3ac
> 	[   17.020987]  seq_read_iter+0xe0/0x45c
> 	[   17.020993]  seq_read+0xec/0x130
> 	[   17.020996]  full_proxy_read+0x60/0xb4
> 	[   17.020999]  vfs_read+0xc0/0x31c
> 	[   17.021003]  ksys_read+0x70/0x104
> 	[   17.021006]  __arm64_sys_read+0x1c/0x28
> 	[   17.021008]  invoke_syscall+0x48/0x114
> 	[   17.021014]  el0_svc_common+0x3c/0xe8
> 	[   17.021017]  do_el0_svc+0x20/0x2c
> 	[   17.021020]  el0_svc+0x34/0xd8
> 	[   17.021024]  el0t_64_sync_handler+0x120/0x12c
> 	[   17.021027]  el0t_64_sync+0x190/0x194
> 	[   17.021031] Code: f94012c2 aa1403e0 b0004701 91212021 (b9400c42)
> 	[   17.021033] ---[ end trace 0000000000000000 ]---
> 	Segmentation fault

Well, I asked to add it, so please drop the timestamps and registers and
include it into the commit message. While you are at it, please review
Documentation/process/submitting-patches.rst and change the commit
message to follow the guidelines.

While doing so (and while responding to a comment below) you will notice
that this change should not be applied to the generic match_data_kryo
instance. Instead you should add a device-specific entry into match
table and use struct qcom_cpufreq_match_data instance that has
.genpd_names set.

> 
> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > ---
> > >  drivers/cpufreq/qcom-cpufreq-nvmem.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > > index 939702dfa73f..5e6525c7788c 100644
> > > --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > > +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > > @@ -399,6 +399,7 @@ static const char *generic_genpd_names[] = { "perf", NULL };
> > >
> > >  static const struct qcom_cpufreq_match_data match_data_kryo = {
> > >  	.get_version = qcom_cpufreq_kryo_name_version,
> > > +	.genpd_names = generic_genpd_names,
> >
> > This forces that every Kryo SoC has "perf" genpd, which obviously isn't
> > corret (at least from the upstream support point of view).
> 
> While trying to get the above backtrace, randomly during boot
> I see the following BUG too.

This isn't a response to my comment.

> 
> 	[    1.562847] ------------[ cut here ]------------
> 	[    1.574342] kernel BUG at drivers/cpufreq/cpufreq.c:1542!
> 	[    1.579203] Internal error: Oops - BUG: 00000000f2000800 [#1] PREEMPT SMP
> 	[    1.579209] Modules linked in:
> 	[    1.579217] CPU: 2 UID: 0 PID: 11 Comm: kworker/u16:0 Not tainted 6.10.0-rc4-next-20240620-00020-g125eb3184fc1-dirty #10
> 	[    1.579227] Hardware name: Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7 (DT)
> 	[    1.579232] Workqueue: events_unbound deferred_probe_work_func
> 	[    1.579249] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> 	[    1.579257] pc : cpufreq_online+0x938/0x954
> 	[    1.579271] lr : cpufreq_online+0x788/0x954
> 	[    1.579281] sp : ffff8000817c3520
> 	[    1.579283] x29: ffff8000817c3520 x28: ffff0000029efa50 x27: 0000000000000001
> 	[    1.579294] x26: 0000000000000001 x25: ffff8000814d8da0 x24: 0000000000000000
> 	[    1.579303] x23: ffff0000029ef9d0 x22: ffff800081735000 x21: 0000000000000000
> 	[    1.579312] x20: 00000000000c15c0 x19: ffff0000029ef800 x18: ffff00000183481c
> 	[    1.579321] x17: ffff8000818a3638 x16: 0000000000000000 x15: ffff8000818a3670
> 	[    1.579330] x14: 0000000000000003 x13: ffff00000192b140 x12: ffff8000814d8c58
> 	[    1.579338] x11: ffff00000192b140 x10: 00000000000009b0 x9 : ffff8000817c3240
> 	[    1.579347] x8 : ffff00000192bad0 x7 : 0000000000000001 x6 : ffff8000814d8da0
> 	[    1.579355] x5 : ffff8000812c32d0 x4 : 0000000000000000 x3 : 0000000000000000
> 	[    1.579363] x2 : 0000000000000000 x1 : 0000000000000000 x0 : 00000000fffffff0
> 	[    1.579372] Call trace:
> 	[    1.579375]  cpufreq_online+0x938/0x954
> 	[    1.579386]  cpufreq_add_dev+0x80/0x98
> 	[    1.579395]  subsys_interface_register+0x100/0x130
> 	[    1.579404]  cpufreq_register_driver+0x150/0x244
> 	[    1.579413]  dt_cpufreq_probe+0x8c/0x440
> 	[    1.579420]  platform_probe+0x68/0xc8
> 	[    1.579430]  really_probe+0xbc/0x29c
> 	[    1.579438]  __driver_probe_device+0x78/0x12c
> 	[    1.579446]  driver_probe_device+0xd8/0x15c
> 	[    1.579454]  __device_attach_driver+0xb8/0x134
> 	[    1.579463]  bus_for_each_drv+0x84/0xe0
> 	[    1.579470]  __device_attach+0x9c/0x188
> 	[    1.579478]  device_initial_probe+0x14/0x20
> 	[    1.579487]  bus_probe_device+0xac/0xb0
> 	[    1.579494]  device_add+0x55c/0x720
> 	[    1.579500]  platform_device_add+0x1b8/0x244
> 	[    1.579510]  platform_device_register_full+0xfc/0x184
> 	[    1.579516]  platform_device_register_resndata.constprop.0+0x5c/0x8c
> 	[    1.579524]  qcom_cpufreq_probe+0x1e4/0x498
> 	[    1.579531]  platform_probe+0x68/0xc8
> 	[    1.579540]  really_probe+0xbc/0x29c
> 	[    1.579548]  __driver_probe_device+0x78/0x12c
> 	[    1.579556]  driver_probe_device+0xd8/0x15c
> 	[    1.579564]  __device_attach_driver+0xb8/0x134
> 	[    1.579573]  bus_for_each_drv+0x84/0xe0
> 	[    1.579580]  __device_attach+0x9c/0x188
> 	[    1.579588]  device_initial_probe+0x14/0x20
> 	[    1.579596]  bus_probe_device+0xac/0xb0
> 	[    1.579603]  deferred_probe_work_func+0x88/0xc0
> 	[    1.579611]  process_one_work+0x148/0x28c
> 	[    1.579623]  worker_thread+0x2e8/0x3f8
> 	[    1.579633]  kthread+0x110/0x114
> 	[    1.579641]  ret_from_fork+0x10/0x20
> 	[    1.579653] Code: aa1703e0 52800021 97e38ed5 17ffffea (d4210000)
> 	[    1.579657] ---[ end trace 0000000000000000 ]---
> 	[    1.851078] note: kworker/u16:0[11] exited with irqs disabled
> 	[    1.855791] note: kworker/u16:0[11] exited with preempt_count 1
> 	[    1.861586] ------------[ cut here ]------------
> 
> Randomly, the following call seems to return -EBUSY causing
> the above BUG().
> 
> 	ret = __cpufreq_driver_target(policy, old_freq - 1,
> 				      CPUFREQ_RELATION_L);
> 
> 	/*
> 	 * Reaching here after boot in a few seconds may not
> 	 * mean that system will remain stable at "unknown"
> 	 * frequency for longer duration. Hence, a BUG_ON().
> 	 */
> 	BUG_ON(ret);
> 
> Not sure why this does not happen in every boot, and how it
> is tied to genpd_names. Will debug and update.

Thanks!

-- 
With best wishes
Dmitry

Re: [PATCH v3 8/9] soc: qcom: cpr3: Add IPQ9574 definitions

[Varadarajan Narayanan]

On Thu, Jun 27, 2024 at 04:46:05PM +0300, Dmitry Baryshkov wrote:
> On Thu, Jun 27, 2024 at 12:53:18PM GMT, Varadarajan Narayanan wrote:
> > On Wed, Jun 26, 2024 at 09:27:53PM +0300, Dmitry Baryshkov wrote:
> > > On Wed, Jun 26, 2024 at 04:10:01PM GMT, Varadarajan Narayanan wrote:
> > > > From: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > >
> > > > Add thread, scaling factor, CPR descriptor defines to enable CPR
> > > > on IPQ9574.
> > > >
> > > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > > ---
> > > > v3: Fix patch author
> > > >     Included below information in cover letter
> > > > v2: Fix Signed-off-by order
> > > > Depends:
> > > > 	[1] https://lore.kernel.org/lkml/20230217-topic-cpr3h-v14-0-9fd23241493d@linaro.org/T/
> > > > 	[2] https://github.com/quic-varada/cpr/commits/konrad/
> > > > ---
> > > >  drivers/pmdomain/qcom/cpr3.c | 137 +++++++++++++++++++++++++++++++++++
> > > >  1 file changed, 137 insertions(+)
> > > >
> > > > diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c
> > > > index c28028be50d8..66c8a4bd9adc 100644
> > > > --- a/drivers/pmdomain/qcom/cpr3.c
> > > > +++ b/drivers/pmdomain/qcom/cpr3.c
> > >
> > > > +
> > > > +static const struct cpr_desc ipq9574_cpr_desc = {
> > > > +	.cpr_type = CTRL_TYPE_CPR4,
> > >
> > > So, is it CPR4 or CPRh?
> >
> > CPR4.
>
> Then why do you have cprh in the compatible?

Sorry, copy-paste from msm8998. Will fix that in the next version.

Thanks
Varada

> > > > +	.num_threads = 1,
> > > > +	.apm_threshold = 850000,
> > > > +	.apm_crossover = 880000,
> > > > +	.apm_hysteresis = 0,
> > > > +	.cpr_base_voltage = 700000,
> > > > +	.cpr_max_voltage = 1100000,
> > > > +	.timer_delay_us = 5000,
> > > > +	.timer_cons_up = 0,
> > > > +	.timer_cons_down = 0,
> > > > +	.up_threshold = 2,
> > > > +	.down_threshold = 2,
> > > > +	.idle_clocks = 15,
> > > > +	.count_mode = CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN,
> > > > +	.count_repeat = 1,
> > > > +	.gcnt_us = 1,
> > > > +	.vreg_step_fixed = 12500,
> > > > +	.vreg_step_up_limit = 1,
> > > > +	.vreg_step_down_limit = 1,
> > > > +	.vdd_settle_time_us = 34,
> > > > +	.corner_settle_time_us = 6,
> > > > +	.reduce_to_corner_uV = true,
> > > > +	.hw_closed_loop_en = false,
> > > > +	.threads = (const struct cpr_thread_desc *[]) {
> > > > +		&ipq9574_thread_silver,
> > >
> > > If it's silver, where is gold or bronze?
> >
> > Will rename this as "ipq9574_thread"
> >
> > Thanks
> > Varada
> >
> > > > +	},
> > > > +};
> > > > +
> > > > +static const struct cpr_acc_desc ipq9574_cpr_acc_desc = {
> > > > +	.cpr_desc = &ipq9574_cpr_desc,
> > > > +};
> > > > +
> > > >  static const int sdm630_gold_scaling_factor[][CPR3_RO_COUNT] = {
> > > >  	/* Same RO factors for all fuse corners */
> > > >  	{
> > > > @@ -2828,6 +2964,7 @@ static void cpr_remove(struct platform_device *pdev)
> > > >  }
> > > >
> > > >  static const struct of_device_id cpr3_match_table[] = {
> > > > +	{ .compatible = "qcom,ipq9574-cprh", .data = &ipq9574_cpr_acc_desc },
> > > >  	{ .compatible = "qcom,msm8998-cprh", .data = &msm8998_cpr_acc_desc },
> > > >  	{ .compatible = "qcom,sdm630-cprh", .data = &sdm630_cpr_acc_desc },
> > > >  	{ }
> > > > --
> > > > 2.34.1
> > > >
> > >
> > > --
> > > With best wishes
> > > Dmitry
>
> --
> With best wishes
> Dmitry

Re: [PATCH v3 2/9] cpufreq: qcom-nvmem: Add genpd names to match_data_kryo

[Varadarajan Narayanan]

On Fri, Jun 28, 2024 at 10:40:23AM +0300, Dmitry Baryshkov wrote:
> On Fri, Jun 28, 2024 at 12:02:48PM GMT, Varadarajan Narayanan wrote:
> > On Wed, Jun 26, 2024 at 09:23:17PM +0300, Dmitry Baryshkov wrote:
> > > On Wed, Jun 26, 2024 at 04:09:55PM GMT, Varadarajan Narayanan wrote:
> > > > This is used for tying up the cpu@N nodes with the power domains.
> > > > Without this, 'cat /sys/kernel/debug/qcom_cpr3/thread0'
> > > > crashes with NULL pointer access.
> > >
> > > Add the interesting part of the backtrace, please.

Sure.

> >
> >         if (thread->drv->desc->cpr_type < CTRL_TYPE_CPRH) {
> >                 seq_printf(s, "current_volt = %d uV\n", thread->drv->last_uV);
> >                 seq_printf(s, "requested voltage: %d uV\n", thread->corner->last_uV);
> >         }
> >
> > thread->corner is NULL in the second printf above.
> >
> > 	# cat /sys/kernel/debug/qcom_cpr3/thread0
> > 	[   16.965241] Unable to handle kernel NULL pointer dereference at virtual address 000000000000000c
> > 	[   16.965270] Mem abort info:
> > 	[   16.973181]   ESR = 0x0000000096000004
> > 	[   16.975607]   EC = 0x25: DABT (current EL), IL = 32 bits
> > 	[   16.979425]   SET = 0, FnV = 0
> > 	[   16.984889]   EA = 0, S1PTW = 0
> > 	[   16.987756]   FSC = 0x04: level 0 translation fault
> > 	[   16.990792] Data abort info:
> > 	[   16.995652]   ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
> > 	[   16.998779]   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> > 	[   17.004074]   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> > 	[   17.009196] user pgtable: 4k pages, 48-bit VAs, pgdp=00000000481b1000
> > 	[   17.014579] [000000000000000c] pgd=0000000000000000, p4d=0000000000000000
> > 	[   17.020919] Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
> > 	[   17.020921] Modules linked in:
> > 	[   17.020926] CPU: 0 UID: 0 PID: 118 Comm: cat Not tainted 6.10.0-rc4-next-20240620-00020-g125eb3184fc1-dirty #9
> > 	[   17.020931] Hardware name: Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7 (DT)
> > 	[   17.020933] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> > 	[   17.020936] pc : cpr3_debug_info_show+0x3a0/0x3ac
> > 	[   17.020945] lr : cpr3_debug_info_show+0x390/0x3ac
> > 	[   17.020948] sp : ffff800086293b90
> > 	[   17.020949] x29: ffff800086293b90 x28: ffff0000034ae038 x27: 0000000000400cc0
> > 	[   17.020953] x26: 000000007ffff000 x25: ffff0000034ae028 x24: 0000000000000000
> > 	[   17.020957] x23: ffff800086293c80 x22: ffff000002399880 x21: ffff000002a8fa80
> > 	[   17.020960] x20: ffff0000034ae000 x19: 0000000000000000 x18: ffffffffffffffff
> > 	[   17.020964] x17: 0000000000000000 x16: 0000000000000000 x15: ffff800086293a40
> > 	[   17.020967] x14: ffff000002913000 x13: ffff00000291200f x12: 0000000000000000
> > 	[   17.020970] x11: 0000000000000000 x10: 0000000000000000 x9 : ffff0000034a9000
> > 	[   17.020973] x8 : 000000000a567520 x7 : 0000000000000001 x6 : 000000000a567520
> > 	[   17.020976] x5 : ffff000002912014 x4 : ffff800080e1f3a5 x3 : 0000000000000014
> > 	[   17.020979] x2 : 0000000000000000 x1 : ffff800080e1f848 x0 : ffff0000034ae000
> > 	[   17.020983] Call trace:
> > 	[   17.020984]  cpr3_debug_info_show+0x3a0/0x3ac
> > 	[   17.020987]  seq_read_iter+0xe0/0x45c
> > 	[   17.020993]  seq_read+0xec/0x130
> > 	[   17.020996]  full_proxy_read+0x60/0xb4
> > 	[   17.020999]  vfs_read+0xc0/0x31c
> > 	[   17.021003]  ksys_read+0x70/0x104
> > 	[   17.021006]  __arm64_sys_read+0x1c/0x28
> > 	[   17.021008]  invoke_syscall+0x48/0x114
> > 	[   17.021014]  el0_svc_common+0x3c/0xe8
> > 	[   17.021017]  do_el0_svc+0x20/0x2c
> > 	[   17.021020]  el0_svc+0x34/0xd8
> > 	[   17.021024]  el0t_64_sync_handler+0x120/0x12c
> > 	[   17.021027]  el0t_64_sync+0x190/0x194
> > 	[   17.021031] Code: f94012c2 aa1403e0 b0004701 91212021 (b9400c42)
> > 	[   17.021033] ---[ end trace 0000000000000000 ]---
> > 	Segmentation fault
>
> Well, I asked to add it, so please drop the timestamps and registers and
> include it into the commit message. While you are at it, please review
> Documentation/process/submitting-patches.rst and change the commit
> message to follow the guidelines.
>
> While doing so (and while responding to a comment below) you will notice
> that this change should not be applied to the generic match_data_kryo
> instance. Instead you should add a device-specific entry into match
> table and use struct qcom_cpufreq_match_data instance that has
> .genpd_names set.

Ok, will add a new match data for IPQ9574.

> > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > > ---
> > > >  drivers/cpufreq/qcom-cpufreq-nvmem.c | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > > > index 939702dfa73f..5e6525c7788c 100644
> > > > --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > > > +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > > > @@ -399,6 +399,7 @@ static const char *generic_genpd_names[] = { "perf", NULL };
> > > >
> > > >  static const struct qcom_cpufreq_match_data match_data_kryo = {
> > > >  	.get_version = qcom_cpufreq_kryo_name_version,
> > > > +	.genpd_names = generic_genpd_names,
> > >
> > > This forces that every Kryo SoC has "perf" genpd, which obviously isn't
> > > corret (at least from the upstream support point of view).

Understand, will have a different match data for IPQ9574.

> > While trying to get the above backtrace, randomly during boot
> > I see the following BUG too.
>
> This isn't a response to my comment.

Sorry, felt that genpd_names would be needed for kryo CPUs too
and wanted to bring this BUG() to your attention. Was wondering
how kryo CPUs didn't face the following BUG(). Since this BUG()
was hitting occasionally, assumed it could be some boot time
driver probe order/timing related race that was getting masked in
kryo CPUs but occuring in IQP9574.

> > 	[    1.562847] ------------[ cut here ]------------
> > 	[    1.574342] kernel BUG at drivers/cpufreq/cpufreq.c:1542!
> > 	[    1.579203] Internal error: Oops - BUG: 00000000f2000800 [#1] PREEMPT SMP
> > 	[    1.579209] Modules linked in:
> > 	[    1.579217] CPU: 2 UID: 0 PID: 11 Comm: kworker/u16:0 Not tainted 6.10.0-rc4-next-20240620-00020-g125eb3184fc1-dirty #10
> > 	[    1.579227] Hardware name: Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7 (DT)
> > 	[    1.579232] Workqueue: events_unbound deferred_probe_work_func
> > 	[    1.579249] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> > 	[    1.579257] pc : cpufreq_online+0x938/0x954
> > 	[    1.579271] lr : cpufreq_online+0x788/0x954
> > 	[    1.579281] sp : ffff8000817c3520
> > 	[    1.579283] x29: ffff8000817c3520 x28: ffff0000029efa50 x27: 0000000000000001
> > 	[    1.579294] x26: 0000000000000001 x25: ffff8000814d8da0 x24: 0000000000000000
> > 	[    1.579303] x23: ffff0000029ef9d0 x22: ffff800081735000 x21: 0000000000000000
> > 	[    1.579312] x20: 00000000000c15c0 x19: ffff0000029ef800 x18: ffff00000183481c
> > 	[    1.579321] x17: ffff8000818a3638 x16: 0000000000000000 x15: ffff8000818a3670
> > 	[    1.579330] x14: 0000000000000003 x13: ffff00000192b140 x12: ffff8000814d8c58
> > 	[    1.579338] x11: ffff00000192b140 x10: 00000000000009b0 x9 : ffff8000817c3240
> > 	[    1.579347] x8 : ffff00000192bad0 x7 : 0000000000000001 x6 : ffff8000814d8da0
> > 	[    1.579355] x5 : ffff8000812c32d0 x4 : 0000000000000000 x3 : 0000000000000000
> > 	[    1.579363] x2 : 0000000000000000 x1 : 0000000000000000 x0 : 00000000fffffff0
> > 	[    1.579372] Call trace:
> > 	[    1.579375]  cpufreq_online+0x938/0x954
> > 	[    1.579386]  cpufreq_add_dev+0x80/0x98
> > 	[    1.579395]  subsys_interface_register+0x100/0x130
> > 	[    1.579404]  cpufreq_register_driver+0x150/0x244
> > 	[    1.579413]  dt_cpufreq_probe+0x8c/0x440
> > 	[    1.579420]  platform_probe+0x68/0xc8
> > 	[    1.579430]  really_probe+0xbc/0x29c
> > 	[    1.579438]  __driver_probe_device+0x78/0x12c
> > 	[    1.579446]  driver_probe_device+0xd8/0x15c
> > 	[    1.579454]  __device_attach_driver+0xb8/0x134
> > 	[    1.579463]  bus_for_each_drv+0x84/0xe0
> > 	[    1.579470]  __device_attach+0x9c/0x188
> > 	[    1.579478]  device_initial_probe+0x14/0x20
> > 	[    1.579487]  bus_probe_device+0xac/0xb0
> > 	[    1.579494]  device_add+0x55c/0x720
> > 	[    1.579500]  platform_device_add+0x1b8/0x244
> > 	[    1.579510]  platform_device_register_full+0xfc/0x184
> > 	[    1.579516]  platform_device_register_resndata.constprop.0+0x5c/0x8c
> > 	[    1.579524]  qcom_cpufreq_probe+0x1e4/0x498
> > 	[    1.579531]  platform_probe+0x68/0xc8
> > 	[    1.579540]  really_probe+0xbc/0x29c
> > 	[    1.579548]  __driver_probe_device+0x78/0x12c
> > 	[    1.579556]  driver_probe_device+0xd8/0x15c
> > 	[    1.579564]  __device_attach_driver+0xb8/0x134
> > 	[    1.579573]  bus_for_each_drv+0x84/0xe0
> > 	[    1.579580]  __device_attach+0x9c/0x188
> > 	[    1.579588]  device_initial_probe+0x14/0x20
> > 	[    1.579596]  bus_probe_device+0xac/0xb0
> > 	[    1.579603]  deferred_probe_work_func+0x88/0xc0
> > 	[    1.579611]  process_one_work+0x148/0x28c
> > 	[    1.579623]  worker_thread+0x2e8/0x3f8
> > 	[    1.579633]  kthread+0x110/0x114
> > 	[    1.579641]  ret_from_fork+0x10/0x20
> > 	[    1.579653] Code: aa1703e0 52800021 97e38ed5 17ffffea (d4210000)
> > 	[    1.579657] ---[ end trace 0000000000000000 ]---
> > 	[    1.851078] note: kworker/u16:0[11] exited with irqs disabled
> > 	[    1.855791] note: kworker/u16:0[11] exited with preempt_count 1
> > 	[    1.861586] ------------[ cut here ]------------
> >
> > Randomly, the following call seems to return -EBUSY causing
> > the above BUG().
> >
> > 	ret = __cpufreq_driver_target(policy, old_freq - 1,
> > 				      CPUFREQ_RELATION_L);
> >
> > 	/*
> > 	 * Reaching here after boot in a few seconds may not
> > 	 * mean that system will remain stable at "unknown"
> > 	 * frequency for longer duration. Hence, a BUG_ON().
> > 	 */
> > 	BUG_ON(ret);
> >
> > Not sure why this does not happen in every boot, and how it
> > is tied to genpd_names. Will debug and update.

qcom_cpufreq_probe invokes dev_pm_opp_set_config if either
genpd_names or get_version is set in qcom_cpufreq_match_data.
If genpd_names is available, dev_pm_opp_set_config calls
_opp_attach_genpd giving genpd_names as an input. This in turn
calls dev_pm_domain_attach_by_name and binds the CPU device with
the OPP tables etc. Sometimes, the pm_domain driver is probed by
this time and sometimes it is not. When it is not probed,
qcom_cpufreq_probe is also held back via the EPROBE_DEFER
mechanism. This in turn holds back the cpufreq driver probe.

When genpd_names is not set in match_data_kryo,
dev_pm_opp_set_config doesn't call _opp_attach_genpd. Hence,
regardless of pm_domain driver's probe status, qcom_cpufreq_probe
completes. This allows the cpufreq driver's probe to proceed. The
cpufreq driver tries to set some frequency based on the
opp-tables. At this point if pm_domain driver is probed, the
frequency change goes through. If pm_domain is not probed yet,
the above BUG() happens.

Will post the next version shortly with this and the other
comments addressed. Please take a look.

Thanks
Varada