* [PATCH 0/2] Add device tree for ASRock Rack ALTRAD8 BMC @ 2025-09-11 5:10 Rebecca Cran 2025-09-11 5:10 ` [PATCH 1/2] dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board Rebecca Cran 2025-09-11 5:10 ` [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC Rebecca Cran 0 siblings, 2 replies; 15+ messages in thread From: Rebecca Cran @ 2025-09-11 5:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel Cc: Rebecca Cran The ASRock Rack ALTRAD8 BMC is an Aspeed AST2500-based BMC for the ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q boards with an Ampere Altra processor. The BMC runs OpenBMC. These patches add a device tree and binding for the BMC. Rebecca Cran (2): dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + arch/arm/boot/dts/aspeed/Makefile | 1 + arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts | 647 ++++++++++++++++++++ 3 files changed, 649 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts base-commit: 7aac71907bdea16e2754a782b9d9155449a9d49d -- 2.47.3 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/2] dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board 2025-09-11 5:10 [PATCH 0/2] Add device tree for ASRock Rack ALTRAD8 BMC Rebecca Cran @ 2025-09-11 5:10 ` Rebecca Cran 2025-09-11 6:29 ` Krzysztof Kozlowski 2025-09-11 5:10 ` [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC Rebecca Cran 1 sibling, 1 reply; 15+ messages in thread From: Rebecca Cran @ 2025-09-11 5:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel Cc: Rebecca Cran Document ASRock Rack ALTRAD8 (ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q) compatibles. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 456dbf7b5ec8..7d5c6bfaeb97 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -34,6 +34,7 @@ properties: - amd,ethanolx-bmc - ampere,mtjade-bmc - aspeed,ast2500-evb + - asrock,altrad8-bmc - asrock,e3c246d4i-bmc - asrock,e3c256d4i-bmc - asrock,romed8hm3-bmc -- 2.47.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board 2025-09-11 5:10 ` [PATCH 1/2] dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board Rebecca Cran @ 2025-09-11 6:29 ` Krzysztof Kozlowski 0 siblings, 0 replies; 15+ messages in thread From: Krzysztof Kozlowski @ 2025-09-11 6:29 UTC (permalink / raw) To: Rebecca Cran, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On 11/09/2025 07:10, Rebecca Cran wrote: > Document ASRock Rack ALTRAD8 (ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q) > compatibles. > > Signed-off-by: Rebecca Cran <rebecca@bsdio.com> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> <form letter> This is an automated instruction, just in case, because many review tags are being ignored. If you know the process, just skip it entirely (please do not feel offended by me posting it here - no bad intentions intended, no patronizing, I just want to avoid wasted efforts). If you do not know the process, here is a short explanation: Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions of patchset, under or above your Signed-off-by tag, unless patch changed significantly (e.g. new properties added to the DT bindings). Tag is "received", when provided in a message replied to you on the mailing list. Tools like b4 can help here ('b4 trailers -u ...'). However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for tags received on the version they apply. Full context and explanation: https://elixir.bootlin.com/linux/v6.15/source/Documentation/process/submitting-patches.rst#L591 </form letter> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-11 5:10 [PATCH 0/2] Add device tree for ASRock Rack ALTRAD8 BMC Rebecca Cran 2025-09-11 5:10 ` [PATCH 1/2] dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board Rebecca Cran @ 2025-09-11 5:10 ` Rebecca Cran 2025-09-11 6:29 ` Krzysztof Kozlowski ` (2 more replies) 1 sibling, 3 replies; 15+ messages in thread From: Rebecca Cran @ 2025-09-11 5:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel Cc: Rebecca Cran The ALTRAD8 BMC is an Aspeed AST2500-based BMC for the ASRock Rack ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q boards. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> --- arch/arm/boot/dts/aspeed/Makefile | 1 + arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts | 647 ++++++++++++++++++++ 2 files changed, 648 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index aba7451ab749..6bffb7130839 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-ampere-mtjefferson.dtb \ aspeed-bmc-ampere-mtmitchell.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ + aspeed-bmc-asrock-altrad8.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ aspeed-bmc-asrock-e3c256d4i.dtb \ aspeed-bmc-asrock-romed8hm3.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts new file mode 100644 index 000000000000..61f6cf8018c0 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts @@ -0,0 +1,647 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/i2c/i2c.h> + +/ { + model = "ASRock ALTRAD8 BMC"; + compatible = "asrock,altrad8-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + i2c50 = &m2_2; + i2c51 = &pcie4; + i2c52 = &pcie5; + i2c53 = &pcie6; + i2c54 = &pcie7; + i2c55 = &ocu_2; + i2c56 = &ocu_1; + i2c57 = &m2_1; + i2c58 = &slim1_1; + i2c59 = &slim2_1; + i2c60 = &slim3_1; + i2c61 = &slim4_1; + i2c62 = &slim1_2; + i2c63 = &slim2_2; + i2c64 = &slim3_2; + i2c65 = &slim4_2; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + systemfault { + gpios = <&gpio ASPEED_GPIO(G,3) GPIO_ACTIVE_LOW>; + label = "platform:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + + enclosure_identify { + gpios = <&gpio ASPEED_GPIO(G,0) GPIO_ACTIVE_LOW>; + label = "platform:green:indicator"; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + }; + }; + + leds-fanfail { + compatible = "gpio-leds"; + + fan1 { + retain-state-shutdown; + default-state = "off"; + gpios = <&pca0 0 GPIO_ACTIVE_LOW>; + label = "fan1:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + + fan2 { + retain-state-shutdown; + default-state = "off"; + gpios = <&pca0 1 GPIO_ACTIVE_LOW>; + label = "fan2:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + + fan3 { + retain-state-shutdown; + default-state = "off"; + gpios = <&pca0 2 GPIO_ACTIVE_LOW>; + label = "fan3:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + + fan4 { + retain-state-shutdown; + default-state = "off"; + gpios = <&pca0 3 GPIO_ACTIVE_LOW>; + label = "fan4:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + + fan5{ + retain-state-shutdown; + default-state = "off"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + label = "fan5:red:fault"; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_FAULT; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4> ,<&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + code@400000 { + reg = <0x400000 0x1C00000>; + label = "pnor-code"; + }; + tfa@400000 { + reg = <0x400000 0x200000>; + label = "pnor-tfa"; + }; + uefi@600000 { + reg = <0x600000 0x1A00000>; + label = "pnor-uefi"; + }; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_ncts1_default + &pinctrl_nrts1_default>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +/* The BMC's uart */ +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; + + nvmem-cells = <ð0_macaddress>; + nvmem-cell-names = "mac-address"; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; + + nvmem-cells = <ð1_macaddress>; + nvmem-cell-names = "mac-address"; +}; + +&i2c0 { + status = "okay"; + bus-frequency = <100000>; + + ipmb0@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; + +}; + +&i2c1 { + status = "okay"; + bus-frequency = <100000>; + + pca9548@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + m2_2: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + pcie4: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + pcie5: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + pcie6: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + pcie7: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + ocu_2: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + ocu_1: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + m2_1: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + pca9548@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + slim1_1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + slim2_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + slim3_1: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + slim4_1: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + slim1_2: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + slim2_2: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + slim3_2: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + slim4_2: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c2 { + status = "okay"; + bus-frequency = <100000>; + + smpro@4f { + compatible = "ampere,smpro"; + reg = <0x4f>; + }; +}; + +&i2c3 { + status = "okay"; + + power-supply@3c { + compatible = "pmbus"; + reg = <0x3c>; + }; + + /* PSU FRU */ + eeprom@38 { + compatible = "atmel,24c02"; + reg = <0x38>; + }; +}; + +&i2c4 { + status = "okay"; + bus-frequency = <100000>; + + nct7802@29 { + compatible = "nuvoton,nct7802"; + reg = <0x29>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + status = "okay"; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + sensor-type = "temperature"; + temperature-mode = "thermal-diode"; + }; + }; + + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + bus-frequency = <100000>; + + rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c7 { + status = "okay"; + bus-frequency = <100000>; + + /* BMC FRU */ + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eth0_macaddress: macaddress@3f88 { + reg = <0x3f88 6>; + }; + + eth1_macaddress: macaddress@3f80 { + reg = <0x3f80 6>; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + bus-frequency = <100000>; + + pca0: pca9557@1c { + compatible = "nxp,pca9557"; + reg = <0x1c>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + }; + gpio@1 { + reg = <1>; + }; + gpio@2 { + reg = <2>; + }; + gpio@3 { + reg = <3>; + }; + gpio@4 { + reg = <4>; + }; + gpio@5 { + reg = <5>; + }; + gpio@6 { + reg = <6>; + }; + gpio@7 { + reg = <7>; + }; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; + bus-frequency = <100000>; + + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +&vhub { + status = "okay"; +}; + + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&adc { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x08>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x09>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x0a>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0c>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0d>; + }; + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0e>; + }; + fan@7 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x07 0x0f>; + }; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","","BMC_READY","","","","", + /*B0-B7*/ "i2c-backup-sel","","","","","","","host0-shd-ack-n", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "POWER_BUTTON","POWER_OUT","RESET_BUTTON", + "host0-sysreset-n","","","SYS_PWR_GD","", + /*E0-E7*/ "","s0-vrd1-vddq0123-fault-l", + "s0-vrd1-vddq4567-fault-l","s0-vrd0-vddc-fault-l", + "s0-vrd3-p0v75-fault-l","","","", + /*F0-F7*/ "","","SYS_ATX_PSON_L","","","","","", + /*G0-G7*/ "id-led","id-button","","","UBOOT_READY",\ + "BMC_SALT2_L","","", + /*H0-H7*/ "PS_PWROK","uart1-mode1","uart2-mode1","uart3-mode1", + "uart4-mode1","","BMC_HB_LED","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "s0-hightemp-n","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","s0-spi-auth-fail-n","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","CPLD_DISABLE_BMC","","","","","", + /*Q0-Q7*/ "","","ext-hightemp-n","","","","", + "CHASSIS_INTRUSION", + /*R0-R7*/ "","","EXT_HIGHTEMP_L","spi0-program-sel","", + "HWM_BAT_EN","","", + /*S0-S7*/ "s0-vr-hot-n","","","BMC_SYSRESET_L","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "SIOS3","SIOS5","SIOPWREQ","SIOONCTRL","","","","", + /*Z0-Z7*/ "","SIOPWRGD","","s0-rtc-lock","","","","", + /*AA0-AA7*/ "RTC_INT","","","","","PMBUS_SEL_N","","", + /*AB0-AB7*/ "host0-reboot-ack-n","s0-sys-auth-failure-n", + "","","","","","", + /*AC0-AC7*/ "s0-fault-alert","host0-ready","s0-overtemp-n", + "","bmc-ok","host0-special-boot","presence-cpu0", + "host0-shd-req-n"; +}; -- 2.47.3 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-11 5:10 ` [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC Rebecca Cran @ 2025-09-11 6:29 ` Krzysztof Kozlowski 2025-09-12 23:37 ` Rebecca Cran 2025-09-11 14:09 ` Andrew Lunn 2025-09-15 5:02 ` Andrew Jeffery 2 siblings, 1 reply; 15+ messages in thread From: Krzysztof Kozlowski @ 2025-09-11 6:29 UTC (permalink / raw) To: Rebecca Cran, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On 11/09/2025 07:10, Rebecca Cran wrote: > The ALTRAD8 BMC is an Aspeed AST2500-based BMC for the ASRock Rack > ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q boards. > > Signed-off-by: Rebecca Cran <rebecca@bsdio.com> > --- > arch/arm/boot/dts/aspeed/Makefile | 1 + > arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts | 647 ++++++++++++++++++++ > 2 files changed, 648 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile > index aba7451ab749..6bffb7130839 100644 > --- a/arch/arm/boot/dts/aspeed/Makefile > +++ b/arch/arm/boot/dts/aspeed/Makefile > @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ > aspeed-bmc-ampere-mtjefferson.dtb \ > aspeed-bmc-ampere-mtmitchell.dtb \ > aspeed-bmc-arm-stardragon4800-rep2.dtb \ > + aspeed-bmc-asrock-altrad8.dtb \ > aspeed-bmc-asrock-e3c246d4i.dtb \ > aspeed-bmc-asrock-e3c256d4i.dtb \ > aspeed-bmc-asrock-romed8hm3.dtb \ > diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts > new file mode 100644 > index 000000000000..61f6cf8018c0 > --- /dev/null > +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts > @@ -0,0 +1,647 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/dts-v1/; > +#include "aspeed-g5.dtsi" > +#include <dt-bindings/gpio/aspeed-gpio.h> > +#include <dt-bindings/leds/common.h> > +#include <dt-bindings/i2c/i2c.h> > + > +/ { > + model = "ASRock ALTRAD8 BMC"; > + compatible = "asrock,altrad8-bmc", "aspeed,ast2500"; > + > + aliases { > + serial4 = &uart5; > + i2c50 = &m2_2; > + i2c51 = &pcie4; > + i2c52 = &pcie5; > + i2c53 = &pcie6; > + i2c54 = &pcie7; > + i2c55 = &ocu_2; > + i2c56 = &ocu_1; > + i2c57 = &m2_1; > + i2c58 = &slim1_1; > + i2c59 = &slim2_1; > + i2c60 = &slim3_1; > + i2c61 = &slim4_1; > + i2c62 = &slim1_2; > + i2c63 = &slim2_2; > + i2c64 = &slim3_2; > + i2c65 = &slim4_2; > + }; > + > + chosen { > + stdout-path = &uart5; > + bootargs = "console=ttyS4,115200 earlycon"; Please drop bootargs. Baud rate goes to stdout-path and earlycon is debugging tool, not suitable for mainline. > + }; > + > + memory@80000000 { > + reg = <0x80000000 0x20000000>; > + }; > + > + reserved-memory { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + gfx_memory: framebuffer { > + size = <0x01000000>; > + alignment = <0x01000000>; > + compatible = "shared-dma-pool"; > + reusable; > + }; > + > + vga_memory: framebuffer@9f000000 { > + no-map; > + reg = <0x9f000000 0x01000000>; /* 16M */ > + }; > + > + video_engine_memory: jpegbuffer { > + size = <0x02000000>; /* 32M */ > + alignment = <0x01000000>; > + compatible = "shared-dma-pool"; > + reusable; > + }; > + }; > + > + leds { > + compatible = "gpio-leds"; > + > + systemfault { Never tested. It does not look like you tested the DTS against bindings. Please run `make dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). Maybe you need to update your dtschema and yamllint. Don't rely on distro packages for dtschema and be sure you are using the latest released dtschema. > + gpios = <&gpio ASPEED_GPIO(G,3) GPIO_ACTIVE_LOW>; > + label = "platform:red:fault"; > + color = <LED_COLOR_ID_RED>; > + function = LED_FUNCTION_FAULT; > + }; > + > + enclosure_identify { > + gpios = <&gpio ASPEED_GPIO(G,0) GPIO_ACTIVE_LOW>; > + label = "platform:green:indicator"; > + color = <LED_COLOR_ID_GREEN>; > + function = LED_FUNCTION_INDICATOR; > + }; > + }; > + > + leds-fanfail { > + compatible = "gpio-leds"; > + > + fan1 { > + retain-state-shutdown; > + default-state = "off"; > + gpios = <&pca0 0 GPIO_ACTIVE_LOW>; > + label = "fan1:red:fault"; > + color = <LED_COLOR_ID_RED>; > + function = LED_FUNCTION_FAULT; > + }; > + > + fan2 { > + retain-state-shutdown; > + default-state = "off"; > + gpios = <&pca0 1 GPIO_ACTIVE_LOW>; > + label = "fan2:red:fault"; > + color = <LED_COLOR_ID_RED>; > + function = LED_FUNCTION_FAULT; > + }; > + > + fan3 { > + retain-state-shutdown; > + default-state = "off"; > + gpios = <&pca0 2 GPIO_ACTIVE_LOW>; > + label = "fan3:red:fault"; > + color = <LED_COLOR_ID_RED>; > + function = LED_FUNCTION_FAULT; > + }; > + > + fan4 { > + retain-state-shutdown; > + default-state = "off"; > + gpios = <&pca0 3 GPIO_ACTIVE_LOW>; > + label = "fan4:red:fault"; > + color = <LED_COLOR_ID_RED>; > + function = LED_FUNCTION_FAULT; > + }; > + > + fan5{ > + retain-state-shutdown; > + default-state = "off"; > + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; > + label = "fan5:red:fault"; > + color = <LED_COLOR_ID_RED>; > + function = LED_FUNCTION_FAULT; > + }; > + }; > + > + iio-hwmon { > + compatible = "iio-hwmon"; > + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, > + <&adc 4> ,<&adc 5>, <&adc 6>, <&adc 7>, > + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, > + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; > + }; > +}; > + > +&fmc { > + status = "okay"; > + flash@0 { > + status = "okay"; > + label = "bmc"; > + m25p,fast-read; > + spi-max-frequency = <50000000>; > +#include "openbmc-flash-layout-64.dtsi" > + }; > +}; > + > +&spi1 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_spi1_default>; > + > + flash@0 { > + status = "okay"; > + m25p,fast-read; > + label = "pnor"; > + spi-max-frequency = <100000000>; > + > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + code@400000 { > + reg = <0x400000 0x1C00000>; > + label = "pnor-code"; > + }; > + tfa@400000 { > + reg = <0x400000 0x200000>; > + label = "pnor-tfa"; > + }; > + uefi@600000 { > + reg = <0x600000 0x1A00000>; > + label = "pnor-uefi"; > + }; > + }; > + }; > +}; > + > +&uart1 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_txd1_default > + &pinctrl_rxd1_default > + &pinctrl_ncts1_default > + &pinctrl_nrts1_default>; > +}; > + > +&uart2 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_txd2_default > + &pinctrl_rxd2_default>; > +}; > + > +&uart3 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_txd3_default > + &pinctrl_rxd3_default>; > +}; > + > +&uart4 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_txd4_default > + &pinctrl_rxd4_default>; > +}; > + > +/* The BMC's uart */ > +&uart5 { > + status = "okay"; > +}; > + > +&mac0 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rmii1_default>; > + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, > + <&syscon ASPEED_CLK_MAC1RCLK>; > + clock-names = "MACCLK", "RCLK"; > + use-ncsi; > + > + nvmem-cells = <ð0_macaddress>; > + nvmem-cell-names = "mac-address"; > +}; > + > +&mac1 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; > + > + nvmem-cells = <ð1_macaddress>; > + nvmem-cell-names = "mac-address"; > +}; > + > +&i2c0 { > + status = "okay"; > + bus-frequency = <100000>; > + > + ipmb0@10 { 0 suffix is not generic. Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation If you cannot find a name matching your device, please check in kernel sources for similar cases or you can grow the spec (via pull request to DT spec repo). > + compatible = "ipmb-dev"; > + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; > + i2c-protocol; > + }; > + > +}; > + > +&i2c1 { > + status = "okay"; > + bus-frequency = <100000>; > + > + pca9548@73 { Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation If you cannot find a name matching your device, please check in kernel sources for similar cases or you can grow the spec (via pull request to DT spec repo). > + compatible = "nxp,pca9548"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x73>; > + i2c-mux-idle-disconnect; > + > + m2_2: i2c@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + }; > + > + pcie4: i2c@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <1>; > + }; > + > + pcie5: i2c@2 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <2>; > + }; > + > + pcie6: i2c@3 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <3>; > + }; > + > + pcie7: i2c@4 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <4>; > + }; > + > + ocu_2: i2c@5 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <5>; > + }; > + > + ocu_1: i2c@6 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <6>; > + }; > + > + m2_1: i2c@7 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <7>; > + }; > + }; > + > + pca9548@75 { Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation If you cannot find a name matching your device, please check in kernel sources for similar cases or you can grow the spec (via pull request to DT spec repo). ... and same comments everywhere else. Since this wasn't ever tested, I am not doing full review. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-11 6:29 ` Krzysztof Kozlowski @ 2025-09-12 23:37 ` Rebecca Cran 2025-09-15 4:51 ` Andrew Jeffery 0 siblings, 1 reply; 15+ messages in thread From: Rebecca Cran @ 2025-09-12 23:37 UTC (permalink / raw) To: Krzysztof Kozlowski, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On 9/11/25 00:29, Krzysztof Kozlowski wrote: > Never tested. > > It does not look like you tested the DTS against bindings. Please run > `make dtbs_check W=1` (see > Documentation/devicetree/bindings/writing-schema.rst or > https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ > for instructions). Am I doing something wrong, or are a certain number of validation issues expected? For example, I'm seeing these - most of which are from aspeed-g5.dtsi, not my dts file: arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: /ahb/apb/memory-controller@1e6e0000: failed to match any schema with compatible: ['aspeed,ast2500-sdram-edac'] arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: /ahb/apb/syscon@1e6e2000/p2a-control@2c: failed to match any schema with compatible: ['aspeed,ast2500-p2a-ctrl'] arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: /ahb/apb/display@1e6e6000: failed to match any schema with compatible: ['aspeed,ast2500-gfx', 'syscon'] arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: /ahb/apb/timer@1e782000: failed to match any schema with compatible: ['aspeed,ast2400-timer'] arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: /ahb/apb/pwm-tacho-controller@1e786000: failed to match any schema with compatible: ['aspeed,ast2500-pwm-tacho'] /home/bcran/src/linux/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: fan@0: aspeed,fan-tach-ch: b'\x00\x08' is not of type 'object', 'integer', 'array', 'boolean', 'null' from schema $id: http://devicetree.org/schemas/dt-core.yaml# ... /home/bcran/src/linux/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: lpc@1e789000 (aspeed,ast2500-lpc-v2): reg-io-width: 4 is not of type 'object' from schema $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# /home/bcran/src/linux/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: lpc@1e789000 (aspeed,ast2500-lpc-v2): lpc-snoop@90: 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# /home/bcran/src/linux/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: kcs@24 (aspeed,ast2500-kcs-bmc-v2): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml# ... arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: /ahb/apb/lpc@1e789000/lhc@a0: failed to match any schema with compatible: ['aspeed,ast2500-lhc'] arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: /ahb/apb/lpc@1e789000/ibt@140: failed to match any schema with compatible: ['aspeed,ast2500-ibt-bmc'] arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: /ahb/apb/bus@1e78a000/i2c@100/power-supply@3c: failed to match any schema with compatible: ['pmbus'] /home/bcran/src/linux/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dtb: gpio@1c (nxp,pca9557): '#address-cells', '#size-cells', 'gpio@0', 'gpio@1', 'gpio@2', 'gpio@3', 'gpio@4', 'gpio@5', 'gpio@6', 'gpio@7' do not match any of the regexes: '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$', '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/gpio/gpio-pca95xx.yaml# -- Rebecca Cran ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-12 23:37 ` Rebecca Cran @ 2025-09-15 4:51 ` Andrew Jeffery 0 siblings, 0 replies; 15+ messages in thread From: Andrew Jeffery @ 2025-09-15 4:51 UTC (permalink / raw) To: Rebecca Cran, Krzysztof Kozlowski, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel Hi Rebecca, On Fri, 2025-09-12 at 17:37 -0600, Rebecca Cran wrote: > On 9/11/25 00:29, Krzysztof Kozlowski wrote: > > Never tested. > > > > It does not look like you tested the DTS against bindings. Please run > > `make dtbs_check W=1` (see > > Documentation/devicetree/bindings/writing-schema.rst or > > https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ > > for instructions). > > > Am I doing something wrong, or are a certain number of validation issues > expected? I expect you're not doing anything wrong there. There are a number of historical warnings from the ASPEED DTSIs. However, generally, the policy is as documented here: https://docs.kernel.org/process/maintainer-soc.html#validating-devicetree-file > > For example, I'm seeing these - most of which are from aspeed-g5.dtsi, > not my dts file: > *snip* I'm okay with taking new ast2[456]00 devicetrees that don't introduce any new warnings of their own. However, given you're contributing a new devicetree, it would be super helpful if you could look at removing one or two of the warnings from the DTSI while you're at it, as this improves the utility of the checking tools for everyone. Cheers, Andrew ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-11 5:10 ` [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC Rebecca Cran 2025-09-11 6:29 ` Krzysztof Kozlowski @ 2025-09-11 14:09 ` Andrew Lunn 2025-09-16 0:26 ` Rebecca Cran 2025-09-15 5:02 ` Andrew Jeffery 2 siblings, 1 reply; 15+ messages in thread From: Andrew Lunn @ 2025-09-11 14:09 UTC (permalink / raw) To: Rebecca Cran Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel > +&mac0 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rmii1_default>; > + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, > + <&syscon ASPEED_CLK_MAC1RCLK>; > + clock-names = "MACCLK", "RCLK"; > + use-ncsi; > + > + nvmem-cells = <ð0_macaddress>; > + nvmem-cell-names = "mac-address"; > +}; There is no phy-handle here, and no mdio node in this file. What is the MAC connected to? Does it connect to the hosts Ethernet interface? > + > +&mac1 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; > + > + nvmem-cells = <ð1_macaddress>; > + nvmem-cell-names = "mac-address"; > +}; RGMII pinctrl is referenced here. This opens up the question about RGMII delays. What is this MAC connected to? Andrew ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-11 14:09 ` Andrew Lunn @ 2025-09-16 0:26 ` Rebecca Cran 2025-09-16 0:37 ` Andrew Lunn 0 siblings, 1 reply; 15+ messages in thread From: Rebecca Cran @ 2025-09-16 0:26 UTC (permalink / raw) To: Andrew Lunn Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On 9/11/25 08:09, Andrew Lunn wrote: > There is no phy-handle here, and no mdio node in this file. What is > the MAC connected to? Does it connect to the hosts Ethernet interface? Yes, it's connected to one of the host's 10Gb Ethernet interfaces. > RGMII pinctrl is referenced here. This opens up the question about > RGMII delays. What is this MAC connected to? It's the AST2500 MAC2, connected to the management LAN ethernet port. -- Rebecca Cran ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-16 0:26 ` Rebecca Cran @ 2025-09-16 0:37 ` Andrew Lunn 2025-09-16 18:40 ` Rebecca Cran 0 siblings, 1 reply; 15+ messages in thread From: Andrew Lunn @ 2025-09-16 0:37 UTC (permalink / raw) To: Rebecca Cran Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On Mon, Sep 15, 2025 at 06:26:04PM -0600, Rebecca Cran wrote: > On 9/11/25 08:09, Andrew Lunn wrote: > > There is no phy-handle here, and no mdio node in this file. What is > > the MAC connected to? Does it connect to the hosts Ethernet interface? > > Yes, it's connected to one of the host's 10Gb Ethernet interfaces. O.K. Maybe add a comment please. > > RGMII pinctrl is referenced here. This opens up the question about > > RGMII delays. What is this MAC connected to? > > It's the AST2500 MAC2, connected to the management LAN ethernet port. And does it have a PHY? On an MDIO bus? Unless i'm mistaken, you don't describe the PHY, a phy-handle pointing to the PHY, and don't have phy-mode = 'rgmii-id'. Andrew ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-16 0:37 ` Andrew Lunn @ 2025-09-16 18:40 ` Rebecca Cran 2025-09-16 19:07 ` Andrew Lunn 0 siblings, 1 reply; 15+ messages in thread From: Rebecca Cran @ 2025-09-16 18:40 UTC (permalink / raw) To: Andrew Lunn Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On 9/15/25 18:37, Andrew Lunn wrote: > And does it have a PHY? On an MDIO bus? Unless i'm mistaken, you don't > describe the PHY, a phy-handle pointing to the PHY, and don't have > phy-mode = 'rgmii-id'. I've been trying to figure this out. Yes, it's connected to a PHY (an RTL8211E). At the moment it's being detected by OpenBMC as: ftgmac100 1e680000.ethernet: Read MAC address 9c:6b:00:43:0b:bd from device tree RTL8211E Gigabit Ethernet 1e680000.ethernet--1:00: attached PHY driver (mii_bus:phy_addr=1e680000.ethernet--1:00, irq=POLL) ftgmac100 1e680000.ethernet eth1: irq 43, mapped at 7e548db4 ftgmac100 1e680000.ethernet eth1: Link is Up - 1Gbps/Full - flow control rx/tx aspeed-g5.dtsi has: mac1: ethernet@1e680000 { compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; reg = <0x1e680000 0x180>; interrupts = <3>; clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; status = "disabled"; }; It doesn't define a PHY, but I presume I can't define one without it conflicting with the definition of mac1. -- Rebecca Cran ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-16 18:40 ` Rebecca Cran @ 2025-09-16 19:07 ` Andrew Lunn 2025-09-16 21:22 ` Rebecca Cran 0 siblings, 1 reply; 15+ messages in thread From: Andrew Lunn @ 2025-09-16 19:07 UTC (permalink / raw) To: Rebecca Cran Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On Tue, Sep 16, 2025 at 12:40:15PM -0600, Rebecca Cran wrote: > On 9/15/25 18:37, Andrew Lunn wrote: > > > And does it have a PHY? On an MDIO bus? Unless i'm mistaken, you don't > > describe the PHY, a phy-handle pointing to the PHY, and don't have > > phy-mode = 'rgmii-id'. > > I've been trying to figure this out. Yes, it's connected to a PHY (an > RTL8211E). > > At the moment it's being detected by OpenBMC as: > > ftgmac100 1e680000.ethernet: Read MAC address 9c:6b:00:43:0b:bd from device > tree > RTL8211E Gigabit Ethernet 1e680000.ethernet--1:00: attached PHY driver So what is probably happening is that the ftgmac100 is creating an MDIO bus. It does not matter if there is no node for it, it still creates the bus, and the PHYs on the bus are found. You should be able to see this in /sys/class/mdio_bus/. Then, since there is no phy-handle, it uses phy_find_first() to find the first PHY on the bus, and binds to that. Now, it looks like all other aspeed-g5 boards also don't link to the PHY. But the driver does seem to support adding an 'mdio' node within the ethernet node, and listing the PHYs. Something like: mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@0 { reg = <0>; }; }; And then you can add a phy-handle to point to it. Then the question is, did Aspeed mess up the RGMII delays for g5? You can try phy-mode = 'rgmii-id' and see if it works. Andrew ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-16 19:07 ` Andrew Lunn @ 2025-09-16 21:22 ` Rebecca Cran 2025-09-16 22:05 ` Andrew Lunn 0 siblings, 1 reply; 15+ messages in thread From: Rebecca Cran @ 2025-09-16 21:22 UTC (permalink / raw) To: Andrew Lunn Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On 9/16/25 13:07, Andrew Lunn wrote: > Now, it looks like all other aspeed-g5 boards also don't link to the > PHY. But the driver does seem to support adding an 'mdio' node within > the ethernet node, and listing the PHYs. Something like: > > mdio { > #address-cells = <1>; > #size-cells = <0>; > > ethphy0: ethernet-phy@0 { > reg = <0>; > }; > }; > > And then you can add a phy-handle to point to it. > > Then the question is, did Aspeed mess up the RGMII delays for g5? You > can try phy-mode = 'rgmii-id' and see if it works. I can't get that to work, with either 'rgmii-id' or 'rgmii'. It says "Failed to connect to phy". -- Rebecca Cran ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-16 21:22 ` Rebecca Cran @ 2025-09-16 22:05 ` Andrew Lunn 0 siblings, 0 replies; 15+ messages in thread From: Andrew Lunn @ 2025-09-16 22:05 UTC (permalink / raw) To: Rebecca Cran Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On Tue, Sep 16, 2025 at 03:22:04PM -0600, Rebecca Cran wrote: > On 9/16/25 13:07, Andrew Lunn wrote: > > > Now, it looks like all other aspeed-g5 boards also don't link to the > > PHY. But the driver does seem to support adding an 'mdio' node within > > the ethernet node, and listing the PHYs. Something like: > > > > mdio { > > #address-cells = <1>; > > #size-cells = <0>; > > > > ethphy0: ethernet-phy@0 { > > reg = <0>; > > }; > > }; > > > > And then you can add a phy-handle to point to it. > > > > Then the question is, did Aspeed mess up the RGMII delays for g5? You > > can try phy-mode = 'rgmii-id' and see if it works. > > I can't get that to work, with either 'rgmii-id' or 'rgmii'. > > It says "Failed to connect to phy". That probably means i have the wrong reg value. Try 1, 2, ... 31. Or put a printk() in phy_find_first() to print the value of addr. Andrew ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC 2025-09-11 5:10 ` [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC Rebecca Cran 2025-09-11 6:29 ` Krzysztof Kozlowski 2025-09-11 14:09 ` Andrew Lunn @ 2025-09-15 5:02 ` Andrew Jeffery 2 siblings, 0 replies; 15+ messages in thread From: Andrew Jeffery @ 2025-09-15 5:02 UTC (permalink / raw) To: Rebecca Cran, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel On Wed, 2025-09-10 at 23:10 -0600, Rebecca Cran wrote: > The ALTRAD8 BMC is an Aspeed AST2500-based BMC for the ASRock Rack > ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q boards. > > Signed-off-by: Rebecca Cran <rebecca@bsdio.com> > --- > arch/arm/boot/dts/aspeed/Makefile | 1 + > arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts | 647 > ++++++++++++++++++++ > 2 files changed, 648 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed/Makefile > b/arch/arm/boot/dts/aspeed/Makefile > index aba7451ab749..6bffb7130839 100644 > --- a/arch/arm/boot/dts/aspeed/Makefile > +++ b/arch/arm/boot/dts/aspeed/Makefile > @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ > aspeed-bmc-ampere-mtjefferson.dtb \ > aspeed-bmc-ampere-mtmitchell.dtb \ > aspeed-bmc-arm-stardragon4800-rep2.dtb \ > + aspeed-bmc-asrock-altrad8.dtb \ > aspeed-bmc-asrock-e3c246d4i.dtb \ > aspeed-bmc-asrock-e3c256d4i.dtb \ > aspeed-bmc-asrock-romed8hm3.dtb \ > diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts > b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts > new file mode 100644 > index 000000000000..61f6cf8018c0 > --- /dev/null > +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts > @@ -0,0 +1,647 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/dts-v1/; > +#include "aspeed-g5.dtsi" > +#include <dt-bindings/gpio/aspeed-gpio.h> > +#include <dt-bindings/leds/common.h> > +#include <dt-bindings/i2c/i2c.h> > + > +/ { > + model = "ASRock ALTRAD8 BMC"; > + compatible = "asrock,altrad8-bmc", "aspeed,ast2500"; > + *snip* > +}; > + > +&uart1 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_txd1_default > + &pinctrl_rxd1_default > + &pinctrl_ncts1_default > + &pinctrl_nrts1_default>; > +}; > + > +&uart2 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_txd2_default > + &pinctrl_rxd2_default>; > +}; > + > +&uart3 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_txd3_default > + &pinctrl_rxd3_default>; > +}; > + > +&uart4 { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_txd4_default > + &pinctrl_rxd4_default>; > +}; > + > +/* The BMC's uart */ > +&uart5 { > + status = "okay"; > +}; > + > +&mac0 { Recently I've decided that I'd like the "usual" node references here in the DTS to be ordered alphabetically. The style guide gives us two ordering options, either by ascending unit address or alphabetically: https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes Without the unit address being visible it's hard to verify the former, hence the preference for the latter. Can you please sort these accordingly? > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rmii1_default>; > + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, > + <&syscon ASPEED_CLK_MAC1RCLK>; > + clock-names = "MACCLK", "RCLK"; > + use-ncsi; > + > + nvmem-cells = <ð0_macaddress>; > + nvmem-cell-names = "mac-address"; > +}; > *snip* > + > +&i2c3 { > + status = "okay"; > + > + power-supply@3c { > + compatible = "pmbus"; Devicetrees describe the hardware and not abstract protocols like PMBus, so the compatible string must refer to a specific manufacturer,model here. Cheers, Andrew ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2025-09-16 23:03 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-09-11 5:10 [PATCH 0/2] Add device tree for ASRock Rack ALTRAD8 BMC Rebecca Cran 2025-09-11 5:10 ` [PATCH 1/2] dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board Rebecca Cran 2025-09-11 6:29 ` Krzysztof Kozlowski 2025-09-11 5:10 ` [PATCH 2/2] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC Rebecca Cran 2025-09-11 6:29 ` Krzysztof Kozlowski 2025-09-12 23:37 ` Rebecca Cran 2025-09-15 4:51 ` Andrew Jeffery 2025-09-11 14:09 ` Andrew Lunn 2025-09-16 0:26 ` Rebecca Cran 2025-09-16 0:37 ` Andrew Lunn 2025-09-16 18:40 ` Rebecca Cran 2025-09-16 19:07 ` Andrew Lunn 2025-09-16 21:22 ` Rebecca Cran 2025-09-16 22:05 ` Andrew Lunn 2025-09-15 5:02 ` Andrew Jeffery
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