[PATCH 0/5] r8a7795: add clocks for the watchdogs

[PATCH 0/5] r8a7795: add clocks for the watchdogs

[Wolfram Sang]

Okay, here is the updated series. Rebased to latest renesas-drivers
(renesas-drivers-2016-03-15-v4.5) and actually tested with both parent clocks
for R. Works fine.

All FIXMEs and comments from Geert (Thanks!) have been addressed, I hope. It
can go in, I'd think.

I have still the open question if we can set a register in secure-mode somehow,
so I can test the SWDT which is based on OSCCLK?

Regards,

   Wolfram

Wolfram Sang (5):
  clk: shmobile: cpg-mssr: add generic support for read-only DIV6 clocks
  clk: shmobile: r8a7795: add OSC and RINT clocks
  clk: shmobile: r8a7795: add R clk
  clk: shmobile: r8a7795: add stop for R clk
  arm64: dts: salvator-x: populate EXTALR

 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts |  4 ++++
 drivers/clk/renesas/r8a7795-cpg-mssr.c             | 27 ++++++++++++++++++----
 drivers/clk/renesas/renesas-cpg-mssr.c             | 18 ++++++++++-----
 drivers/clk/renesas/renesas-cpg-mssr.h             |  3 +++
 include/dt-bindings/clock/r8a7795-cpg-mssr.h       |  2 ++
 5 files changed, 44 insertions(+), 10 deletions(-)

-- 
2.7.0

[PATCH 1/5] clk: shmobile: cpg-mssr: add generic support for read-only DIV6 clocks

[Wolfram Sang]

From: Wolfram Sang <wsa+renesas@sang-engineering.com>

Gen3 has two clocks (OSC and R) which look like a DIV6 clock but their
divider value is read-only and depends on MD pins at bootup. Add support
for such clocks by reading the value and adding a fixed clock.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

Since RFC, only rebased.

 drivers/clk/renesas/renesas-cpg-mssr.c | 18 ++++++++++++------
 drivers/clk/renesas/renesas-cpg-mssr.h |  3 +++
 2 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index dfdeb7d9f60201..6f7f3f65d7ecea 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -254,7 +254,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
 {
 	struct clk *clk = NULL, *parent;
 	struct device *dev = priv->dev;
-	unsigned int id = core->id;
+	unsigned int id = core->id, div = core->div;
 	const char *parent_name;
 
 	WARN_DEBUG(id >= priv->num_core_clks);
@@ -267,6 +267,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
 
 	case CLK_TYPE_FF:
 	case CLK_TYPE_DIV6P1:
+	case CLK_TYPE_DIV6_RO:
 		WARN_DEBUG(core->parent >= priv->num_core_clks);
 		parent = priv->clks[core->parent];
 		if (IS_ERR(parent)) {
@@ -275,13 +276,18 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
 		}
 
 		parent_name = __clk_get_name(parent);
-		if (core->type == CLK_TYPE_FF) {
-			clk = clk_register_fixed_factor(NULL, core->name,
-							parent_name, 0,
-							core->mult, core->div);
-		} else {
+
+		if (core->type == CLK_TYPE_DIV6_RO)
+			/* Multiply with the DIV6 register value */
+			div *= (readl(priv->base + core->offset) & 0x3f) + 1;
+
+		if (core->type == CLK_TYPE_DIV6P1) {
 			clk = cpg_div6_register(core->name, 1, &parent_name,
 						priv->base + core->offset);
+		} else {
+			clk = clk_register_fixed_factor(NULL, core->name,
+							parent_name, 0,
+							core->mult, div);
 		}
 		break;
 
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index cad3c7d1b0c6f0..0d1e3e811e79bf 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -37,6 +37,7 @@ enum clk_types {
 	CLK_TYPE_IN,		/* External Clock Input */
 	CLK_TYPE_FF,		/* Fixed Factor Clock */
 	CLK_TYPE_DIV6P1,	/* DIV6 Clock with 1 parent clock */
+	CLK_TYPE_DIV6_RO,	/* DIV6 Clock read only with extra divisor */
 
 	/* Custom definitions start here */
 	CLK_TYPE_CUSTOM,
@@ -53,6 +54,8 @@ enum clk_types {
 	DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
 #define DEF_DIV6P1(_name, _id, _parent, _offset)	\
 	DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
+#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div)	\
+	DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
 
     /*
      * Definitions of Module Clocks
-- 
2.7.0

[PATCH 2/5] clk: shmobile: r8a7795: add OSC and RINT clocks

[Wolfram Sang]

From: Wolfram Sang <wsa+renesas@sang-engineering.com>

And put LAST_DT_CORE_CLK to a place where it won't be missed on updates.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

Since RFC, moved CLK_RINT to the end and reworked LAST_DT_CORE_CLK

 drivers/clk/renesas/r8a7795-cpg-mssr.c       | 8 ++++----
 include/dt-bindings/clock/r8a7795-cpg-mssr.h | 2 ++
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index a9f933055663cb..d305bcd3ef6619 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -28,11 +28,8 @@
 
 
 enum clk_ids {
-	/* Core Clock Outputs exported to DT */
-	LAST_DT_CORE_CLK = R8A7795_CLK_OSC,
-
 	/* External Input Clocks */
-	CLK_EXTAL,
+	CLK_EXTAL = LAST_DT_CORE_CLK + 1,
 	CLK_EXTALR,
 
 	/* Internal Core Clocks */
@@ -116,6 +113,9 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
 	DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
 	DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),
 	DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
+
+	DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, 0x0240, 8),
+	DEF_DIV6_RO("r_int",    R8A7795_CLK_RINT,  CLK_EXTAL, 0x0240, 32),
 };
 
 static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
index e864aae0a2561c..274c2728e6dff5 100644
--- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
@@ -59,5 +59,7 @@
 #define R8A7795_CLK_CPEX		44
 #define R8A7795_CLK_R			45
 #define R8A7795_CLK_OSC			46
+#define R8A7795_CLK_RINT		47
+#define LAST_DT_CORE_CLK		R8A7795_CLK_RINT
 
 #endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
-- 
2.7.0

[PATCH 3/5] clk: shmobile: r8a7795: add R clk

[Wolfram Sang]

From: Wolfram Sang <wsa+renesas@sang-engineering.com>

R can select between two parents. We deal with it like this: During
initialization, check if EXTALR is populated. If so, use it for R. If
not, use R_Internal. clk_mux doesn't help here because we don't want to
switch parents depending on the clock rate. The clock rate (and source)
should stay constant for the watchdog, so I think a setup like this
during initialization makes sense.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

Since RFC, remove FIXME by using clk_get_rate() via clk.h

 drivers/clk/renesas/r8a7795-cpg-mssr.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index d305bcd3ef6619..c260da5e70e116 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -13,6 +13,7 @@
  */
 
 #include <linux/bug.h>
+#include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/device.h>
 #include <linux/err.h>
@@ -26,6 +27,7 @@
 
 #include "renesas-cpg-mssr.h"
 
+#define CPG_RCKCR	0x240
 
 enum clk_ids {
 	/* External Input Clocks */
@@ -60,6 +62,7 @@ enum r8a7795_clk_types {
 	CLK_TYPE_GEN3_PLL3,
 	CLK_TYPE_GEN3_PLL4,
 	CLK_TYPE_GEN3_SD,
+	CLK_TYPE_GEN3_R,
 };
 
 #define DEF_GEN3_SD(_name, _id, _parent, _offset)	\
@@ -114,8 +117,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
 	DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),
 	DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
 
-	DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, 0x0240, 8),
-	DEF_DIV6_RO("r_int",    R8A7795_CLK_RINT,  CLK_EXTAL, 0x0240, 32),
+	DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, CPG_RCKCR, 8),
+	DEF_DIV6_RO("r_int",    R8A7795_CLK_RINT,  CLK_EXTAL, CPG_RCKCR, 32),
+
+	/* must come after EXTALR because we need its rate */
+	DEF_BASE("r",           R8A7795_CLK_R, CLK_TYPE_GEN3_R, R8A7795_CLK_RINT),
 };
 
 static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
@@ -581,6 +587,18 @@ struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
 	case CLK_TYPE_GEN3_SD:
 		return cpg_sd_clk_register(core, base, __clk_get_name(parent));
 
+	case CLK_TYPE_GEN3_R:
+		/* RINT is default. Only if EXTALR is populated, we switch to it */
+		value = readl(base + CPG_RCKCR) & 0x3f;
+
+		if (clk_get_rate(clks[CLK_EXTALR])) {
+			parent = clks[CLK_EXTALR];
+			value |= BIT(15);
+		}
+
+		writel(value, base + CPG_RCKCR);
+		break;
+
 	default:
 		return ERR_PTR(-EINVAL);
 	}
-- 
2.7.0

[PATCH 4/5] clk: shmobile: r8a7795: add stop for R clk

[Wolfram Sang]

From: Wolfram Sang <wsa+renesas@sang-engineering.com>

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
---

Since RFC, rebased and added ack.

 drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index c260da5e70e116..22ba841d7f88b8 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -148,6 +148,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
 	DEF_MOD("usb3-if0",		 328,	R8A7795_CLK_S3D1),
 	DEF_MOD("usb-dmac0",		 330,	R8A7795_CLK_S3D1),
 	DEF_MOD("usb-dmac1",		 331,	R8A7795_CLK_S3D1),
+	DEF_MOD("rwdt0",		 402,	R8A7795_CLK_R),
 	DEF_MOD("intc-ex",		 407,	R8A7795_CLK_CP),
 	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S3D1),
 	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S3D4),
-- 
2.7.0

[PATCH 5/5] arm64: dts: salvator-x: populate EXTALR

[Wolfram Sang]

From: Wolfram Sang <wsa+renesas@sang-engineering.com>

It can be used for the watchdog.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

New patch.

 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 7d278ac04e4fa5..342f26bd0924f3 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -185,6 +185,10 @@
 	clock-frequency = <16666666>;
 };
 
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
 &pfc {
 	pinctrl-0 = <&scif_clk_pins>;
 	pinctrl-names = "default";
-- 
2.7.0

Re: [PATCH 1/5] clk: shmobile: cpg-mssr: add generic support for read-only DIV6 clocks

[Geert Uytterhoeven]

On Thu, Mar 24, 2016 at 2:00 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
> Gen3 has two clocks (OSC and R) which look like a DIV6 clock but their
> divider value is read-only and depends on MD pins at bootup. Add support
> for such clocks by reading the value and adding a fixed clock.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>


-- 
Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 5/5] arm64: dts: salvator-x: populate EXTALR

[Geert Uytterhoeven]

On Thu, Mar 24, 2016 at 2:00 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
> It can be used for the watchdog.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/5] clk: shmobile: r8a7795: add OSC and RINT clocks

[Geert Uytterhoeven]

Hi Wolfram,

On Thu, Mar 24, 2016 at 2:00 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
> And put LAST_DT_CORE_CLK to a place where it won't be missed on updates.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>
> Since RFC, moved CLK_RINT to the end and reworked LAST_DT_CORE_CLK

Ugh... (see below)

>  drivers/clk/renesas/r8a7795-cpg-mssr.c       | 8 ++++----
>  include/dt-bindings/clock/r8a7795-cpg-mssr.h | 2 ++
>  2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> index a9f933055663cb..d305bcd3ef6619 100644
> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> @@ -28,11 +28,8 @@
>
>
>  enum clk_ids {
> -       /* Core Clock Outputs exported to DT */
> -       LAST_DT_CORE_CLK = R8A7795_CLK_OSC,
> -
>         /* External Input Clocks */
> -       CLK_EXTAL,
> +       CLK_EXTAL = LAST_DT_CORE_CLK + 1,
>         CLK_EXTALR,
>
>         /* Internal Core Clocks */
> @@ -116,6 +113,9 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
>         DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
>         DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),
>         DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
> +
> +       DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, 0x0240, 8),
> +       DEF_DIV6_RO("r_int",    R8A7795_CLK_RINT,  CLK_EXTAL, 0x0240, 32),
>  };
>
>  static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
> diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
> index e864aae0a2561c..274c2728e6dff5 100644
> --- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h
> +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
> @@ -59,5 +59,7 @@
>  #define R8A7795_CLK_CPEX               44
>  #define R8A7795_CLK_R                  45
>  #define R8A7795_CLK_OSC                        46
> +#define R8A7795_CLK_RINT               47
> +#define LAST_DT_CORE_CLK               R8A7795_CLK_RINT

LAST_DT_CORE_CLK is not part of the DT bindings, but part of the internal
driver implementation. Please don't move it.

Furthermore, why do you export R8A7795_CLK_RINT?
it's nowhere referenced from DT.

I think it belongs under "Internal Core Clocks" in r8a7795-cpg-mssr.c.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/5] clk: shmobile: r8a7795: add R clk

[Geert Uytterhoeven]

Hi Wolfram,

On Thu, Mar 24, 2016 at 2:00 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
> R can select between two parents. We deal with it like this: During
> initialization, check if EXTALR is populated. If so, use it for R. If
> not, use R_Internal. clk_mux doesn't help here because we don't want to
> switch parents depending on the clock rate. The clock rate (and source)
> should stay constant for the watchdog, so I think a setup like this
> during initialization makes sense.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>
> Since RFC, remove FIXME by using clk_get_rate() via clk.h
>
>  drivers/clk/renesas/r8a7795-cpg-mssr.c | 22 ++++++++++++++++++++--
>  1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
> index d305bcd3ef6619..c260da5e70e116 100644
> --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c

> @@ -114,8 +117,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
>         DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),
>         DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
>
> -       DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, 0x0240, 8),
> -       DEF_DIV6_RO("r_int",    R8A7795_CLK_RINT,  CLK_EXTAL, 0x0240, 32),
> +       DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, CPG_RCKCR, 8),
> +       DEF_DIV6_RO("r_int",    R8A7795_CLK_RINT,  CLK_EXTAL, CPG_RCKCR, 32),
> +
> +       /* must come after EXTALR because we need its rate */

must come after r_int because we need that clock as a possible parent?

> +       DEF_BASE("r",           R8A7795_CLK_R, CLK_TYPE_GEN3_R, R8A7795_CLK_RINT),
>  };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/5] clk: shmobile: r8a7795: add OSC and RINT clocks

[Wolfram Sang]

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> Furthermore, why do you export R8A7795_CLK_RINT?
> it's nowhere referenced from DT.
> 
> I think it belongs under "Internal Core Clocks" in r8a7795-cpg-mssr.c.

Ok, did this. I thought it was the same "class" as OSC, but I agree to
your view.


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Re: [PATCH 3/5] clk: shmobile: r8a7795: add R clk

[Wolfram Sang]

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> > @@ -114,8 +117,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
> >         DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),
> >         DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
> >
> > -       DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, 0x0240, 8),
> > -       DEF_DIV6_RO("r_int",    R8A7795_CLK_RINT,  CLK_EXTAL, 0x0240, 32),
> > +       DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, CPG_RCKCR, 8),
> > +       DEF_DIV6_RO("r_int",    R8A7795_CLK_RINT,  CLK_EXTAL, CPG_RCKCR, 32),
> > +
> > +       /* must come after EXTALR because we need its rate */
> 
> must come after r_int because we need that clock as a possible parent?

Well, I added the comment because the dependency to EXTALR is not
obvious. Unlike the dependency to RINT which is described in the same
manner as the rest of the clocks.

Maybe I should simply remove the comment if it creates only confusion?


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Re: [PATCH 3/5] clk: shmobile: r8a7795: add R clk

[Geert Uytterhoeven]

Hi Wolfram,

On Tue, Mar 29, 2016 at 5:54 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
>> > @@ -114,8 +117,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
>> >         DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),
>> >         DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
>> >
>> > -       DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, 0x0240, 8),
>> > -       DEF_DIV6_RO("r_int",    R8A7795_CLK_RINT,  CLK_EXTAL, 0x0240, 32),
>> > +       DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, CPG_RCKCR, 8),
>> > +       DEF_DIV6_RO("r_int",    R8A7795_CLK_RINT,  CLK_EXTAL, CPG_RCKCR, 32),
>> > +
>> > +       /* must come after EXTALR because we need its rate */
>>
>> must come after r_int because we need that clock as a possible parent?
>
> Well, I added the comment because the dependency to EXTALR is not
> obvious. Unlike the dependency to RINT which is described in the same
> manner as the rest of the clocks.
>
> Maybe I should simply remove the comment if it creates only confusion?

That's indeed a viable option...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds