From: Doug Brown <doug@schmorgal.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
Doug Brown <doug@schmorgal.com>
Subject: [PATCH 01/12] clk: mmp: pxa168: add additional register defines
Date: Sun, 12 Jun 2022 12:29:26 -0700 [thread overview]
Message-ID: <20220612192937.162952-2-doug@schmorgal.com> (raw)
In-Reply-To: <20220612192937.162952-1-doug@schmorgal.com>
In preparation for adding additional peripherals over time, this commit
adds a bunch of extra APBC_* defines based on information from the
datasheet. It also reorganizes the list of defines to be ordered
sequentially by address (grouped by type).
Signed-off-by: Doug Brown <doug@schmorgal.com>
---
drivers/clk/mmp/clk-of-pxa168.c | 31 ++++++++++++++++++++++++-------
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c
index f110c02e83cb..c975a45f9bb6 100644
--- a/drivers/clk/mmp/clk-of-pxa168.c
+++ b/drivers/clk/mmp/clk-of-pxa168.c
@@ -22,9 +22,6 @@
#include "clk.h"
#include "reset.h"
-#define APBC_RTC 0x28
-#define APBC_TWSI0 0x2c
-#define APBC_KPC 0x30
#define APBC_UART0 0x0
#define APBC_UART1 0x4
#define APBC_GPIO 0x8
@@ -32,20 +29,40 @@
#define APBC_PWM1 0x10
#define APBC_PWM2 0x14
#define APBC_PWM3 0x18
+#define APBC_RTC 0x28
+#define APBC_TWSI0 0x2c
+#define APBC_KPC 0x30
#define APBC_TIMER 0x34
+#define APBC_AIB 0x3c
+#define APBC_SW_JTAG 0x40
+#define APBC_ONEWIRE 0x48
+#define APBC_TWSI1 0x6c
+#define APBC_UART2 0x70
+#define APBC_AC97 0x84
#define APBC_SSP0 0x81c
#define APBC_SSP1 0x820
#define APBC_SSP2 0x84c
#define APBC_SSP3 0x858
#define APBC_SSP4 0x85c
-#define APBC_TWSI1 0x6c
-#define APBC_UART2 0x70
+#define APMU_DISP0 0x4c
+#define APMU_CCIC0 0x50
#define APMU_SDH0 0x54
#define APMU_SDH1 0x58
#define APMU_USB 0x5c
-#define APMU_DISP0 0x4c
-#define APMU_CCIC0 0x50
#define APMU_DFC 0x60
+#define APMU_DMA 0x64
+#define APMU_BUS 0x6c
+#define APMU_GC 0xcc
+#define APMU_SMC 0xd4
+#define APMU_XD 0xdc
+#define APMU_SDH2 0xe0
+#define APMU_SDH3 0xe4
+#define APMU_CF 0xf0
+#define APMU_MSP 0xf4
+#define APMU_CMU 0xf8
+#define APMU_FE 0xfc
+#define APMU_PCIE 0x100
+#define APMU_EPD 0x104
#define MPMU_UART_PLL 0x14
struct pxa168_clk_unit {
--
2.25.1
next prev parent reply other threads:[~2022-06-12 19:31 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-12 19:29 [PATCH 00/12] PXA168 clock fixes Doug Brown
2022-06-12 19:29 ` Doug Brown [this message]
2022-09-30 20:43 ` [PATCH 01/12] clk: mmp: pxa168: add additional register defines Stephen Boyd
2022-06-12 19:29 ` [PATCH 02/12] clk: mmp: pxa168: fix incorrect dividers Doug Brown
2022-09-30 20:43 ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 03/12] dt-bindings: marvell,pxa168: add clock ids for additional dividers Doug Brown
2022-06-16 17:48 ` Rob Herring
2022-09-30 20:43 ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 04/12] clk: mmp: pxa168: add new clocks for peripherals Doug Brown
2022-09-30 20:43 ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 05/12] clk: mmp: pxa168: fix const-correctness Doug Brown
2022-09-30 20:44 ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 06/12] clk: mmp: pxa168: fix incorrect parent clocks Doug Brown
2022-09-30 20:44 ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 07/12] clk: mmp: pxa168: add muxes for more peripherals Doug Brown
2022-09-30 20:44 ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 08/12] clk: mmp: pxa168: fix GPIO clock enable bits Doug Brown
2022-09-30 20:44 ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 09/12] dt-bindings: marvell,pxa168: add clock id for SDH3 Doug Brown
2022-06-16 17:48 ` Rob Herring
2022-09-30 20:44 ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 10/12] clk: mmp: pxa168: add clocks for SDH2 and SDH3 Doug Brown
2022-09-30 20:44 ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 11/12] dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks Doug Brown
2022-06-16 17:49 ` Rob Herring
2022-09-30 20:45 ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 12/12] clk: mmp: pxa168: control shared SDH bits with separate clock Doug Brown
2022-09-30 20:45 ` Stephen Boyd
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