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From: Doug Brown <doug@schmorgal.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	Doug Brown <doug@schmorgal.com>
Subject: [PATCH 04/12] clk: mmp: pxa168: add new clocks for peripherals
Date: Sun, 12 Jun 2022 12:29:29 -0700	[thread overview]
Message-ID: <20220612192937.162952-5-doug@schmorgal.com> (raw)
In-Reply-To: <20220612192937.162952-1-doug@schmorgal.com>

This commit adds three new clocks that previously didn't exist, but are
needed in order to match the clock parenting as described in the PXA168
datasheet.

Signed-off-by: Doug Brown <doug@schmorgal.com>
---
 drivers/clk/mmp/clk-of-pxa168.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c
index 42569cf3f42f..aba58ce6e60c 100644
--- a/drivers/clk/mmp/clk-of-pxa168.c
+++ b/drivers/clk/mmp/clk-of-pxa168.c
@@ -94,6 +94,9 @@ static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
 	{PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 1, 5, 0},
 	{PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 1, 5, 0},
 	{PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
+	{PXA168_CLK_PLL1_2_1_10, "pll1_2_1_10", "pll1_2", 1, 10, 0},
+	{PXA168_CLK_PLL1_2_3_16, "pll1_2_3_16", "pll1_2", 3, 16, 0},
+	{PXA168_CLK_CLK32_2, "clk32_2", "clk32", 1, 2, 0},
 };
 
 static struct mmp_clk_factor_masks uart_factor_masks = {
-- 
2.25.1


  parent reply	other threads:[~2022-06-12 19:30 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-12 19:29 [PATCH 00/12] PXA168 clock fixes Doug Brown
2022-06-12 19:29 ` [PATCH 01/12] clk: mmp: pxa168: add additional register defines Doug Brown
2022-09-30 20:43   ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 02/12] clk: mmp: pxa168: fix incorrect dividers Doug Brown
2022-09-30 20:43   ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 03/12] dt-bindings: marvell,pxa168: add clock ids for additional dividers Doug Brown
2022-06-16 17:48   ` Rob Herring
2022-09-30 20:43   ` Stephen Boyd
2022-06-12 19:29 ` Doug Brown [this message]
2022-09-30 20:43   ` [PATCH 04/12] clk: mmp: pxa168: add new clocks for peripherals Stephen Boyd
2022-06-12 19:29 ` [PATCH 05/12] clk: mmp: pxa168: fix const-correctness Doug Brown
2022-09-30 20:44   ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 06/12] clk: mmp: pxa168: fix incorrect parent clocks Doug Brown
2022-09-30 20:44   ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 07/12] clk: mmp: pxa168: add muxes for more peripherals Doug Brown
2022-09-30 20:44   ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 08/12] clk: mmp: pxa168: fix GPIO clock enable bits Doug Brown
2022-09-30 20:44   ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 09/12] dt-bindings: marvell,pxa168: add clock id for SDH3 Doug Brown
2022-06-16 17:48   ` Rob Herring
2022-09-30 20:44   ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 10/12] clk: mmp: pxa168: add clocks for SDH2 and SDH3 Doug Brown
2022-09-30 20:44   ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 11/12] dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks Doug Brown
2022-06-16 17:49   ` Rob Herring
2022-09-30 20:45   ` Stephen Boyd
2022-06-12 19:29 ` [PATCH 12/12] clk: mmp: pxa168: control shared SDH bits with separate clock Doug Brown
2022-09-30 20:45   ` Stephen Boyd

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