[PATCH mainline-linux 0/3] Remove WDT{0,2,3} support from RZ/V2H(P)

[PATCH mainline-linux 0/3] Remove WDT{0,2,3} support from RZ/V2H(P)

[Fabrizio Castro]

Dear All,

The HW user manual states that the CA55 cores from the Renesas RZ/V2H(P)
SoC are only allowed access to WDT1, however when WDT support was added
it included all the WDT IPs (WDT0, WDT1, WDT2, and WDT3).

Address this by removing the device tree nodes and clock/reset entries
for WDT{0,2,3}.

Cheers,
Fab

Fabrizio Castro (3):
  dt-bindings: watchdog: renesas,r9a09g057-wdt: Rework example
  arm64: dts: renesas: r9a09g057: Remove wdt{0,2,3} nodes
  clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}

 .../watchdog/renesas,r9a09g057-wdt.yaml       |  8 ++---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    | 30 -------------------
 drivers/clk/renesas/r9a09g057-cpg.c           | 15 ----------
 3 files changed, 4 insertions(+), 49 deletions(-)

-- 
2.34.1

[PATCH mainline-linux 1/3] dt-bindings: watchdog: renesas,r9a09g057-wdt: Rework example

[Fabrizio Castro]

When the bindings for the Renesas RZ/V2H(P) SoC were factored
out IP WDT0 was selected for the example, however the HW user
manual states that only IP WDT1 can be used by Linux.

This commit is part of a series that removes WDT{0,2,3} support
from the kernel, therefore the example from the bindings has
lost its meaning.

Update the example accordingly.

Fixes: fcba2855251f ("dt-bindings: watchdog: factor out RZ/V2H(P) watchdog")
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 .../bindings/watchdog/renesas,r9a09g057-wdt.yaml          | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
index 099200c4f136..975c5aa4d747 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
@@ -89,11 +89,11 @@ examples:
   - |
     #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
 
-    watchdog@11c00400 {
+    watchdog@14400000 {
             compatible = "renesas,r9a09g057-wdt";
-            reg = <0x11c00400 0x400>;
-            clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
+            reg = <0x14400000 0x400>;
+            clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
             clock-names = "pclk", "oscclk";
-            resets = <&cpg 0x75>;
+            resets = <&cpg 0x76>;
             power-domains = <&cpg>;
     };
-- 
2.34.1

[PATCH mainline-linux 2/3] arm64: dts: renesas: r9a09g057: Remove wdt{0,2,3} nodes

[Fabrizio Castro]

The HW user manual for the Renesas RZ/V2H(P) SoC (a.k.a r9a09g057)
states that only WDT1 is supposed to be accessed by the CA55 cores.
WDT0 is supposed to be used by the CM33 core, WDT2 is supposed
to be used by the CR8 core 0, and WDT3 is supposed to be used
by the CR8 core 1.

Remove wdt{0,2,3} from the SoC specific device tree to make it
compliant with the specification from the HW manual.

This change is harmless as there are currently no users of the
wdt{0,2,3} device tree nodes, only the wdt1 node is actually used.

Fixes: 095105496e7d ("arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes")
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 30 ----------------------
 1 file changed, 30 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 80cba9fcfe7b..504c28386622 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -581,16 +581,6 @@ ostm7: timer@12c03000 {
 			status = "disabled";
 		};
 
-		wdt0: watchdog@11c00400 {
-			compatible = "renesas,r9a09g057-wdt";
-			reg = <0 0x11c00400 0 0x400>;
-			clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
-			clock-names = "pclk", "oscclk";
-			resets = <&cpg 0x75>;
-			power-domains = <&cpg>;
-			status = "disabled";
-		};
-
 		wdt1: watchdog@14400000 {
 			compatible = "renesas,r9a09g057-wdt";
 			reg = <0 0x14400000 0 0x400>;
@@ -601,26 +591,6 @@ wdt1: watchdog@14400000 {
 			status = "disabled";
 		};
 
-		wdt2: watchdog@13000000 {
-			compatible = "renesas,r9a09g057-wdt";
-			reg = <0 0x13000000 0 0x400>;
-			clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
-			clock-names = "pclk", "oscclk";
-			resets = <&cpg 0x77>;
-			power-domains = <&cpg>;
-			status = "disabled";
-		};
-
-		wdt3: watchdog@13000400 {
-			compatible = "renesas,r9a09g057-wdt";
-			reg = <0 0x13000400 0 0x400>;
-			clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
-			clock-names = "pclk", "oscclk";
-			resets = <&cpg 0x78>;
-			power-domains = <&cpg>;
-			status = "disabled";
-		};
-
 		rtc: rtc@11c00800 {
 			compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";
 			reg = <0 0x11c00800 0 0x400>;
-- 
2.34.1

[PATCH mainline-linux 3/3] clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}

[Fabrizio Castro]

The HW user manual for the Renesas RZ/V2H(P) SoC specifies
that only the WDT1 IP is supposed to be used by Linux,
while the WDT{0,2,3} IPs are supposed to be used by the CM33
and CR8 cores.

Remove the clock and reset entries for WDT{0,2,3} to prevent
interfering with the CM33 and CR8 cores.

This change is harmless as only WDT1 is used by Linux, there
are no users for the WDT{0,2,3} cores.

Fixes: 3aeccbe08171 ("clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT")
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
 drivers/clk/renesas/r9a09g057-cpg.c | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 6943cad318b5..07803e0c91de 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -280,22 +280,10 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
 						BUS_MSTOP(11, BIT(15))),
 	DEF_MOD("gtm_7_pclk",			CLK_PLLCLN_DIV16, 4, 10, 2, 10,
 						BUS_MSTOP(12, BIT(0))),
-	DEF_MOD("wdt_0_clkp",			CLK_PLLCM33_DIV16, 4, 11, 2, 11,
-						BUS_MSTOP(3, BIT(10))),
-	DEF_MOD("wdt_0_clk_loco",		CLK_QEXTAL, 4, 12, 2, 12,
-						BUS_MSTOP(3, BIT(10))),
 	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,
 						BUS_MSTOP(1, BIT(0))),
 	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14,
 						BUS_MSTOP(1, BIT(0))),
-	DEF_MOD("wdt_2_clkp",			CLK_PLLCLN_DIV16, 4, 15, 2, 15,
-						BUS_MSTOP(5, BIT(12))),
-	DEF_MOD("wdt_2_clk_loco",		CLK_QEXTAL, 5, 0, 2, 16,
-						BUS_MSTOP(5, BIT(12))),
-	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17,
-						BUS_MSTOP(5, BIT(13))),
-	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,
-						BUS_MSTOP(5, BIT(13))),
 	DEF_MOD("rsci0_pclk",			CLK_PLLCLN_DIV16, 5, 13, 2, 29,
 						BUS_MSTOP(11, BIT(3))),
 	DEF_MOD("rsci0_tclk",			CLK_PLLCLN_DIV16, 5, 14, 2, 30,
@@ -598,10 +586,7 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
 	DEF_RST(7, 2, 3, 3),		/* GTM_5_PRESETZ */
 	DEF_RST(7, 3, 3, 4),		/* GTM_6_PRESETZ */
 	DEF_RST(7, 4, 3, 5),		/* GTM_7_PRESETZ */
-	DEF_RST(7, 5, 3, 6),		/* WDT_0_RESET */
 	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
-	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
-	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
 	DEF_RST(8, 1, 3, 18),		/* RSCI0_PRESETN */
 	DEF_RST(8, 2, 3, 19),		/* RSCI0_TRESETN */
 	DEF_RST(8, 3, 3, 20),		/* RSCI1_PRESETN */
-- 
2.34.1

Re: [PATCH mainline-linux 1/3] dt-bindings: watchdog: renesas,r9a09g057-wdt: Rework example

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1807 bytes --]

On Thu, Jan 29, 2026 at 02:07:29PM +0000, Fabrizio Castro wrote:
> When the bindings for the Renesas RZ/V2H(P) SoC were factored
> out IP WDT0 was selected for the example, however the HW user
> manual states that only IP WDT1 can be used by Linux.
> 
> This commit is part of a series that removes WDT{0,2,3} support
> from the kernel, therefore the example from the bindings has
> lost its meaning.
> 
> Update the example accordingly.
> 
> Fixes: fcba2855251f ("dt-bindings: watchdog: factor out RZ/V2H(P) watchdog")

Given this is an example, I don't think a fixes tag is appropriate here.

> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
>  .../bindings/watchdog/renesas,r9a09g057-wdt.yaml          | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
> index 099200c4f136..975c5aa4d747 100644
> --- a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
> @@ -89,11 +89,11 @@ examples:
>    - |
>      #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
>  
> -    watchdog@11c00400 {
> +    watchdog@14400000 {
>              compatible = "renesas,r9a09g057-wdt";
> -            reg = <0x11c00400 0x400>;
> -            clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
> +            reg = <0x14400000 0x400>;
> +            clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
>              clock-names = "pclk", "oscclk";
> -            resets = <&cpg 0x75>;
> +            resets = <&cpg 0x76>;
>              power-domains = <&cpg>;
>      };
> -- 
> 2.34.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

RE: [PATCH mainline-linux 1/3] dt-bindings: watchdog: renesas,r9a09g057-wdt: Rework example

[Fabrizio Castro]

Hi Conor,

Thanks for your feedback.

> From: Conor Dooley <conor@kernel.org>
> Sent: 29 January 2026 17:39
> To: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Cc: Rob Herring <robh@kernel.org>; Guenter Roeck <linux@roeck-us.net>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Wim Van Sebroeck <wim@linux-watchdog.org>;
> Krzysztof Kozlowski <krzk+dt@kernel.org>; Geert Uytterhoeven <geert+renesas@glider.be>; Conor Dooley
> <conor+dt@kernel.org>; magnus.damm <magnus.damm@gmail.com>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>; linux-watchdog@vger.kernel.org; linux-kernel@vger.kernel.org; linux-renesas-
> soc@vger.kernel.org; devicetree@vger.kernel.org; wsa+renesas <wsa+renesas@sang-engineering.com>; linux-
> clk@vger.kernel.org; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH mainline-linux 1/3] dt-bindings: watchdog: renesas,r9a09g057-wdt: Rework example
> 
> On Thu, Jan 29, 2026 at 02:07:29PM +0000, Fabrizio Castro wrote:
> > When the bindings for the Renesas RZ/V2H(P) SoC were factored
> > out IP WDT0 was selected for the example, however the HW user
> > manual states that only IP WDT1 can be used by Linux.
> >
> > This commit is part of a series that removes WDT{0,2,3} support
> > from the kernel, therefore the example from the bindings has
> > lost its meaning.
> >
> > Update the example accordingly.
> >
> > Fixes: fcba2855251f ("dt-bindings: watchdog: factor out RZ/V2H(P) watchdog")
> 
> Given this is an example, I don't think a fixes tag is appropriate here.

I'll take this out in v2.

Cheers,
Fab

> 
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > ---
> >  .../bindings/watchdog/renesas,r9a09g057-wdt.yaml          | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
> b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
> > index 099200c4f136..975c5aa4d747 100644
> > --- a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
> > +++ b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml
> > @@ -89,11 +89,11 @@ examples:
> >    - |
> >      #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
> >
> > -    watchdog@11c00400 {
> > +    watchdog@14400000 {
> >              compatible = "renesas,r9a09g057-wdt";
> > -            reg = <0x11c00400 0x400>;
> > -            clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
> > +            reg = <0x14400000 0x400>;
> > +            clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
> >              clock-names = "pclk", "oscclk";
> > -            resets = <&cpg 0x75>;
> > +            resets = <&cpg 0x76>;
> >              power-domains = <&cpg>;
> >      };
> > --
> > 2.34.1
> >

Re: [PATCH mainline-linux 1/3] dt-bindings: watchdog: renesas,r9a09g057-wdt: Rework example

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1817 bytes --]

On Thu, Jan 29, 2026 at 05:41:24PM +0000, Fabrizio Castro wrote:
> Hi Conor,
> 
> Thanks for your feedback.
> 
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 29 January 2026 17:39
> > To: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > Cc: Rob Herring <robh@kernel.org>; Guenter Roeck <linux@roeck-us.net>; Michael Turquette
> > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Wim Van Sebroeck <wim@linux-watchdog.org>;
> > Krzysztof Kozlowski <krzk+dt@kernel.org>; Geert Uytterhoeven <geert+renesas@glider.be>; Conor Dooley
> > <conor+dt@kernel.org>; magnus.damm <magnus.damm@gmail.com>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> > lad.rj@bp.renesas.com>; linux-watchdog@vger.kernel.org; linux-kernel@vger.kernel.org; linux-renesas-
> > soc@vger.kernel.org; devicetree@vger.kernel.org; wsa+renesas <wsa+renesas@sang-engineering.com>; linux-
> > clk@vger.kernel.org; Biju Das <biju.das.jz@bp.renesas.com>
> > Subject: Re: [PATCH mainline-linux 1/3] dt-bindings: watchdog: renesas,r9a09g057-wdt: Rework example
> > 
> > On Thu, Jan 29, 2026 at 02:07:29PM +0000, Fabrizio Castro wrote:
> > > When the bindings for the Renesas RZ/V2H(P) SoC were factored
> > > out IP WDT0 was selected for the example, however the HW user
> > > manual states that only IP WDT1 can be used by Linux.
> > >
> > > This commit is part of a series that removes WDT{0,2,3} support
> > > from the kernel, therefore the example from the bindings has
> > > lost its meaning.
> > >
> > > Update the example accordingly.
> > >
> > > Fixes: fcba2855251f ("dt-bindings: watchdog: factor out RZ/V2H(P) watchdog")
> > 
> > Given this is an example, I don't think a fixes tag is appropriate here.
> 
> I'll take this out in v2.

w/o fixes,
Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]