Linux clock framework development
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From: Devi Priya <quic_devipriy@quicinc.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: <andersson@kernel.org>, <mturquette@baylibre.com>,
	<sboyd@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
	<conor+dt@kernel.org>, <konrad.dybcio@linaro.org>,
	<catalin.marinas@arm.com>, <will@kernel.org>,
	<p.zabel@pengutronix.de>, <richardcochran@gmail.com>,
	<geert+renesas@glider.be>, <dmitry.baryshkov@linaro.org>,
	<neil.armstrong@linaro.org>, <arnd@arndb.de>,
	<m.szyprowski@samsung.com>, <nfraprado@collabora.com>,
	<u-kumar1@ti.com>, <linux-arm-msm@vger.kernel.org>,
	<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <netdev@vger.kernel.org>
Subject: Re: [PATCH V4 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
Date: Wed, 26 Jun 2024 20:09:15 +0530	[thread overview]
Message-ID: <302298ef-7827-49e1-8b0f-04467cb38ad7@quicinc.com> (raw)
In-Reply-To: <f9d3f263-8559-4357-a1c6-8d4b5fa20b8c@lunn.ch>



On 6/25/2024 8:09 PM, Andrew Lunn wrote:
>> +static struct clk_alpha_pll ubi32_pll_main = {
>> +	.offset = 0x28000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>> +	.flags = SUPPORTS_DYNAMIC_UPDATE,
>> +	.clkr = {
>> +		.hw.init = &(const struct clk_init_data) {
>> +			.name = "ubi32_pll_main",
>> +			.parent_data = &(const struct clk_parent_data) {
>> +				.index = DT_XO,
>> +			},
>> +			.num_parents = 1,
>> +			.ops = &clk_alpha_pll_huayra_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
>> +	.offset = 0x28000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>> +	.width = 2,
>> +	.clkr.hw.init = &(const struct clk_init_data) {
>> +		.name = "ubi32_pll",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +			&ubi32_pll_main.clkr.hw
>> +		},
>> +		.num_parents = 1,
>> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
> 
> Can these structures be made const? You have quite a few different
> structures in this driver, some of which are const, and some which are
> not.
> 
Sure, will check and update this in V6

Thanks,
Devi Priya
> 	Andrew
> 

  reply	other threads:[~2024-06-26 14:40 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-25  7:05 [PATCH V4 0/7] Add NSS clock controller support for IPQ9574 Devi Priya
2024-06-25  7:05 ` [PATCH V4 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574 Devi Priya
2024-06-25  7:05 ` [PATCH V4 2/7] dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX Devi Priya
2024-06-25  7:05 ` [PATCH V4 3/7] clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock Devi Priya
2024-06-25  7:05 ` [PATCH V4 4/7] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions Devi Priya
2024-06-25  8:29   ` Rob Herring (Arm)
2024-06-25  7:05 ` [PATCH V4 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574 Devi Priya
2024-06-25 14:39   ` Andrew Lunn
2024-06-26 14:39     ` Devi Priya [this message]
2024-10-04  7:55       ` Manikanta Mylavarapu
2024-10-04 14:02         ` Andrew Lunn
2024-10-09  7:39           ` Manikanta Mylavarapu
2024-06-25 17:03   ` Konrad Dybcio
2024-06-27  5:37     ` Devi Priya
2024-06-27 15:14       ` Dmitry Baryshkov
2024-06-25  7:05 ` [PATCH V4 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node Devi Priya
2024-06-25  7:05 ` [PATCH V4 7/7] arm64: defconfig: Build NSS Clock Controller driver for IPQ9574 Devi Priya

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