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* [PATCH 02/13] clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228
       [not found] <20240615170417.3134517-1-jonas@kwiboo.se>
@ 2024-06-15 17:03 ` Jonas Karlman
  2024-06-17 20:30   ` Heiko Stübner
  0 siblings, 1 reply; 4+ messages in thread
From: Jonas Karlman @ 2024-06-15 17:03 UTC (permalink / raw)
  To: dri-devel, Michael Turquette, Stephen Boyd, Heiko Stuebner,
	Yakir Yang, Jeffy Chen
  Cc: linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman,
	linux-clk

Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically
parented by the hdmiphy clk and it is expected that the DCLK_VOP and
hdmiphy clk rate are kept in sync.

Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used
on RK3328, to make full use of all possible supported display modes.

Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP")
Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
 drivers/clk/rockchip/clk-rk3228.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index a24a35553e13..7343d2d7676b 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -409,7 +409,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
 			RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
 	DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
 			RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
-	MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
+	MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 			RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
 
 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
-- 
2.45.2


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH 02/13] clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228
  2024-06-15 17:03 ` [PATCH 02/13] clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228 Jonas Karlman
@ 2024-06-17 20:30   ` Heiko Stübner
  2024-06-17 20:50     ` Jonas Karlman
  0 siblings, 1 reply; 4+ messages in thread
From: Heiko Stübner @ 2024-06-17 20:30 UTC (permalink / raw)
  To: dri-devel, Michael Turquette, Stephen Boyd, Yakir Yang,
	Jeffy Chen, Jonas Karlman
  Cc: linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman,
	linux-clk

Am Samstag, 15. Juni 2024, 19:03:53 CEST schrieb Jonas Karlman:
> Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically
> parented by the hdmiphy clk and it is expected that the DCLK_VOP and
> hdmiphy clk rate are kept in sync.
> 
> Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used
> on RK3328, to make full use of all possible supported display modes.
> 
> Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP")
> Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

did your mailer have a hickup? Somehow I got patch2 (only this one)
2 times



^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 02/13] clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228
  2024-06-17 20:30   ` Heiko Stübner
@ 2024-06-17 20:50     ` Jonas Karlman
  2024-06-17 20:56       ` Dragan Simic
  0 siblings, 1 reply; 4+ messages in thread
From: Jonas Karlman @ 2024-06-17 20:50 UTC (permalink / raw)
  To: Heiko Stübner
  Cc: dri-devel, Michael Turquette, Stephen Boyd, Yakir Yang,
	Jeffy Chen, linux-arm-kernel, linux-rockchip, linux-kernel,
	linux-clk

Hi Heiko,

On 2024-06-17 22:30, Heiko Stübner wrote:
> Am Samstag, 15. Juni 2024, 19:03:53 CEST schrieb Jonas Karlman:
>> Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically
>> parented by the hdmiphy clk and it is expected that the DCLK_VOP and
>> hdmiphy clk rate are kept in sync.
>>
>> Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used
>> on RK3328, to make full use of all possible supported display modes.
>>
>> Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP")
>> Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> 
> did your mailer have a hickup? Somehow I got patch2 (only this one)
> 2 times
> 

Strange, not something I know about, each patch 1-13 are listed as 250
Accepted (heiko@sntech.de) and patches arrived to the ML and patchwork:

https://lore.kernel.org/all/20240615170417.3134517-1-jonas@kwiboo.se/
https://patchwork.freedesktop.org/series/134926/
https://patchwork.kernel.org/cover/13699322/

Regards,
Jonas


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 02/13] clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228
  2024-06-17 20:50     ` Jonas Karlman
@ 2024-06-17 20:56       ` Dragan Simic
  0 siblings, 0 replies; 4+ messages in thread
From: Dragan Simic @ 2024-06-17 20:56 UTC (permalink / raw)
  To: Jonas Karlman
  Cc: Heiko Stübner, dri-devel, Michael Turquette, Stephen Boyd,
	Yakir Yang, Jeffy Chen, linux-arm-kernel, linux-rockchip,
	linux-kernel, linux-clk

On 2024-06-17 22:50, Jonas Karlman wrote:
> On 2024-06-17 22:30, Heiko Stübner wrote:
>> Am Samstag, 15. Juni 2024, 19:03:53 CEST schrieb Jonas Karlman:
>>> Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically
>>> parented by the hdmiphy clk and it is expected that the DCLK_VOP and
>>> hdmiphy clk rate are kept in sync.
>>> 
>>> Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as 
>>> used
>>> on RK3328, to make full use of all possible supported display modes.
>>> 
>>> Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 
>>> VOP")
>>> Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for 
>>> rk3228")
>>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>> 
>> did your mailer have a hickup? Somehow I got patch2 (only this one)
>> 2 times
> 
> Strange, not something I know about, each patch 1-13 are listed as 250
> Accepted (heiko@sntech.de) and patches arrived to the ML and patchwork:
> 
> https://lore.kernel.org/all/20240615170417.3134517-1-jonas@kwiboo.se/
> https://patchwork.freedesktop.org/series/134926/
> https://patchwork.kernel.org/cover/13699322/

It might be that something is wrong with the MX host for sntech.de, I 
got
one email rejected today with "invalid certificate" (or something like 
that)
as the error message.

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2024-06-17 20:57 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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     [not found] <20240615170417.3134517-1-jonas@kwiboo.se>
2024-06-15 17:03 ` [PATCH 02/13] clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228 Jonas Karlman
2024-06-17 20:30   ` Heiko Stübner
2024-06-17 20:50     ` Jonas Karlman
2024-06-17 20:56       ` Dragan Simic

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