[PATCH v1 0/2] Add CMU_HSI1 support for Exynos990 SoC

[PATCH v1 0/2] Add CMU_HSI1 support for Exynos990 SoC

[Umer Uddin]

Hi all, definitely long time no see.

This small patchset adds support for the CMU_HSI1 block for the
Exynos990 SoC. Gates are not implemented as we can make use of
the HWACG system set up by previous bootloaders.

Best regards,
Umer Uddin

Umer Uddin (2):
  dt-bindings: clock: exynos990: Add CMU_HSI1 bindings
  clk: samsung: exynos990: Add CMU_HSI1 block

 .../clock/samsung,exynos990-clock.yaml        |  27 +++
 drivers/clk/samsung/clk-exynos990.c           | 221 ++++++++++++++++++
 include/dt-bindings/clock/samsung,exynos990.h |   7 +
 3 files changed, 255 insertions(+)

-- 
2.47.2

[PATCH v1 1/2] dt-bindings: clock: exynos990: Add CMU_HSI1 bindings

[Umer Uddin]

Add dt-schema documentation for the Exynos990 CMU_HSI1 block.

This clock management unit provides clocks for the DesignWare MMC
controller, PCIE subsystem and UFS subsystem.

Signed-off-by: Umer Uddin <umer.uddin@mentallysanemainliners.org>
---
 .../clock/samsung,exynos990-clock.yaml        | 27 +++++++++++++++++++
 include/dt-bindings/clock/samsung,exynos990.h |  7 +++++
 2 files changed, 34 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
index c15cc1752..ce3b845ce 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
@@ -31,6 +31,7 @@ properties:
   compatible:
     enum:
       - samsung,exynos990-cmu-hsi0
+      - samsung,exynos990-cmu-hsi1
       - samsung,exynos990-cmu-peris
       - samsung,exynos990-cmu-top
 
@@ -80,6 +81,32 @@ allOf:
             - const: usbdp_debug
             - const: dpgtc
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos990-cmu-hsi1
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_HSI1 BUS clock (from CMU_TOP)
+            - description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)
+            - description: CMU_HSI1 PCIE clock (from CMU_TOP)
+            - description: CMU_HSI1 UFS_CARD clock (from CMU_TOP)
+            - description: CMU_HSI1 UFS_EMBD clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: mmc_card
+            - const: pcie
+            - const: ufs_card
+            - const: ufs_embd
+
   - if:
       properties:
         compatible:
diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h
index 6b9df09d2..3164cca44 100644
--- a/include/dt-bindings/clock/samsung,exynos990.h
+++ b/include/dt-bindings/clock/samsung,exynos990.h
@@ -254,4 +254,11 @@
 #define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK	18
 #define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK	19
 
+/* CMU_HSI1 */
+#define CLK_MOUT_HSI1_BUS_USER		1
+#define CLK_MOUT_HSI1_MMC_CARD_USER	2
+#define CLK_MOUT_HSI1_PCIE_USER		3
+#define CLK_MOUT_HSI1_UFS_CARD_USER	4
+#define CLK_MOUT_HSI1_UFS_EMBD_USER	5
+
 #endif
-- 
2.47.2

[PATCH v1 2/2] clk: samsung: exynos990: Add CMU_HSI1 block

[Umer Uddin]

The CMU_HSI1 block is used for providing clocks for the DesignWare
MMC Controller, PCIE Subsystem and UFS subsystem, and has six
dependency clocks from CMU_TOP.

Signed-off-by: Umer Uddin <umer.uddin@mentallysanemainliners.org>
---
 drivers/clk/samsung/clk-exynos990.c | 221 ++++++++++++++++++++++++++++
 1 file changed, 221 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
index 8d3f193d2..91ecbafcf 100644
--- a/drivers/clk/samsung/clk-exynos990.c
+++ b/drivers/clk/samsung/clk-exynos990.c
@@ -20,6 +20,7 @@
 #define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1)
 #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1)
 #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1)
+#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_UFS_EMBD_USER + 1)
 
 /* ---- CMU_TOP ------------------------------------------------------------- */
 
@@ -1483,6 +1484,222 @@ static void __init exynos990_cmu_peris_init(struct device_node *np)
 CLK_OF_DECLARE(exynos990_cmu_peris, "samsung,exynos990-cmu-peris",
 	       exynos990_cmu_peris_init);
 
+/* ---- CMU_HSI1 ------------------------------------------------------------ */
+
+/* Register Offset definitions for CMU_HSI1 (0x13000000) */
+#define PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER												0x0600
+#define PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER												0x0604
+#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER												0x0610
+#define PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER												0x0614
+#define PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER												0x0620
+#define PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER												0x0624
+#define PLL_CON0_MUX_CLKCMU_HSI1_UFS_CARD_USER												0x0630
+#define PLL_CON1_MUX_CLKCMU_HSI1_UFS_CARD_USER												0x0634
+#define PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER												0x0640
+#define PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER												0x0644
+#define HSI1_CMU_HSI1_CONTROLLER_OPTION													0x0800
+#define CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN									0x2000
+#define CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN					0x2004
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK									0x2008
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK										0x200c
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK									0x2010
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK									0x2014
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK									0x2018
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK										0x201c
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN									0x2020
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK									0x2024
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK			0x2028
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK									0x202c
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK						0x2030
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL					0x2034
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK									0x2038
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG				0x203c
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG				0x2040
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG				0x2044
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK				0x2048
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK				0x204c
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY000X2_LN07LPP_QCH_TM_WRAPPER_INST_0_I_APB_PCLK	0x2050
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK									0x2054
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK									0x2058
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK										0x205c
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK										0x2060
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK								0x2064
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK								0x2068
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2									0x206c
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK									0x2070
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_ACLK										0x2074
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO									0x2078
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK									0x207c
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK										0x2080
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO									0x2084
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK									0x2088
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK									0x208c
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK										0x2090
+#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK										0x2094
+#define DMYQCH_CON_PCIE_GEN2_QCH_REF													0x3000
+#define DMYQCH_CON_PCIE_GEN4_0_QCH_REF													0x3004
+#define QCH_CON_D_TZPC_HSI1_QCH														0x3024
+#define QCH_CON_GPIO_HSI1_QCH														0x3028
+#define QCH_CON_HSI1_CMU_HSI1_QCH													0x302c
+#define QCH_CON_LHM_AXI_P_HSI1_QCH													0x3030
+#define QCH_CON_LHS_ACEL_D_HSI1_QCH													0x3034
+#define QCH_CON_MMC_CARD_QCH														0x3038
+#define QCH_CON_PCIE_GEN2_QCH_APB													0x303c
+#define QCH_CON_PCIE_GEN2_QCH_DBI													0x3040
+#define QCH_CON_PCIE_GEN2_QCH_MSTR													0x3044
+#define QCH_CON_PCIE_GEN2_QCH_PCS													0x3048
+#define QCH_CON_PCIE_GEN2_QCH_PHY													0x304c
+#define QCH_CON_PCIE_GEN4_0_QCH_APB													0x3050
+#define QCH_CON_PCIE_GEN4_0_QCH_AXI													0x3054
+#define QCH_CON_PCIE_GEN4_0_QCH_DBI													0x3058
+#define QCH_CON_PCIE_GEN4_0_QCH_PCS_APB													0x305c
+#define QCH_CON_PCIE_GEN4_0_QCH_PMA_APB													0x3060
+#define QCH_CON_PCIE_IA_GEN2_QCH													0x3064
+#define QCH_CON_PCIE_IA_GEN4_0_QCH													0x3068
+#define QCH_CON_PPMU_HSI1_QCH														0x306c
+#define QCH_CON_SYSMMU_HSI1_QCH														0x3070
+#define QCH_CON_SYSREG_HSI1_QCH														0x3074
+#define QCH_CON_UFS_CARD_QCH														0x3078
+#define QCH_CON_UFS_CARD_QCH_FMP													0x307c
+#define QCH_CON_UFS_EMBD_QCH														0x3080
+#define QCH_CON_UFS_EMBD_QCH_FMP													0x3084
+#define QCH_CON_VGEN_LITE_HSI1_QCH													0x3088
+
+static const unsigned long hsi1_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER,
+	PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER,
+	PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,
+	PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER,
+	PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER,
+	PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER,
+	PLL_CON0_MUX_CLKCMU_HSI1_UFS_CARD_USER,
+	PLL_CON1_MUX_CLKCMU_HSI1_UFS_CARD_USER,
+	PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER,
+	PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER,
+	HSI1_CMU_HSI1_CONTROLLER_OPTION,
+	CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN,
+	CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY000X2_LN07LPP_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_ACLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK,
+	CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK,
+	DMYQCH_CON_PCIE_GEN2_QCH_REF,
+	DMYQCH_CON_PCIE_GEN4_0_QCH_REF,
+	QCH_CON_D_TZPC_HSI1_QCH,
+	QCH_CON_GPIO_HSI1_QCH,
+	QCH_CON_HSI1_CMU_HSI1_QCH,
+	QCH_CON_LHM_AXI_P_HSI1_QCH,
+	QCH_CON_LHS_ACEL_D_HSI1_QCH,
+	QCH_CON_MMC_CARD_QCH,
+	QCH_CON_PCIE_GEN2_QCH_APB,
+	QCH_CON_PCIE_GEN2_QCH_DBI,
+	QCH_CON_PCIE_GEN2_QCH_MSTR,
+	QCH_CON_PCIE_GEN2_QCH_PCS,
+	QCH_CON_PCIE_GEN2_QCH_PHY,
+	QCH_CON_PCIE_GEN4_0_QCH_APB,
+	QCH_CON_PCIE_GEN4_0_QCH_AXI,
+	QCH_CON_PCIE_GEN4_0_QCH_DBI,
+	QCH_CON_PCIE_GEN4_0_QCH_PCS_APB,
+	QCH_CON_PCIE_GEN4_0_QCH_PMA_APB,
+	QCH_CON_PCIE_IA_GEN2_QCH,
+	QCH_CON_PCIE_IA_GEN4_0_QCH,
+	QCH_CON_PPMU_HSI1_QCH,
+	QCH_CON_SYSMMU_HSI1_QCH,
+	QCH_CON_SYSREG_HSI1_QCH,
+	QCH_CON_UFS_CARD_QCH,
+	QCH_CON_UFS_CARD_QCH_FMP,
+	QCH_CON_UFS_EMBD_QCH,
+	QCH_CON_UFS_EMBD_QCH_FMP,
+	QCH_CON_VGEN_LITE_HSI1_QCH,
+};
+
+/* Parent clock list for CMU_HSI1 muxes */
+PNAME(mout_hsi1_ufs_embd_p) =		{ "oscclk",
+					  "dout_cmu_shared0_div4",
+					  "dout_cmu_shared2_div2",
+					  "oscclk" };
+PNAME(mout_hsi1_ufs_card_p) =		{ "oscclk",
+					  "dout_cmu_shared0_div4",
+					  "dout_cmu_shared2_div2",
+					  "oscclk" };
+PNAME(mout_hsi1_pcie_p) =		{ "oscclk", "fout_shared2_pll" };
+PNAME(mout_hsi1_bus_p) =		{ "dout_cmu_shared0_div3",
+					  "dout_cmu_shared0_div4",
+					  "dout_cmu_shared1_div4",
+					  "dout_cmu_shared4_div3",
+					  "dout_cmu_shared2_div2",
+					  "fout_mmc_pll",
+					  "oscclk",
+					  "oscclk" };
+PNAME(mout_hsi1_mmc_card_p) =		{ "oscclk",
+					  "fout_shared2_pll",
+					  "fout_mmc_pll",
+					  "dout_cmu_shared0_div4" };
+PNAME(mout_hsi1_bus_user_p) =		{ "oscclk", "dout_cmu_hsi1_bus" };
+PNAME(mout_hsi1_mmc_card_user_p) =	{ "oscclk", "dout_cmu_hsi1_mmc_card" };
+PNAME(mout_hsi1_pcie_user_p) =		{ "oscclk", "dout_cmu_hsi1_pcie" };
+PNAME(mout_hsi1_ufs_card_user_p) =	{ "oscclk", "dout_cmu_hsi1_ufs_card" };
+PNAME(mout_hsi1_ufs_embd_user_p) =	{ "oscclk", "dout_cmu_hsi1_ufs_embd" };
+
+static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_HSI1_BUS_USER, "mout_hsi1_bus_user",
+	    mout_hsi1_bus_user_p, PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER,
+	    4, 1),
+	MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user",
+	    mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,
+	    4, 1),
+	MUX(CLK_MOUT_HSI1_PCIE_USER, "mout_hsi1_pcie_user",
+	    mout_hsi1_pcie_user_p, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER,
+	    4, 1),
+	MUX(CLK_MOUT_HSI1_UFS_CARD_USER, "mout_hsi1_ufs_card_user",
+	    mout_hsi1_ufs_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_UFS_CARD_USER,
+	    4, 1),
+	MUX(CLK_MOUT_HSI1_UFS_EMBD_USER, "mout_hsi1_ufs_embd_user",
+	    mout_hsi1_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER,
+	    4, 1),
+};
+
+static const struct samsung_cmu_info hsi1_cmu_info __initconst = {
+	.mux_clks = hsi1_mux_clks,
+	.nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks),
+	.nr_clk_ids = CLKS_NR_HSI1,
+	.clk_regs = hsi1_clk_regs,
+	.nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs),
+	.clk_name		= "bus",
+};
+
 /* ----- platform_driver ----- */
 
 static int __init exynos990_cmu_probe(struct platform_device *pdev)
@@ -1501,6 +1718,10 @@ static const struct of_device_id exynos990_cmu_of_match[] = {
 		.compatible = "samsung,exynos990-cmu-hsi0",
 		.data = &hsi0_cmu_info,
 	},
+	{
+		.compatible = "samsung,exynos990-cmu-hsi1",
+		.data = &hsi1_cmu_info,
+	},
 	{ },
 };
 
-- 
2.47.2

Re: [PATCH v1 2/2] clk: samsung: exynos990: Add CMU_HSI1 block

[kernel test robot]

Hi Umer,

kernel test robot noticed the following build warnings:

[auto build test WARNING on krzk/for-next]
[also build test WARNING on krzk-dt/for-next clk/clk-next linus/master v6.15 next-20250528]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Umer-Uddin/dt-bindings-clock-exynos990-Add-CMU_HSI1-bindings/20250528-185847
base:   https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
patch link:    https://lore.kernel.org/r/20250528105252.157533-3-umer.uddin%40mentallysanemainliners.org
patch subject: [PATCH v1 2/2] clk: samsung: exynos990: Add CMU_HSI1 block
config: arm-randconfig-002-20250529 (https://download.01.org/0day-ci/archive/20250529/202505290752.ccgBnlpc-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250529/202505290752.ccgBnlpc-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505290752.ccgBnlpc-lkp@intel.com/

All warnings (new ones prefixed by >>):

   In file included from drivers/clk/samsung/clk-exynos990.c:15:
>> drivers/clk/samsung/clk-exynos990.c:1666:7: warning: 'mout_hsi1_mmc_card_p' defined but not used [-Wunused-const-variable=]
    PNAME(mout_hsi1_mmc_card_p) =  { "oscclk",
          ^~~~~~~~~~~~~~~~~~~~
   drivers/clk/samsung/clk.h:237:44: note: in definition of macro 'PNAME'
    #define PNAME(x) static const char * const x[] __initconst
                                               ^
>> drivers/clk/samsung/clk-exynos990.c:1658:7: warning: 'mout_hsi1_bus_p' defined but not used [-Wunused-const-variable=]
    PNAME(mout_hsi1_bus_p) =  { "dout_cmu_shared0_div3",
          ^~~~~~~~~~~~~~~
   drivers/clk/samsung/clk.h:237:44: note: in definition of macro 'PNAME'
    #define PNAME(x) static const char * const x[] __initconst
                                               ^
>> drivers/clk/samsung/clk-exynos990.c:1657:7: warning: 'mout_hsi1_pcie_p' defined but not used [-Wunused-const-variable=]
    PNAME(mout_hsi1_pcie_p) =  { "oscclk", "fout_shared2_pll" };
          ^~~~~~~~~~~~~~~~
   drivers/clk/samsung/clk.h:237:44: note: in definition of macro 'PNAME'
    #define PNAME(x) static const char * const x[] __initconst
                                               ^
>> drivers/clk/samsung/clk-exynos990.c:1653:7: warning: 'mout_hsi1_ufs_card_p' defined but not used [-Wunused-const-variable=]
    PNAME(mout_hsi1_ufs_card_p) =  { "oscclk",
          ^~~~~~~~~~~~~~~~~~~~
   drivers/clk/samsung/clk.h:237:44: note: in definition of macro 'PNAME'
    #define PNAME(x) static const char * const x[] __initconst
                                               ^
>> drivers/clk/samsung/clk-exynos990.c:1649:7: warning: 'mout_hsi1_ufs_embd_p' defined but not used [-Wunused-const-variable=]
    PNAME(mout_hsi1_ufs_embd_p) =  { "oscclk",
          ^~~~~~~~~~~~~~~~~~~~
   drivers/clk/samsung/clk.h:237:44: note: in definition of macro 'PNAME'
    #define PNAME(x) static const char * const x[] __initconst
                                               ^


vim +/mout_hsi1_mmc_card_p +1666 drivers/clk/samsung/clk-exynos990.c

  1647	
  1648	/* Parent clock list for CMU_HSI1 muxes */
> 1649	PNAME(mout_hsi1_ufs_embd_p) =		{ "oscclk",
  1650						  "dout_cmu_shared0_div4",
  1651						  "dout_cmu_shared2_div2",
  1652						  "oscclk" };
> 1653	PNAME(mout_hsi1_ufs_card_p) =		{ "oscclk",
  1654						  "dout_cmu_shared0_div4",
  1655						  "dout_cmu_shared2_div2",
  1656						  "oscclk" };
> 1657	PNAME(mout_hsi1_pcie_p) =		{ "oscclk", "fout_shared2_pll" };
> 1658	PNAME(mout_hsi1_bus_p) =		{ "dout_cmu_shared0_div3",
  1659						  "dout_cmu_shared0_div4",
  1660						  "dout_cmu_shared1_div4",
  1661						  "dout_cmu_shared4_div3",
  1662						  "dout_cmu_shared2_div2",
  1663						  "fout_mmc_pll",
  1664						  "oscclk",
  1665						  "oscclk" };
> 1666	PNAME(mout_hsi1_mmc_card_p) =		{ "oscclk",
  1667						  "fout_shared2_pll",
  1668						  "fout_mmc_pll",
  1669						  "dout_cmu_shared0_div4" };
  1670	PNAME(mout_hsi1_bus_user_p) =		{ "oscclk", "dout_cmu_hsi1_bus" };
  1671	PNAME(mout_hsi1_mmc_card_user_p) =	{ "oscclk", "dout_cmu_hsi1_mmc_card" };
  1672	PNAME(mout_hsi1_pcie_user_p) =		{ "oscclk", "dout_cmu_hsi1_pcie" };
  1673	PNAME(mout_hsi1_ufs_card_user_p) =	{ "oscclk", "dout_cmu_hsi1_ufs_card" };
  1674	PNAME(mout_hsi1_ufs_embd_user_p) =	{ "oscclk", "dout_cmu_hsi1_ufs_embd" };
  1675	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v1 2/2] clk: samsung: exynos990: Add CMU_HSI1 block

[Krzysztof Kozlowski]

On 28/05/2025 12:52, Umer Uddin wrote:
> The CMU_HSI1 block is used for providing clocks for the DesignWare
> MMC Controller, PCIE Subsystem and UFS subsystem, and has six
> dependency clocks from CMU_TOP.
> 
> Signed-off-by: Umer Uddin <umer.uddin@mentallysanemainliners.org>
> ---
>  drivers/clk/samsung/clk-exynos990.c | 221 ++++++++++++++++++++++++++++
>  1 file changed, 221 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
> index 8d3f193d2..91ecbafcf 100644
> --- a/drivers/clk/samsung/clk-exynos990.c
> +++ b/drivers/clk/samsung/clk-exynos990.c
> @@ -20,6 +20,7 @@
>  #define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1)
>  #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1)
>  #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1)
> +#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_UFS_EMBD_USER + 1)
>  
>  /* ---- CMU_TOP ------------------------------------------------------------- */
>  
> @@ -1483,6 +1484,222 @@ static void __init exynos990_cmu_peris_init(struct device_node *np)
>  CLK_OF_DECLARE(exynos990_cmu_peris, "samsung,exynos990-cmu-peris",
>  	       exynos990_cmu_peris_init);
>  
> +/* ---- CMU_HSI1 ------------------------------------------------------------ */
> +
> +/* Register Offset definitions for CMU_HSI1 (0x13000000) */
> +#define PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER												0x0600


This is way past coding style limit: 80.

This is way past hard cut-off: checkpatch.

> +#define PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER												0x0604
> +#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER												0x0610
> +#define PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER												0x0614
> +#define PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER												0x0620
> +#define PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER												0x0624
> +#define PLL_CON0_MUX_CLKCMU_HSI1_UFS_CARD_USER												0x0630
> +#define PLL_CON1_MUX_CLKCMU_HSI1_UFS_CARD_USER												0x0634
> +#define PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER												0x0640
> +#define PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER												0x0644
> +#define HSI1_CMU_HSI1_CONTROLLER_OPTION													0x0800
> +#define CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN									0x2000
> +#define CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN					0x2004
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK									0x2008
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK										0x200c
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK									0x2010
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK									0x2014
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK									0x2018
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK										0x201c
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN									0x2020
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK									0x2024
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK			0x2028
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK									0x202c
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK						0x2030
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL					0x2034
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK									0x2038
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG				0x203c
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG				0x2040
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG				0x2044
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK				0x2048
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK				0x204c
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY000X2_LN07LPP_QCH_TM_WRAPPER_INST_0_I_APB_PCLK	0x2050

These names are not really useful. Please shorten them to 50-55 characters.

> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK									0x2054
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK									0x2058
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK										0x205c
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK										0x2060
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK								0x2064
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK								0x2068
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2									0x206c
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK									0x2070
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_ACLK										0x2074
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO									0x2078
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK									0x207c
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK										0x2080
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO									0x2084
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK									0x2088
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK									0x208c
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK										0x2090
> +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK										0x2094
> +#define DMYQCH_CON_PCIE_GEN2_QCH_REF													0x3000
> +#define DMYQCH_CON_PCIE_GEN4_0_QCH_REF													0x3004
> +#define QCH_CON_D_TZPC_HSI1_QCH														0x3024
> +#define QCH_CON_GPIO_HSI1_QCH														0x3028
> +#define QCH_CON_HSI1_CMU_HSI1_QCH													0x302c
> +#define QCH_CON_LHM_AXI_P_HSI1_QCH													0x3030
> +#define QCH_CON_LHS_ACEL_D_HSI1_QCH													0x3034
> +#define QCH_CON_MMC_CARD_QCH														0x3038
> +#define QCH_CON_PCIE_GEN2_QCH_APB													0x303c
> +#define QCH_CON_PCIE_GEN2_QCH_DBI													0x3040
> +#define QCH_CON_PCIE_GEN2_QCH_MSTR	


Best regards,
Krzysztof