[PATCH 0/6] Specify Titan GDSC power domain as a parent to other

[PATCH 0/6] Specify Titan GDSC power domain as a parent to other

[Vladimir Zapolskiy]

Make Titan GDSC power domain as a parent of all other GDSC power domains
provided by the Qualcomm camera clock controller to enforce a correct
sequence of enabling and disabling power domains by the consumers.

Only two Fixes tags are given, because so far there is no any consumers
of IPEx, BPS or SBI GDSC power domains, however the changes of making
an explicit PD hierarchy with Titan on the top will be helpful in future.

Vladimir Zapolskiy (6):
  clk: qcom: camcc-sm8550: Specify Titan GDSC power domain as a parent to other
  clk: qcom: camcc-sm6350: Specify Titan GDSC power domain as a parent to other
  clk: qcom: camcc-sdm845: Specify Titan GDSC power domain as a parent to other
  clk: qcom: camcc-sm7150: Specify Titan GDSC power domain as a parent to IPEx and BPS
  clk: qcom: camcc-sm8250: Specify Titan GDSC power domain as a parent to IPE/BPS/SBI
  clk: qcom: camcc-sm8450: Specify Titan GDSC power domain as a parent to IPE/BPS/SBI

 drivers/clk/qcom/camcc-sdm845.c |  3 +++
 drivers/clk/qcom/camcc-sm6350.c |  7 +++++++
 drivers/clk/qcom/camcc-sm7150.c |  3 +++
 drivers/clk/qcom/camcc-sm8250.c |  3 +++
 drivers/clk/qcom/camcc-sm8450.c |  3 +++
 drivers/clk/qcom/camcc-sm8550.c | 10 ++++++++++
 6 files changed, 29 insertions(+)

-- 
2.49.0

[PATCH 1/6] clk: qcom: camcc-sm8550: Specify Titan GDSC power domain as a parent to other

[Vladimir Zapolskiy]

Make Titan GDSC power domain as a parent of all other GDSC power domains
provided by the SM8550 camera clock controller to enforce a correct
sequence of enabling and disabling power domains by the consumers.

Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
 drivers/clk/qcom/camcc-sm8550.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
index 63aed9e4c362..b8ece8a57a8a 100644
--- a/drivers/clk/qcom/camcc-sm8550.c
+++ b/drivers/clk/qcom/camcc-sm8550.c
@@ -3204,6 +3204,8 @@ static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
 	},
 };
 
+static struct gdsc cam_cc_titan_top_gdsc;
+
 static struct gdsc cam_cc_bps_gdsc = {
 	.gdscr = 0x10004,
 	.en_rest_wait_val = 0x2,
@@ -3213,6 +3215,7 @@ static struct gdsc cam_cc_bps_gdsc = {
 		.name = "cam_cc_bps_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &cam_cc_titan_top_gdsc.pd,
 	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3225,6 +3228,7 @@ static struct gdsc cam_cc_ife_0_gdsc = {
 		.name = "cam_cc_ife_0_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &cam_cc_titan_top_gdsc.pd,
 	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3237,6 +3241,7 @@ static struct gdsc cam_cc_ife_1_gdsc = {
 		.name = "cam_cc_ife_1_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &cam_cc_titan_top_gdsc.pd,
 	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3249,6 +3254,7 @@ static struct gdsc cam_cc_ife_2_gdsc = {
 		.name = "cam_cc_ife_2_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &cam_cc_titan_top_gdsc.pd,
 	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3261,6 +3267,7 @@ static struct gdsc cam_cc_ipe_0_gdsc = {
 		.name = "cam_cc_ipe_0_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &cam_cc_titan_top_gdsc.pd,
 	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3273,6 +3280,7 @@ static struct gdsc cam_cc_sbi_gdsc = {
 		.name = "cam_cc_sbi_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &cam_cc_titan_top_gdsc.pd,
 	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3285,6 +3293,7 @@ static struct gdsc cam_cc_sfe_0_gdsc = {
 		.name = "cam_cc_sfe_0_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &cam_cc_titan_top_gdsc.pd,
 	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
@@ -3297,6 +3306,7 @@ static struct gdsc cam_cc_sfe_1_gdsc = {
 		.name = "cam_cc_sfe_1_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &cam_cc_titan_top_gdsc.pd,
 	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
 };
 
-- 
2.49.0

[PATCH 2/6] clk: qcom: camcc-sm6350: Specify Titan GDSC power domain as a parent to other

[Vladimir Zapolskiy]

Make Titan GDSC power domain as a parent of all other GDSC power domains
provided by the SM6350 camera clock controller to enforce a correct
sequence of enabling and disabling power domains by the consumers.

Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
 drivers/clk/qcom/camcc-sm6350.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c
index 8aac97d29ce3..6c272f7b0721 100644
--- a/drivers/clk/qcom/camcc-sm6350.c
+++ b/drivers/clk/qcom/camcc-sm6350.c
@@ -1693,6 +1693,8 @@ static struct clk_branch camcc_sys_tmr_clk = {
 	},
 };
 
+static struct gdsc titan_top_gdsc;
+
 static struct gdsc bps_gdsc = {
 	.gdscr = 0x6004,
 	.en_rest_wait_val = 0x2,
@@ -1702,6 +1704,7 @@ static struct gdsc bps_gdsc = {
 		.name = "bps_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &titan_top_gdsc.pd,
 	.flags = VOTABLE,
 };
 
@@ -1714,6 +1717,7 @@ static struct gdsc ipe_0_gdsc = {
 		.name = "ipe_0_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &titan_top_gdsc.pd,
 	.flags = VOTABLE,
 };
 
@@ -1726,6 +1730,7 @@ static struct gdsc ife_0_gdsc = {
 		.name = "ife_0_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &titan_top_gdsc.pd,
 };
 
 static struct gdsc ife_1_gdsc = {
@@ -1737,6 +1742,7 @@ static struct gdsc ife_1_gdsc = {
 		.name = "ife_1_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &titan_top_gdsc.pd,
 };
 
 static struct gdsc ife_2_gdsc = {
@@ -1748,6 +1754,7 @@ static struct gdsc ife_2_gdsc = {
 		.name = "ife_2_gdsc",
 	},
 	.pwrsts = PWRSTS_OFF_ON,
+	.parent = &titan_top_gdsc.pd,
 };
 
 static struct gdsc titan_top_gdsc = {
-- 
2.49.0

[PATCH 3/6] clk: qcom: camcc-sdm845: Specify Titan GDSC power domain as a parent to other

[Vladimir Zapolskiy]

Make Titan GDSC power domain as a parent of all other GDSC power domains
provided by the SDM845 camera clock controller, and it should include
IPE0/1 and BPS ones, even if there are no users of them currently.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
 drivers/clk/qcom/camcc-sdm845.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
index cf60e8dd292a..fb313da7165b 100644
--- a/drivers/clk/qcom/camcc-sdm845.c
+++ b/drivers/clk/qcom/camcc-sdm845.c
@@ -1543,6 +1543,7 @@ static struct gdsc bps_gdsc = {
 		.name = "bps_gdsc",
 	},
 	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.parent = &titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
@@ -1552,6 +1553,7 @@ static struct gdsc ipe_0_gdsc = {
 		.name = "ipe_0_gdsc",
 	},
 	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.parent = &titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
@@ -1561,6 +1563,7 @@ static struct gdsc ipe_1_gdsc = {
 		.name = "ipe_1_gdsc",
 	},
 	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.parent = &titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
-- 
2.49.0

[PATCH 4/6] clk: qcom: camcc-sm7150: Specify Titan GDSC power domain as a parent to IPEx and BPS

[Vladimir Zapolskiy]

Make Titan GDSC power domain as a parent of all other GDSC power domains
provided by the SM7150 camera clock controller, and it should include
IPE0/1 and BPS ones, even if there are no users of them currently.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
 drivers/clk/qcom/camcc-sm7150.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/qcom/camcc-sm7150.c b/drivers/clk/qcom/camcc-sm7150.c
index 4a3baf5d8e85..0e072ae39ec0 100644
--- a/drivers/clk/qcom/camcc-sm7150.c
+++ b/drivers/clk/qcom/camcc-sm7150.c
@@ -1846,6 +1846,7 @@ static struct gdsc camcc_bps_gdsc = {
 		.name = "camcc_bps_gdsc",
 	},
 	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.parent = &camcc_titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
@@ -1875,6 +1876,7 @@ static struct gdsc camcc_ipe_0_gdsc = {
 		.name = "camcc_ipe_0_gdsc",
 	},
 	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.parent = &camcc_titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
@@ -1884,6 +1886,7 @@ static struct gdsc camcc_ipe_1_gdsc = {
 		.name = "camcc_ipe_1_gdsc",
 	},
 	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.parent = &camcc_titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
-- 
2.49.0

[PATCH 5/6] clk: qcom: camcc-sm8250: Specify Titan GDSC power domain as a parent to IPE/BPS/SBI

[Vladimir Zapolskiy]

Make Titan GDSC power domain as a parent of all other GDSC power domains
provided by the SM8250 camera clock controller, and it should include
IPE, BPS and SBI ones, even if there are no users of them currently.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
 drivers/clk/qcom/camcc-sm8250.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c
index 6da89c49ba3d..c95a00628630 100644
--- a/drivers/clk/qcom/camcc-sm8250.c
+++ b/drivers/clk/qcom/camcc-sm8250.c
@@ -2213,6 +2213,7 @@ static struct gdsc bps_gdsc = {
 		.name = "bps_gdsc",
 	},
 	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.parent = &titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
@@ -2222,6 +2223,7 @@ static struct gdsc ipe_0_gdsc = {
 		.name = "ipe_0_gdsc",
 	},
 	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.parent = &titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
@@ -2231,6 +2233,7 @@ static struct gdsc sbi_gdsc = {
 		.name = "sbi_gdsc",
 	},
 	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.parent = &titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
-- 
2.49.0

[PATCH 6/6] clk: qcom: camcc-sm8450: Specify Titan GDSC power domain as a parent to IPE/BPS/SBI

[Vladimir Zapolskiy]

Make Titan GDSC power domain as a parent of all other GDSC power domains
provided by the SD8450 camera clock controller, and it should include
IPE, BPS and SBI ones, even if there are no users of them currently.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
 drivers/clk/qcom/camcc-sm8450.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c
index 4dd8be8cc988..ef8cf54d0eed 100644
--- a/drivers/clk/qcom/camcc-sm8450.c
+++ b/drivers/clk/qcom/camcc-sm8450.c
@@ -2935,6 +2935,7 @@ static struct gdsc bps_gdsc = {
 		.name = "bps_gdsc",
 	},
 	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.parent = &titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
@@ -2944,6 +2945,7 @@ static struct gdsc ipe_0_gdsc = {
 		.name = "ipe_0_gdsc",
 	},
 	.flags = HW_CTRL | POLL_CFG_GDSCR,
+	.parent = &titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
@@ -2953,6 +2955,7 @@ static struct gdsc sbi_gdsc = {
 		.name = "sbi_gdsc",
 	},
 	.flags = POLL_CFG_GDSCR,
+	.parent = &titan_top_gdsc.pd,
 	.pwrsts = PWRSTS_OFF_ON,
 };
 
-- 
2.49.0

Re: [PATCH 2/6] clk: qcom: camcc-sm6350: Specify Titan GDSC power domain as a parent to other

[Konrad Dybcio]

On 9/11/25 3:12 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM6350 camera clock controller to enforce a correct
> sequence of enabling and disabling power domains by the consumers.
> 
> Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350")
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 3/6] clk: qcom: camcc-sdm845: Specify Titan GDSC power domain as a parent to other

[Konrad Dybcio]

On 9/11/25 3:12 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SDM845 camera clock controller, and it should include
> IPE0/1 and BPS ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 4/6] clk: qcom: camcc-sm7150: Specify Titan GDSC power domain as a parent to IPEx and BPS

[Konrad Dybcio]

On 9/11/25 3:12 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM7150 camera clock controller, and it should include
> IPE0/1 and BPS ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 5/6] clk: qcom: camcc-sm8250: Specify Titan GDSC power domain as a parent to IPE/BPS/SBI

[Konrad Dybcio]

On 9/11/25 3:12 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM8250 camera clock controller, and it should include
> IPE, BPS and SBI ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 6/6] clk: qcom: camcc-sm8450: Specify Titan GDSC power domain as a parent to IPE/BPS/SBI

[Konrad Dybcio]

On 9/11/25 3:12 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SD8450 camera clock controller, and it should include
> IPE, BPS and SBI ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 1/6] clk: qcom: camcc-sm8550: Specify Titan GDSC power domain as a parent to other

[Konrad Dybcio]

On 9/11/25 3:12 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM8550 camera clock controller to enforce a correct
> sequence of enabling and disabling power domains by the consumers.
> 
> Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550")
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 1/6] clk: qcom: camcc-sm8550: Specify Titan GDSC power domain as a parent to other

[Imran Shaik]

On 9/11/2025 6:42 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM8550 camera clock controller to enforce a correct
> sequence of enabling and disabling power domains by the consumers.
> 
> Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550")
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>  drivers/clk/qcom/camcc-sm8550.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>

Thanks,
Imran

Re: [PATCH 2/6] clk: qcom: camcc-sm6350: Specify Titan GDSC power domain as a parent to other

[Imran Shaik]

On 9/11/2025 6:42 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM6350 camera clock controller to enforce a correct
> sequence of enabling and disabling power domains by the consumers.
> 
> Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350")
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>  drivers/clk/qcom/camcc-sm6350.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>

Thanks,
Imran

Re: [PATCH 3/6] clk: qcom: camcc-sdm845: Specify Titan GDSC power domain as a parent to other

[Imran Shaik]

On 9/11/2025 6:42 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SDM845 camera clock controller, and it should include
> IPE0/1 and BPS ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>  drivers/clk/qcom/camcc-sdm845.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>

Thanks,
Imran

Re: [PATCH 4/6] clk: qcom: camcc-sm7150: Specify Titan GDSC power domain as a parent to IPEx and BPS

[Imran Shaik]

On 9/11/2025 6:42 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM7150 camera clock controller, and it should include
> IPE0/1 and BPS ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>  drivers/clk/qcom/camcc-sm7150.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>

Thanks,
Imran

Re: [PATCH 5/6] clk: qcom: camcc-sm8250: Specify Titan GDSC power domain as a parent to IPE/BPS/SBI

[Imran Shaik]

On 9/11/2025 6:42 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM8250 camera clock controller, and it should include
> IPE, BPS and SBI ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>  drivers/clk/qcom/camcc-sm8250.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>

Thanks,
Imran

Re: [PATCH 6/6] clk: qcom: camcc-sm8450: Specify Titan GDSC power domain as a parent to IPE/BPS/SBI

[Imran Shaik]

On 9/11/2025 6:42 AM, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SD8450 camera clock controller, and it should include
> IPE, BPS and SBI ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>  drivers/clk/qcom/camcc-sm8450.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>

Thanks,
Imran

Re: [PATCH 2/6] clk: qcom: camcc-sm6350: Specify Titan GDSC power domain as a parent to other

[Luca Weiss]

Hi Vladimir,

On Thu Sep 11, 2025 at 3:12 AM CEST, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM6350 camera clock controller to enforce a correct
> sequence of enabling and disabling power domains by the consumers.

Thanks, I've had something like this in my camera branch for a while,
but since I've had enough other problems with clocks/PDs there or camss
not working fully yet, I haven't bothered to upstream it.

Thanks!

Regards
Luca

>
> Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350")
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>  drivers/clk/qcom/camcc-sm6350.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c
> index 8aac97d29ce3..6c272f7b0721 100644
> --- a/drivers/clk/qcom/camcc-sm6350.c
> +++ b/drivers/clk/qcom/camcc-sm6350.c
> @@ -1693,6 +1693,8 @@ static struct clk_branch camcc_sys_tmr_clk = {
>  	},
>  };
>  
> +static struct gdsc titan_top_gdsc;
> +
>  static struct gdsc bps_gdsc = {
>  	.gdscr = 0x6004,
>  	.en_rest_wait_val = 0x2,
> @@ -1702,6 +1704,7 @@ static struct gdsc bps_gdsc = {
>  		.name = "bps_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &titan_top_gdsc.pd,
>  	.flags = VOTABLE,
>  };
>  
> @@ -1714,6 +1717,7 @@ static struct gdsc ipe_0_gdsc = {
>  		.name = "ipe_0_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &titan_top_gdsc.pd,
>  	.flags = VOTABLE,
>  };
>  
> @@ -1726,6 +1730,7 @@ static struct gdsc ife_0_gdsc = {
>  		.name = "ife_0_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &titan_top_gdsc.pd,
>  };
>  
>  static struct gdsc ife_1_gdsc = {
> @@ -1737,6 +1742,7 @@ static struct gdsc ife_1_gdsc = {
>  		.name = "ife_1_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &titan_top_gdsc.pd,
>  };
>  
>  static struct gdsc ife_2_gdsc = {
> @@ -1748,6 +1754,7 @@ static struct gdsc ife_2_gdsc = {
>  		.name = "ife_2_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &titan_top_gdsc.pd,
>  };
>  
>  static struct gdsc titan_top_gdsc = {

Re: [PATCH 1/6] clk: qcom: camcc-sm8550: Specify Titan GDSC power domain as a parent to other

[Bjorn Andersson]

On Thu, Sep 11, 2025 at 04:12:13AM +0300, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM8550 camera clock controller to enforce a correct
> sequence of enabling and disabling power domains by the consumers.
> 

I don't understand which problem you're solving.

Are these GDSCs children of the titan_top and your patch is describing
that so that when a client is enabling any one of them they will be
enabled in order?

Are you correcting the description of the hardware? Or is this a hack to
trick the system into performing the operations in order?


Please start your commit message with a problem description, then a
description of your solution.

https://docs.kernel.org/process/submitting-patches.html#describe-your-changes

Regards,
Bjorn

> Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550")
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>  drivers/clk/qcom/camcc-sm8550.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
> index 63aed9e4c362..b8ece8a57a8a 100644
> --- a/drivers/clk/qcom/camcc-sm8550.c
> +++ b/drivers/clk/qcom/camcc-sm8550.c
> @@ -3204,6 +3204,8 @@ static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
>  	},
>  };
>  
> +static struct gdsc cam_cc_titan_top_gdsc;
> +
>  static struct gdsc cam_cc_bps_gdsc = {
>  	.gdscr = 0x10004,
>  	.en_rest_wait_val = 0x2,
> @@ -3213,6 +3215,7 @@ static struct gdsc cam_cc_bps_gdsc = {
>  		.name = "cam_cc_bps_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>  	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>  };
>  
> @@ -3225,6 +3228,7 @@ static struct gdsc cam_cc_ife_0_gdsc = {
>  		.name = "cam_cc_ife_0_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>  	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>  };
>  
> @@ -3237,6 +3241,7 @@ static struct gdsc cam_cc_ife_1_gdsc = {
>  		.name = "cam_cc_ife_1_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>  	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>  };
>  
> @@ -3249,6 +3254,7 @@ static struct gdsc cam_cc_ife_2_gdsc = {
>  		.name = "cam_cc_ife_2_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>  	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>  };
>  
> @@ -3261,6 +3267,7 @@ static struct gdsc cam_cc_ipe_0_gdsc = {
>  		.name = "cam_cc_ipe_0_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>  	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>  };
>  
> @@ -3273,6 +3280,7 @@ static struct gdsc cam_cc_sbi_gdsc = {
>  		.name = "cam_cc_sbi_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>  	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>  };
>  
> @@ -3285,6 +3293,7 @@ static struct gdsc cam_cc_sfe_0_gdsc = {
>  		.name = "cam_cc_sfe_0_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>  	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>  };
>  
> @@ -3297,6 +3306,7 @@ static struct gdsc cam_cc_sfe_1_gdsc = {
>  		.name = "cam_cc_sfe_1_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>  	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>  };
>  
> -- 
> 2.49.0
> 

Re: [PATCH 1/6] clk: qcom: camcc-sm8550: Specify Titan GDSC power domain as a parent to other

[Vladimir Zapolskiy]

On 9/12/25 05:09, Bjorn Andersson wrote:
> On Thu, Sep 11, 2025 at 04:12:13AM +0300, Vladimir Zapolskiy wrote:
>> Make Titan GDSC power domain as a parent of all other GDSC power domains
>> provided by the SM8550 camera clock controller to enforce a correct
>> sequence of enabling and disabling power domains by the consumers.
>>
> 
> I don't understand which problem you're solving.
> 
> Are these GDSCs children of the titan_top and your patch is describing
> that so that when a client is enabling any one of them they will be
> enabled in order?
> 
> Are you correcting the description of the hardware? Or is this a hack to
> trick the system into performing the operations in order?
> 

Consumers of power domains are unaware of power domain hierarhy, same
with clocks for instance.

When a consumer turns on/off a power domain dependant on another one,
the parent power domain shall be turned on/off, and it shall be done
by the power domain provider (camcc in this case), if the power domain
hierarchy is set. The changes in the series establish the hierarchy,
otherwise the CAMSS driver as a CAMCC consumer is irrecoverably broken.

> 
> Please start your commit message with a problem description, then a
> description of your solution.
> 
> https://docs.kernel.org/process/submitting-patches.html#describe-your-changes
> 

I've started from "describe your changes in imperative mood" section,
I'll resend the changes with the reformulated commit messages, thank
you for review.

>> Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550")
>> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
>> ---
>>   drivers/clk/qcom/camcc-sm8550.c | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
>> index 63aed9e4c362..b8ece8a57a8a 100644
>> --- a/drivers/clk/qcom/camcc-sm8550.c
>> +++ b/drivers/clk/qcom/camcc-sm8550.c
>> @@ -3204,6 +3204,8 @@ static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
>>   	},
>>   };
>>   
>> +static struct gdsc cam_cc_titan_top_gdsc;
>> +
>>   static struct gdsc cam_cc_bps_gdsc = {
>>   	.gdscr = 0x10004,
>>   	.en_rest_wait_val = 0x2,
>> @@ -3213,6 +3215,7 @@ static struct gdsc cam_cc_bps_gdsc = {
>>   		.name = "cam_cc_bps_gdsc",
>>   	},
>>   	.pwrsts = PWRSTS_OFF_ON,
>> +	.parent = &cam_cc_titan_top_gdsc.pd,
>>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>>   };
>>   
>> @@ -3225,6 +3228,7 @@ static struct gdsc cam_cc_ife_0_gdsc = {
>>   		.name = "cam_cc_ife_0_gdsc",
>>   	},
>>   	.pwrsts = PWRSTS_OFF_ON,
>> +	.parent = &cam_cc_titan_top_gdsc.pd,
>>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>>   };
>>   
>> @@ -3237,6 +3241,7 @@ static struct gdsc cam_cc_ife_1_gdsc = {
>>   		.name = "cam_cc_ife_1_gdsc",
>>   	},
>>   	.pwrsts = PWRSTS_OFF_ON,
>> +	.parent = &cam_cc_titan_top_gdsc.pd,
>>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>>   };
>>   
>> @@ -3249,6 +3254,7 @@ static struct gdsc cam_cc_ife_2_gdsc = {
>>   		.name = "cam_cc_ife_2_gdsc",
>>   	},
>>   	.pwrsts = PWRSTS_OFF_ON,
>> +	.parent = &cam_cc_titan_top_gdsc.pd,
>>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>>   };
>>   
>> @@ -3261,6 +3267,7 @@ static struct gdsc cam_cc_ipe_0_gdsc = {
>>   		.name = "cam_cc_ipe_0_gdsc",
>>   	},
>>   	.pwrsts = PWRSTS_OFF_ON,
>> +	.parent = &cam_cc_titan_top_gdsc.pd,
>>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>>   };
>>   
>> @@ -3273,6 +3280,7 @@ static struct gdsc cam_cc_sbi_gdsc = {
>>   		.name = "cam_cc_sbi_gdsc",
>>   	},
>>   	.pwrsts = PWRSTS_OFF_ON,
>> +	.parent = &cam_cc_titan_top_gdsc.pd,
>>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>>   };
>>   
>> @@ -3285,6 +3293,7 @@ static struct gdsc cam_cc_sfe_0_gdsc = {
>>   		.name = "cam_cc_sfe_0_gdsc",
>>   	},
>>   	.pwrsts = PWRSTS_OFF_ON,
>> +	.parent = &cam_cc_titan_top_gdsc.pd,
>>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>>   };
>>   
>> @@ -3297,6 +3306,7 @@ static struct gdsc cam_cc_sfe_1_gdsc = {
>>   		.name = "cam_cc_sfe_1_gdsc",
>>   	},
>>   	.pwrsts = PWRSTS_OFF_ON,
>> +	.parent = &cam_cc_titan_top_gdsc.pd,
>>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>>   };
>>   
>> -- 
>> 2.49.0
>>

-- 
Best wishes,
Vladimir

Re: [PATCH 1/6] clk: qcom: camcc-sm8550: Specify Titan GDSC power domain as a parent to other

[Bryan O'Donoghue]

On 11/09/2025 02:12, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM8550 camera clock controller to enforce a correct
> sequence of enabling and disabling power domains by the consumers.

Suggest:

Titan GDSC is the parent power domain of all other GDSCs in the CAMCC 
block. Mark it as such.

> Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550")
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>   drivers/clk/qcom/camcc-sm8550.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
> index 63aed9e4c362..b8ece8a57a8a 100644
> --- a/drivers/clk/qcom/camcc-sm8550.c
> +++ b/drivers/clk/qcom/camcc-sm8550.c
> @@ -3204,6 +3204,8 @@ static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
>   	},
>   };
> 
> +static struct gdsc cam_cc_titan_top_gdsc;
> +
>   static struct gdsc cam_cc_bps_gdsc = {
>   	.gdscr = 0x10004,
>   	.en_rest_wait_val = 0x2,
> @@ -3213,6 +3215,7 @@ static struct gdsc cam_cc_bps_gdsc = {
>   		.name = "cam_cc_bps_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>   };
> 
> @@ -3225,6 +3228,7 @@ static struct gdsc cam_cc_ife_0_gdsc = {
>   		.name = "cam_cc_ife_0_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>   };
> 
> @@ -3237,6 +3241,7 @@ static struct gdsc cam_cc_ife_1_gdsc = {
>   		.name = "cam_cc_ife_1_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>   };
> 
> @@ -3249,6 +3254,7 @@ static struct gdsc cam_cc_ife_2_gdsc = {
>   		.name = "cam_cc_ife_2_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>   };
> 
> @@ -3261,6 +3267,7 @@ static struct gdsc cam_cc_ipe_0_gdsc = {
>   		.name = "cam_cc_ipe_0_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>   };
> 
> @@ -3273,6 +3280,7 @@ static struct gdsc cam_cc_sbi_gdsc = {
>   		.name = "cam_cc_sbi_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>   };
> 
> @@ -3285,6 +3293,7 @@ static struct gdsc cam_cc_sfe_0_gdsc = {
>   		.name = "cam_cc_sfe_0_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>   };
> 
> @@ -3297,6 +3306,7 @@ static struct gdsc cam_cc_sfe_1_gdsc = {
>   		.name = "cam_cc_sfe_1_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &cam_cc_titan_top_gdsc.pd,
>   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>   };
> 
> --
> 2.49.0
> 
> 

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Re: [PATCH 2/6] clk: qcom: camcc-sm6350: Specify Titan GDSC power domain as a parent to other

[Bryan O'Donoghue]

On 11/09/2025 02:12, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM6350 camera clock controller to enforce a correct
> sequence of enabling and disabling power domains by the consumers.
> 
> Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for SM6350")
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>   drivers/clk/qcom/camcc-sm6350.c | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c
> index 8aac97d29ce3..6c272f7b0721 100644
> --- a/drivers/clk/qcom/camcc-sm6350.c
> +++ b/drivers/clk/qcom/camcc-sm6350.c
> @@ -1693,6 +1693,8 @@ static struct clk_branch camcc_sys_tmr_clk = {
>   	},
>   };
> 
> +static struct gdsc titan_top_gdsc;
> +
>   static struct gdsc bps_gdsc = {
>   	.gdscr = 0x6004,
>   	.en_rest_wait_val = 0x2,
> @@ -1702,6 +1704,7 @@ static struct gdsc bps_gdsc = {
>   		.name = "bps_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &titan_top_gdsc.pd,
>   	.flags = VOTABLE,
>   };
> 
> @@ -1714,6 +1717,7 @@ static struct gdsc ipe_0_gdsc = {
>   		.name = "ipe_0_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &titan_top_gdsc.pd,
>   	.flags = VOTABLE,
>   };
> 
> @@ -1726,6 +1730,7 @@ static struct gdsc ife_0_gdsc = {
>   		.name = "ife_0_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &titan_top_gdsc.pd,
>   };
> 
>   static struct gdsc ife_1_gdsc = {
> @@ -1737,6 +1742,7 @@ static struct gdsc ife_1_gdsc = {
>   		.name = "ife_1_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &titan_top_gdsc.pd,
>   };
> 
>   static struct gdsc ife_2_gdsc = {
> @@ -1748,6 +1754,7 @@ static struct gdsc ife_2_gdsc = {
>   		.name = "ife_2_gdsc",
>   	},
>   	.pwrsts = PWRSTS_OFF_ON,
> +	.parent = &titan_top_gdsc.pd,
>   };
> 
>   static struct gdsc titan_top_gdsc = {
> --
> 2.49.0
> 
> 

Please fix up the commit log.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Re: [PATCH 3/6] clk: qcom: camcc-sdm845: Specify Titan GDSC power domain as a parent to other

[Bryan O'Donoghue]

On 11/09/2025 02:12, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SDM845 camera clock controller, and it should include
> IPE0/1 and BPS ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>   drivers/clk/qcom/camcc-sdm845.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
> index cf60e8dd292a..fb313da7165b 100644
> --- a/drivers/clk/qcom/camcc-sdm845.c
> +++ b/drivers/clk/qcom/camcc-sdm845.c
> @@ -1543,6 +1543,7 @@ static struct gdsc bps_gdsc = {
>   		.name = "bps_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -1552,6 +1553,7 @@ static struct gdsc ipe_0_gdsc = {
>   		.name = "ipe_0_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -1561,6 +1563,7 @@ static struct gdsc ipe_1_gdsc = {
>   		.name = "ipe_1_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> --
> 2.49.0
> 
> 
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Re: [PATCH 4/6] clk: qcom: camcc-sm7150: Specify Titan GDSC power domain as a parent to IPEx and BPS

[Bryan O'Donoghue]

On 11/09/2025 02:12, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM7150 camera clock controller, and it should include
> IPE0/1 and BPS ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>   drivers/clk/qcom/camcc-sm7150.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/qcom/camcc-sm7150.c b/drivers/clk/qcom/camcc-sm7150.c
> index 4a3baf5d8e85..0e072ae39ec0 100644
> --- a/drivers/clk/qcom/camcc-sm7150.c
> +++ b/drivers/clk/qcom/camcc-sm7150.c
> @@ -1846,6 +1846,7 @@ static struct gdsc camcc_bps_gdsc = {
>   		.name = "camcc_bps_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &camcc_titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -1875,6 +1876,7 @@ static struct gdsc camcc_ipe_0_gdsc = {
>   		.name = "camcc_ipe_0_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &camcc_titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -1884,6 +1886,7 @@ static struct gdsc camcc_ipe_1_gdsc = {
>   		.name = "camcc_ipe_1_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &camcc_titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> --
> 2.49.0
> 
> 
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

Re: [PATCH 3/6] clk: qcom: camcc-sdm845: Specify Titan GDSC power domain as a parent to other

[Bryan O'Donoghue]

On 11/09/2025 02:12, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SDM845 camera clock controller, and it should include
> IPE0/1 and BPS ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>   drivers/clk/qcom/camcc-sdm845.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
> index cf60e8dd292a..fb313da7165b 100644
> --- a/drivers/clk/qcom/camcc-sdm845.c
> +++ b/drivers/clk/qcom/camcc-sdm845.c
> @@ -1543,6 +1543,7 @@ static struct gdsc bps_gdsc = {
>   		.name = "bps_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -1552,6 +1553,7 @@ static struct gdsc ipe_0_gdsc = {
>   		.name = "ipe_0_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -1561,6 +1563,7 @@ static struct gdsc ipe_1_gdsc = {
>   		.name = "ipe_1_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> --
> 2.49.0
> 
> 

Please apply a Fixes: tag
Cc: stable@vger.kernel.org

---
bod

Re: [PATCH 4/6] clk: qcom: camcc-sm7150: Specify Titan GDSC power domain as a parent to IPEx and BPS

[Bryan O'Donoghue]

On 11/09/2025 02:12, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM7150 camera clock controller, and it should include
> IPE0/1 and BPS ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>   drivers/clk/qcom/camcc-sm7150.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/qcom/camcc-sm7150.c b/drivers/clk/qcom/camcc-sm7150.c
> index 4a3baf5d8e85..0e072ae39ec0 100644
> --- a/drivers/clk/qcom/camcc-sm7150.c
> +++ b/drivers/clk/qcom/camcc-sm7150.c
> @@ -1846,6 +1846,7 @@ static struct gdsc camcc_bps_gdsc = {
>   		.name = "camcc_bps_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &camcc_titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -1875,6 +1876,7 @@ static struct gdsc camcc_ipe_0_gdsc = {
>   		.name = "camcc_ipe_0_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &camcc_titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -1884,6 +1886,7 @@ static struct gdsc camcc_ipe_1_gdsc = {
>   		.name = "camcc_ipe_1_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &camcc_titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> --
> 2.49.0
> 
> 
Please apply a Fixes: tag
Cc: stable@vger.kernel.org

---
bod

Re: [PATCH 5/6] clk: qcom: camcc-sm8250: Specify Titan GDSC power domain as a parent to IPE/BPS/SBI

[Bryan O'Donoghue]

On 11/09/2025 02:12, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SM8250 camera clock controller, and it should include
> IPE, BPS and SBI ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>   drivers/clk/qcom/camcc-sm8250.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c
> index 6da89c49ba3d..c95a00628630 100644
> --- a/drivers/clk/qcom/camcc-sm8250.c
> +++ b/drivers/clk/qcom/camcc-sm8250.c
> @@ -2213,6 +2213,7 @@ static struct gdsc bps_gdsc = {
>   		.name = "bps_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -2222,6 +2223,7 @@ static struct gdsc ipe_0_gdsc = {
>   		.name = "ipe_0_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -2231,6 +2233,7 @@ static struct gdsc sbi_gdsc = {
>   		.name = "sbi_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> --
> 2.49.0
> 
> 

Please fix the commit log per Bjorn's feedback

Apply a Fixes: tag
Cc: stable@vger.kernel.org

Then you may add

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
bod

Re: [PATCH 6/6] clk: qcom: camcc-sm8450: Specify Titan GDSC power domain as a parent to IPE/BPS/SBI

[Bryan O'Donoghue]

On 11/09/2025 02:12, Vladimir Zapolskiy wrote:
> Make Titan GDSC power domain as a parent of all other GDSC power domains
> provided by the SD8450 camera clock controller, and it should include
> IPE, BPS and SBI ones, even if there are no users of them currently.
> 
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
>   drivers/clk/qcom/camcc-sm8450.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c
> index 4dd8be8cc988..ef8cf54d0eed 100644
> --- a/drivers/clk/qcom/camcc-sm8450.c
> +++ b/drivers/clk/qcom/camcc-sm8450.c
> @@ -2935,6 +2935,7 @@ static struct gdsc bps_gdsc = {
>   		.name = "bps_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -2944,6 +2945,7 @@ static struct gdsc ipe_0_gdsc = {
>   		.name = "ipe_0_gdsc",
>   	},
>   	.flags = HW_CTRL | POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> @@ -2953,6 +2955,7 @@ static struct gdsc sbi_gdsc = {
>   		.name = "sbi_gdsc",
>   	},
>   	.flags = POLL_CFG_GDSCR,
> +	.parent = &titan_top_gdsc.pd,
>   	.pwrsts = PWRSTS_OFF_ON,
>   };
> 
> --
> 2.49.0
> 
> 

Please fix the commit log per Bjorn's feedback, I've given a commit log 
you might want to use.

Apply a Fixes: tag
Cc: stable@vger.kernel.org

Then you may add

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

---
bod

Re: [PATCH 1/6] clk: qcom: camcc-sm8550: Specify Titan GDSC power domain as a parent to other

[Bjorn Andersson]

On Fri, Sep 12, 2025 at 09:23:00AM +0300, Vladimir Zapolskiy wrote:
> On 9/12/25 05:09, Bjorn Andersson wrote:
> > On Thu, Sep 11, 2025 at 04:12:13AM +0300, Vladimir Zapolskiy wrote:
> > > Make Titan GDSC power domain as a parent of all other GDSC power domains
> > > provided by the SM8550 camera clock controller to enforce a correct
> > > sequence of enabling and disabling power domains by the consumers.
> > > 
> > 
> > I don't understand which problem you're solving.
> > 
> > Are these GDSCs children of the titan_top and your patch is describing
> > that so that when a client is enabling any one of them they will be
> > enabled in order?
> > 
> > Are you correcting the description of the hardware? Or is this a hack to
> > trick the system into performing the operations in order?
> > 
> 
> Consumers of power domains are unaware of power domain hierarhy, same
> with clocks for instance.
> 

There are several valid cases where this might not be true.

> When a consumer turns on/off a power domain dependant on another one,
> the parent power domain shall be turned on/off, and it shall be done
> by the power domain provider (camcc in this case), if the power domain
> hierarchy is set. The changes in the series establish the hierarchy,
> otherwise the CAMSS driver as a CAMCC consumer is irrecoverably broken.
> 

Excellent, here you're saying "X is parent of Y, this needs to be
described in software". This is completely different from the original
"let's just make X parent of Y".

> > 
> > Please start your commit message with a problem description, then a
> > description of your solution.
> > 
> > https://docs.kernel.org/process/submitting-patches.html#describe-your-changes
> > 
> 
> I've started from "describe your changes in imperative mood" section,

The 7 paragraphs leading up to that are important as well ;)

Looking forward to v2.

Regards,
Bjorn

> I'll resend the changes with the reformulated commit messages, thank
> you for review.
> 
> > > Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550")
> > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> > > ---
> > >   drivers/clk/qcom/camcc-sm8550.c | 10 ++++++++++
> > >   1 file changed, 10 insertions(+)
> > > 
> > > diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
> > > index 63aed9e4c362..b8ece8a57a8a 100644
> > > --- a/drivers/clk/qcom/camcc-sm8550.c
> > > +++ b/drivers/clk/qcom/camcc-sm8550.c
> > > @@ -3204,6 +3204,8 @@ static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
> > >   	},
> > >   };
> > > +static struct gdsc cam_cc_titan_top_gdsc;
> > > +
> > >   static struct gdsc cam_cc_bps_gdsc = {
> > >   	.gdscr = 0x10004,
> > >   	.en_rest_wait_val = 0x2,
> > > @@ -3213,6 +3215,7 @@ static struct gdsc cam_cc_bps_gdsc = {
> > >   		.name = "cam_cc_bps_gdsc",
> > >   	},
> > >   	.pwrsts = PWRSTS_OFF_ON,
> > > +	.parent = &cam_cc_titan_top_gdsc.pd,
> > >   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
> > >   };
> > > @@ -3225,6 +3228,7 @@ static struct gdsc cam_cc_ife_0_gdsc = {
> > >   		.name = "cam_cc_ife_0_gdsc",
> > >   	},
> > >   	.pwrsts = PWRSTS_OFF_ON,
> > > +	.parent = &cam_cc_titan_top_gdsc.pd,
> > >   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
> > >   };
> > > @@ -3237,6 +3241,7 @@ static struct gdsc cam_cc_ife_1_gdsc = {
> > >   		.name = "cam_cc_ife_1_gdsc",
> > >   	},
> > >   	.pwrsts = PWRSTS_OFF_ON,
> > > +	.parent = &cam_cc_titan_top_gdsc.pd,
> > >   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
> > >   };
> > > @@ -3249,6 +3254,7 @@ static struct gdsc cam_cc_ife_2_gdsc = {
> > >   		.name = "cam_cc_ife_2_gdsc",
> > >   	},
> > >   	.pwrsts = PWRSTS_OFF_ON,
> > > +	.parent = &cam_cc_titan_top_gdsc.pd,
> > >   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
> > >   };
> > > @@ -3261,6 +3267,7 @@ static struct gdsc cam_cc_ipe_0_gdsc = {
> > >   		.name = "cam_cc_ipe_0_gdsc",
> > >   	},
> > >   	.pwrsts = PWRSTS_OFF_ON,
> > > +	.parent = &cam_cc_titan_top_gdsc.pd,
> > >   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
> > >   };
> > > @@ -3273,6 +3280,7 @@ static struct gdsc cam_cc_sbi_gdsc = {
> > >   		.name = "cam_cc_sbi_gdsc",
> > >   	},
> > >   	.pwrsts = PWRSTS_OFF_ON,
> > > +	.parent = &cam_cc_titan_top_gdsc.pd,
> > >   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
> > >   };
> > > @@ -3285,6 +3293,7 @@ static struct gdsc cam_cc_sfe_0_gdsc = {
> > >   		.name = "cam_cc_sfe_0_gdsc",
> > >   	},
> > >   	.pwrsts = PWRSTS_OFF_ON,
> > > +	.parent = &cam_cc_titan_top_gdsc.pd,
> > >   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
> > >   };
> > > @@ -3297,6 +3306,7 @@ static struct gdsc cam_cc_sfe_1_gdsc = {
> > >   		.name = "cam_cc_sfe_1_gdsc",
> > >   	},
> > >   	.pwrsts = PWRSTS_OFF_ON,
> > > +	.parent = &cam_cc_titan_top_gdsc.pd,
> > >   	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
> > >   };
> > > -- 
> > > 2.49.0
> > > 
> 
> -- 
> Best wishes,
> Vladimir