From: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
To: Taniya Das <taniya.das@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Abel Vesa <abelvesa@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Ajit Pandey <ajit.pandey@oss.qualcomm.com>,
Imran Shaik <imran.shaik@oss.qualcomm.com>,
Shawn Guo <shengchao.guo@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: qcom: camcc-nord: Correct camera clock source tables
Date: Mon, 28 Sep 2026 13:43:50 +0530 [thread overview]
Message-ID: <553b2e77-d646-423a-9a80-4d0ae539b919@oss.qualcomm.com> (raw)
In-Reply-To: <20260927-fix_camcc-v1-1-9fe956f01f6d@oss.qualcomm.com>
On 9/27/2026 12:07 AM, Taniya Das wrote:
> Select the PLL0 odd output for the 200 MHz and 400 MHz CAMNOC RT
> AXI rates. Use PLL0 main output dividers for the 300 MHz and 400 MHz
> CPHY RX rates.
>
> CSID and IFE Lite use the CPHY RX rates, so share that table rather
> than duplicating it. Remove the unsupported 300 MHz CSI PHY timer
> rate.
>
> Fixes: 7647815dfc8f ("clk: qcom: camcc: Add support for camera clock controller for Nord")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---
> drivers/clk/qcom/camcc-nord.c | 22 +++++++---------------
> 1 file changed, 7 insertions(+), 15 deletions(-)
>
Reviewed-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
prev parent reply other threads:[~2026-09-28 8:13 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-26 18:37 [PATCH] clk: qcom: camcc-nord: Correct camera clock source tables Taniya Das
2026-09-28 7:55 ` Abel Vesa
2026-09-28 8:13 ` Jagadeesh Kona [this message]
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