[PATCH 0/2] clk: qcom: gcc: Update the force_mem_core for UFS ICE

[PATCH 0/2] clk: qcom: gcc: Update the force_mem_core for UFS ICE

[Taniya Das]

The MCQ feature of UFS requires the both UFS ice and UFS phy axi clocks
to have the force_mem_core bit set to allow retention after power
collapse.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
Taniya Das (2):
      clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
      clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks

 drivers/clk/qcom/gcc-sm8650.c   | 2 ++
 drivers/clk/qcom/gcc-sm8750.c   | 3 ++-
 drivers/clk/qcom/gcc-x1e80100.c | 4 ++++
 3 files changed, 8 insertions(+), 1 deletion(-)
---
base-commit: 01c6df60d5d4ae00cd5c1648818744838bba7763
change-id: 20250414-gcc_ufs_mem_core-7bb28a3527ec

Best regards,
-- 
Taniya Das <quic_tdas@quicinc.com>

[PATCH 1/2] clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750

[Taniya Das]

Update the force mem core bit for UFS AXI clock to force the core on
signal to remain active during halt state of the clk. If force mem
core bit of the clock is not set, the memories of the subsystem will
not retain the logic across power states. This is required for the MCQ
feature of the UFS driver.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 drivers/clk/qcom/gcc-sm8650.c | 2 ++
 drivers/clk/qcom/gcc-sm8750.c | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c
index fa1672c4e7d814e1e08c79f9cda9463bf1cd1598..24f98062b9dd50f8397dab8392fff45051ab3665 100644
--- a/drivers/clk/qcom/gcc-sm8650.c
+++ b/drivers/clk/qcom/gcc-sm8650.c
@@ -3817,7 +3817,9 @@ static int gcc_sm8650_probe(struct platform_device *pdev)
 	qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
 	qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
 
+	/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
 	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
 
 	/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
 	regmap_write(regmap, 0x52150, 0x0);
diff --git a/drivers/clk/qcom/gcc-sm8750.c b/drivers/clk/qcom/gcc-sm8750.c
index b36d70976095834ae4f7936d83f228d81b2c31e8..8092dd6b37b56f4fd786e33d4f0e8aabcd6ecdfe 100644
--- a/drivers/clk/qcom/gcc-sm8750.c
+++ b/drivers/clk/qcom/gcc-sm8750.c
@@ -3244,8 +3244,9 @@ static int gcc_sm8750_probe(struct platform_device *pdev)
 	regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20));
 	regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21));
 
-	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
+	/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
 	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
 
 	return qcom_cc_really_probe(&pdev->dev, &gcc_sm8750_desc, regmap);
 }

-- 
2.48.1

Re: [PATCH 1/2] clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750

[Imran Shaik]

On 4/14/2025 2:30 PM, Taniya Das wrote:
> Update the force mem core bit for UFS AXI clock to force the core on
> signal to remain active during halt state of the clk. If force mem
> core bit of the clock is not set, the memories of the subsystem will
> not retain the logic across power states. This is required for the MCQ
> feature of the UFS driver.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  drivers/clk/qcom/gcc-sm8650.c | 2 ++
>  drivers/clk/qcom/gcc-sm8750.c | 3 ++-
>  2 files changed, 4 insertions(+), 1 deletion(-)
> 

Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>

Thanks,
Imran

[PATCH 2/2] clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks

[Taniya Das]

Update the force mem core bit for UFS ICE clock and UFS PHY AXI clock to
force the core on signal to remain active during halt state of the clk.
If force mem core bit of the clock is not set, the memories of the
subsystem will not retain the logic across power states. This is
required for the MCQ feature of UFS.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 drivers/clk/qcom/gcc-x1e80100.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index 009f39139b6440e80fca8f9474be86ca17d9775b..3e44757e25d3245e455918e9474c978c8dacaa5e 100644
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -6753,6 +6753,10 @@ static int gcc_x1e80100_probe(struct platform_device *pdev)
 	/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
 	regmap_write(regmap, 0x52224, 0x0);
 
+	/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
+	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
+
 	return qcom_cc_really_probe(&pdev->dev, &gcc_x1e80100_desc, regmap);
 }
 

-- 
2.48.1

Re: [PATCH 2/2] clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks

[Imran Shaik]

On 4/14/2025 2:30 PM, Taniya Das wrote:
> Update the force mem core bit for UFS ICE clock and UFS PHY AXI clock to
> force the core on signal to remain active during halt state of the clk.
> If force mem core bit of the clock is not set, the memories of the
> subsystem will not retain the logic across power states. This is
> required for the MCQ feature of UFS.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  drivers/clk/qcom/gcc-x1e80100.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>

Thanks,
Imran

Re: [PATCH 0/2] clk: qcom: gcc: Update the force_mem_core for UFS ICE

[Bjorn Andersson]

On Mon, 14 Apr 2025 14:30:39 +0530, Taniya Das wrote:
> The MCQ feature of UFS requires the both UFS ice and UFS phy axi clocks
> to have the force_mem_core bit set to allow retention after power
> collapse.
> 
> 

Applied, thanks!

[1/2] clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
      commit: da94a81ea6c6f1cd2f389c5631e33c145ac7b35b
[2/2] clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
      commit: 201bf08ba9e26eeb0a96ba3fd5c026f531b31aed

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>