[PATCH 0/8] clk: samsung: Introduce support for Exynos9610 clocks.

[PATCH 0/8] clk: samsung: Introduce support for Exynos9610 clocks.

[Alexandru Chimac]

This patchset adds partial support for clocks (no SHUB, USB, MIF0/1, ISP, 
VIPX1/2, MFC) on Exynos9610.

Signed-off-by: Alexandru Chimac <alex@chimac.ro>
---
Alexandru Chimac (8):
      dt-bindings: clock: samsung: Add Exynos9610 CMU bindings
      clk: samsung: clk-pll: Add support for pll_1061x
      clk: samsung: Introduce Exynos9610 clock controller driver
      arm64: dts: exynos9610: Enable clock support
      dt-bindings: soc: exynos-sysreg: Add Exynos9610 SYSREG bindings
      arm64: dts: exynos9610: Add SYSREG nodes
      arm64: dts: exynos9610: Assign clocks to existing nodes
      arm64: dts: exynos9610-gta4xl: Assign clocks to existing nodes

 .../bindings/clock/samsung,exynos9610-clock.yaml   |  344 ++
 .../soc/samsung/samsung,exynos-sysreg.yaml         |   20 +
 arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts   |    2 +
 arch/arm64/boot/dts/exynos/exynos9610.dtsi         |  277 ++
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-exynos9610.c               | 3652 ++++++++++++++++++++
 drivers/clk/samsung/clk-pll.c                      |   29 +-
 drivers/clk/samsung/clk-pll.h                      |    1 +
 include/dt-bindings/clock/samsung,exynos9610.h     |  720 ++++
 9 files changed, 5039 insertions(+), 7 deletions(-)
---
base-commit: 48c4c0b684f394721b7db809e1cc282fccdb33da
change-id: 20250914-exynos9610-clocks-2fba704e6030
prerequisite-message-id: <20250914-exynos9610-devicetree-v1-0-2000fc3bbe0b@chimac.ro>
prerequisite-patch-id: fb1e2f83c03a3b3a330c72d5d9c9fd8cd95ef2ce
prerequisite-patch-id: b42a7c0c72b1bfe33bb65fb911bf28e3e101fa55
prerequisite-patch-id: 4c5c21cf62e50db603fe4e2df17ee664ff0b243e
prerequisite-message-id: <20250914-exynos9610-pinctrl-v1-0-90eda0c8fa03@chimac.ro>
prerequisite-patch-id: 27e949ada132a43ba3dbf880af3e6168ec94eaf9
prerequisite-patch-id: f446d396d0258709db47aef69e68821eb72582dc
prerequisite-patch-id: e3bf016be9509ee79beb3d51907ef6cd58fb98b1

Best regards,
-- 
Alexandru Chimac <alex@chimac.ro>

[PATCH 1/8] dt-bindings: clock: samsung: Add Exynos9610 CMU bindings

[Alexandru Chimac]

This clock management unit has a topmost block (CMU_TOP)
that generates top clocks for other blocks, alongside 20
other blocks, out of which 11 are currently implemented.

Signed-off-by: Alexandru Chimac <alex@chimac.ro>
---
 .../bindings/clock/samsung,exynos9610-clock.yaml   | 344 ++++++++++
 include/dt-bindings/clock/samsung,exynos9610.h     | 720 +++++++++++++++++++++
 2 files changed, 1064 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos9610-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos9610-clock.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..f3b7bc49a6ab18c5dd3c54d1f5fcdb7a67d15668
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos9610-clock.yaml
@@ -0,0 +1,344 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos9610-clock.yaml
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos9610 SoC clock controller
+
+maintainers:
+  - Alexandru Chimac <alexchimac@protonmail.com>
+  - Chanwoo Choi <cw00.choi@samsung.com>
+  - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |
+  Exynos9610 clock controller is comprised of several CMU units, generating
+  clocks for different domains. Those CMU units are modeled as separate device
+  tree nodes, and might depend on each other. Root clocks in that clock tree are
+  three external clocks:: OSCCLK (26MHz), DLL_DCO (360MHz), OSCCLK_RCO (CMGP, 30MHz).
+  The external OSCCLK must be defined as fixed-rate clock in the device tree.
+
+  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs
+  and dividers; all other clocks of function blocks (other CMUs) are usually derived
+  from CMU_TOP.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros
+  in 'include/dt-bindings/clock/samsung,exynos9610.h'.
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos9610-cmu-top
+      - samsung,exynos9610-cmu-apm
+      - samsung,exynos9610-cmu-cam
+      - samsung,exynos9610-cmu-cmgp
+      - samsung,exynos9610-cmu-core
+      - samsung,exynos9610-cmu-cpucl0
+      - samsung,exynos9610-cmu-cpucl1
+      - samsung,exynos9610-cmu-dispaud
+      - samsung,exynos9610-cmu-fsys
+      - samsung,exynos9610-cmu-g2d
+      - samsung,exynos9610-cmu-g3d
+      - samsung,exynos9610-cmu-peri
+
+  clocks:
+    minItems: 1
+    maxItems: 7
+
+  clock-names:
+    minItems: 1
+    maxItems: 7
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-top
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-apm
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+            - description: External reference clock (360Mhz)
+            - description: CMU_APM bus clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dll_dco
+            - const: dout_cmu_apm_bus
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-cam
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+            - description: CMU_CAM bus clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_cmu_cam_bus
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-cmgp
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+            - description: External reference clock (30MHz)
+            - description: CMU_CMGP bus clock (from CMU_APM)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: oscclk_rco
+            - const: gout_cmu_cmgp_bus
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-core
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+            - description: CMU_CORE bus clock (from CMU_TOP)
+            - description: CMU_CORE CCI clock (from CMU_TOP)
+            - description: CMU_CORE G3D clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: gout_cmu_core_bus
+            - const: gout_cmu_core_cci
+            - const: gout_cmu_core_g3d
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-cpucl0
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+            - description: CMU_CPUCL0 debug clock (from CMU_TOP)
+            - description: CMU_CPUCL0 switch clock (from CMU_TOP)
+            - description: HPM clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_cmu_cpucl0_dbg
+            - const: dout_cmu_cpucl0_switch
+            - const: dout_cmu_hpm
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-cpucl1
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+            - description: CMU_CPUCL1 switch clock (from CMU_TOP)
+            - description: HPM clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_cmu_cpucl1_switch
+            - const: dout_cmu_hpm
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-dispaud
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+            - description: External reference clock (10Mhz)
+            - description: External reference clock (100Mhz)
+            - description: External reference clock (60Mhz)
+            - description: CMU_DISPAUD audio clock (from CMU_TOP)
+            - description: CMU_DISPAUD CPU clock (from CMU_TOP)
+            - description: CMU_DISPAUD display clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: ioclk_audiocdclk0
+            - const: ioclk_audiocdclk1
+            - const: tick_usb
+            - const: dout_cmu_dispaud_aud
+            - const: dout_cmu_dispaud_cpu
+            - const: dout_cmu_dispaud_disp
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-fsys
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+            - description: CMU_FSYS bus clock (from CMU_TOP)
+            - description: CMU_FSYS external MMC clock (from CMU_TOP)
+            - description: CMU_FSYS embedded MMC clock (from CMU_TOP)
+            - description: CMU_FSYS embedded UFS clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_cmu_fsys_bus
+            - const: dout_cmu_fsys_mmc_card
+            - const: dout_cmu_fsys_mmc_embd
+            - const: dout_cmu_fsys_ufs_embd
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-g2d
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+            - description: CMU_G2D G2D clock (from CMU_TOP)
+            - description: CMU_G2D MSCL clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_cmu_g2d_g2d
+            - const: dout_cmu_g2d_mscl
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-g3d
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+            - description: CMU_G3D switch clock (from CMU_TOP)
+            - description: HPM clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_cmu_g3d_switch
+            - const: dout_cmu_hpm
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos9610-cmu-peri
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26MHz)
+            - description: CMU_PERI bus clock (from CMU_TOP)
+            - description: CMU_PERI IP clock (from CMU_TOP)
+            - description: CMU_PERI UART clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_cmu_peri_bus
+            - const: dout_cmu_peri_ip
+            - const: dout_cmu_peri_uart
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - clock-names
+  - reg
+
+additionalProperties: false
+
+examples:
+  # Clock controller node for CMU_FSYS
+  - |
+    #include <dt-bindings/clock/samsung,exynos9610.h>
+
+    cmu_fsys: clock-controller@13400000 {
+        compatible = "samsung,exynos9610-cmu-fsys";
+        reg = <0x13400000 0x8000>;
+        #clock-cells = <1>
+
+        clocks = <&oscclk>,
+                 <&cmu_top CLK_DOUT_CMU_FSYS_BUS>,
+                 <&cmu_top CLK_DOUT_CMU_FSYS_MMC_CARD>,
+                 <&cmu_top CLK_DOUT_CMU_FSYS_MMC_EMBD>,
+                 <&cmu_top CLK_DOUT_CMU_FSYS_UFS_EMBD>,
+
+        clock-names = "oscclk",
+                      "dout_cmu_fsys_bus",
+                      "dout_cmu_fsys_mmc_card",
+                      "dout_cmu_fsys_mmc_embd",
+                      "dout_cmu_fsys_ufs_embd";
+    };
+...
diff --git a/include/dt-bindings/clock/samsung,exynos9610.h b/include/dt-bindings/clock/samsung,exynos9610.h
new file mode 100644
index 0000000000000000000000000000000000000000..047c35fd8bf133996aaa185f9c8e5457499e707e
--- /dev/null
+++ b/include/dt-bindings/clock/samsung,exynos9610.h
@@ -0,0 +1,720 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Device tree binding constants for Exynos9610 clocks
+ *
+ * Copyright (c) 2025, Alexandru Chimac <alex@chimac.ro>
+ */
+
+/* CMU_TOP PLLs */
+#define CLK_FOUT_SHARED0_PLL		1
+#define CLK_FOUT_SHARED1_PLL		2
+#define CLK_FOUT_MMC_PLL		3
+
+/* CMU_TOP muxes */
+#define CLK_MOUT_PLL_SHARED0		4
+#define CLK_MOUT_PLL_SHARED1		5
+#define CLK_MOUT_PLL_MMC		6
+#define CLK_MOUT_CMU_APM_BUS		7
+#define CLK_MOUT_CMU_CAM_BUS		8
+#define CLK_MOUT_CMU_CIS_CLK0		9
+#define CLK_MOUT_CMU_CIS_CLK1		10
+#define CLK_MOUT_CMU_CIS_CLK2		11
+#define CLK_MOUT_CMU_CIS_CLK3		12
+#define CLK_MOUT_CMU_CORE_BUS		13
+#define CLK_MOUT_CMU_CORE_CCI		14
+#define CLK_MOUT_CMU_CORE_G3D		15
+#define CLK_MOUT_CMU_CPUCL0_DBG		16
+#define CLK_MOUT_CMU_CPUCL0_SWITCH	17
+#define CLK_MOUT_CMU_CPUCL1_SWITCH	18
+#define CLK_MOUT_CMU_DISPAUD_AUD	19
+#define CLK_MOUT_CMU_DISPAUD_CPU	20
+#define CLK_MOUT_CMU_DISPAUD_DISP	21
+#define CLK_MOUT_CMU_FSYS_BUS		22
+#define CLK_MOUT_CMU_FSYS_MMC_CARD	23
+#define CLK_MOUT_CMU_FSYS_MMC_EMBD	24
+#define CLK_MOUT_CMU_FSYS_UFS_EMBD	25
+#define CLK_MOUT_CMU_G2D_G2D		26
+#define CLK_MOUT_CMU_G2D_MSCL		27
+#define CLK_MOUT_CMU_G3D_SWITCH		28
+#define CLK_MOUT_CMU_HPM		29
+#define CLK_MOUT_CMU_ISP_BUS		30
+#define CLK_MOUT_CMU_ISP_GDC		31
+#define CLK_MOUT_CMU_ISP_VRA		32
+#define CLK_MOUT_CMU_MFC_MFC		33
+#define CLK_MOUT_CMU_MFC_WFD		34
+#define CLK_MOUT_CMU_MIF_BUSP		35
+#define CLK_MOUT_CMU_MIF_SWITCH		36
+#define CLK_MOUT_CMU_PERI_BUS		37
+#define CLK_MOUT_CMU_PERI_IP		38
+#define CLK_MOUT_CMU_PERI_UART		39
+#define CLK_MOUT_CMU_USB_BUS		40
+#define CLK_MOUT_CMU_USB_DPGTC		41
+#define CLK_MOUT_CMU_USB_USB30DRD	42
+#define CLK_MOUT_CMU_VIPX1_BUS		43
+#define CLK_MOUT_CMU_VIPX2_BUS		44
+#define CLK_MOUT_CLK_CMU_CMUREF		45
+#define CLK_MOUT_CMU_CMUREF		46
+
+/* CMU_TOP dividers */
+#define CLK_DOUT_CMU_SHARED0_DIV2	47
+#define CLK_DOUT_CMU_SHARED0_DIV3	48
+#define CLK_DOUT_CMU_SHARED0_DIV4	49
+#define CLK_DOUT_CMU_SHARED1_DIV2	50
+#define CLK_DOUT_CMU_SHARED1_DIV3	51
+#define CLK_DOUT_CMU_SHARED1_DIV4	52
+#define CLK_DOUT_CMU_MMC_DIV2		53
+#define CLK_DOUT_AP2CP_SHARED0_PLL_CLK	54
+#define CLK_DOUT_AP2CP_SHARED1_PLL_CLK	55
+#define CLK_DOUT_CMU_APM_BUS		56
+#define CLK_DOUT_CMU_CAM_BUS		57
+#define CLK_DOUT_CMU_CIS_CLK0		58
+#define CLK_DOUT_CMU_CIS_CLK1		59
+#define CLK_DOUT_CMU_CIS_CLK2		60
+#define CLK_DOUT_CMU_CIS_CLK3		61
+#define CLK_DOUT_CMU_CORE_BUS		62
+#define CLK_DOUT_CMU_CORE_CCI		63
+#define CLK_DOUT_CMU_CORE_G3D		64
+#define CLK_DOUT_CMU_CPUCL0_DBG		65
+#define CLK_DOUT_CMU_CPUCL0_SWITCH	66
+#define CLK_DOUT_CMU_CPUCL1_SWITCH	67
+#define CLK_DOUT_CMU_DISPAUD_AUD	68
+#define CLK_DOUT_CMU_DISPAUD_CPU	69
+#define CLK_DOUT_CMU_DISPAUD_DISP	70
+#define CLK_DOUT_CMU_FSYS_BUS		71
+#define CLK_DOUT_CMU_FSYS_MMC_CARD	72
+#define CLK_DOUT_CMU_FSYS_MMC_EMBD	73
+#define CLK_DOUT_CMU_FSYS_UFS_EMBD	74
+#define CLK_DOUT_CMU_G2D_G2D		75
+#define CLK_DOUT_CMU_G2D_MSCL		76
+#define CLK_DOUT_CMU_G3D_SWITCH		77
+#define CLK_DOUT_CMU_HPM		78
+#define CLK_DOUT_CMU_ISP_BUS		79
+#define CLK_DOUT_CMU_ISP_GDC		80
+#define CLK_DOUT_CMU_ISP_VRA		81
+#define CLK_DOUT_CMU_MFD_MFC		82
+#define CLK_DOUT_CMU_MFD_WFD		83
+#define CLK_DOUT_CMU_MIF_BUSP		84
+#define CLK_DOUT_CMU_PERI_BUS		85
+#define CLK_DOUT_CMU_PERI_IP		86
+#define CLK_DOUT_CMU_PERI_UART		87
+#define CLK_DOUT_CMU_USB_BUS		88
+#define CLK_DOUT_CMU_USB_DPGTC		89
+#define CLK_DOUT_CMU_USB_USB30DRD	90
+#define CLK_DOUT_CMU_VIPX1_BUS		91
+#define CLK_DOUT_CMU_VIPX2_BUS		92
+#define CLK_DOUT_CLK_CMU_CMUREF		93
+#define CLK_DOUT_CMU_OTP		94
+
+/* CMU_TOP gates */
+#define CLK_GOUT_CMU_MIF_SWITCH		95
+#define CLK_GOUT_CLK_CMU_OTP_CLK	96
+#define CLK_GOUT_CMU_APM_BUS		97
+#define CLK_GOUT_CMU_CAM_BUS		98
+#define CLK_GOUT_CMU_CIS_CLK0		99
+#define CLK_GOUT_CMU_CIS_CLK1		100
+#define CLK_GOUT_CMU_CIS_CLK2		101
+#define CLK_GOUT_CMU_CIS_CLK3		102
+#define CLK_GOUT_CMU_CORE_BUS		103
+#define CLK_GOUT_CMU_CORE_CCI		104
+#define CLK_GOUT_CMU_CORE_G3D		105
+#define CLK_GOUT_CMU_CPUCL0_DBG		106
+#define CLK_GOUT_CMU_CPUCL0_SWITCH	107
+#define CLK_GOUT_CMU_CPUCL1_SWITCH	108
+#define CLK_GOUT_CMU_DISPAUD_AUD	109
+#define CLK_GOUT_CMU_DISPAUD_CPU	110
+#define CLK_GOUT_CMU_DISPAUD_DISP	111
+#define CLK_GOUT_CMU_FSYS_BUS		112
+#define CLK_GOUT_CMU_FSYS_MMC_CARD	113
+#define CLK_GOUT_CMU_FSYS_MMC_EMBD	114
+#define CLK_GOUT_CMU_FSYS_UFS_EMBD	115
+#define CLK_GOUT_CMU_G2D_G2D		116
+#define CLK_GOUT_CMU_G2D_MSCL		117
+#define CLK_GOUT_CMU_G3D_SWITCH		118
+#define CLK_GOUT_CMU_HPM		119
+#define CLK_GOUT_CMU_ISP_BUS		120
+#define CLK_GOUT_CMU_ISP_GDC		121
+#define CLK_GOUT_CMU_ISP_VRA		122
+#define CLK_GOUT_CMU_MFC_MFC		123
+#define CLK_GOUT_CMU_MFC_WFD		124
+#define CLK_GOUT_CMU_MIF_BUSP		125
+#define CLK_GOUT_CMU_MODEM_SHARED0	126
+#define CLK_GOUT_CMU_MODEM_SHARED1	127
+#define CLK_GOUT_CMU_PERI_BUS		128
+#define CLK_GOUT_CMU_PERI_IP		129
+#define CLK_GOUT_CMU_PERI_UART		130
+#define CLK_GOUT_CMU_USB_BUS		131
+#define CLK_GOUT_CMU_USB_DPGTC		132
+#define CLK_GOUT_CMU_USB_USB30DRD	133
+#define CLK_GOUT_CMU_VIPX1_BUS		134
+#define CLK_GOUT_CMU_VIPX2_BUS		135
+
+/* CMU_APM muxes */
+#define CLK_MOUT_PLL_APM_BUS_USER		1
+#define CLK_MOUT_PLL_DLL_USER			2
+#define CLK_MOUT_CMU_SHUB_BUS			3
+#define CLK_MOUT_CLK_APM_BUS			4
+
+/* CMU_APM dividers */
+#define CLK_DOUT_CMU_SHUB_BUS			5
+#define CLK_DOUT_CLK_APM_BUS			6
+
+/* CPU_APM gates */
+#define CLK_GOUT_CMU_CMGP_BUS			7
+#define CLK_GOUT_CLK_APM_CMU_PCLK		8
+#define CLK_GOUT_CLK_APM_OSCCLK_CLK		9
+#define CLK_GOUT_CLK_APM_OSCCLK_RCO_CLK		10
+#define CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK	11
+#define CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK	12
+#define CLK_GOUT_APM_APBIF_RTC_ALIVE_PCLK	12
+#define CLK_GOUT_APM_APBIF_TOP_RTC_ALIVE_PCLK	13
+#define CLK_GOUT_APM_GREBEINTEGRATION_HCLK	14
+#define CLK_GOUT_APM_INTMEM_ACLK		15
+#define CLK_GOUT_APM_INTMEM_PCLK		16
+#define CLK_GOUT_APM_LHM_AXI_P_GNSS_CLK		17
+#define CLK_GOUT_APM_LHM_AXI_P_CLK		18
+#define CLK_GOUT_APM_LHM_AXI_P_MODEM_CLK	19
+#define CLK_GOUT_APM_LHM_AXI_P_SHUB_CLK		20
+#define CLK_GOUT_APM_LHM_AXI_P_WLBT_CLK		21
+#define CLK_GOUT_APM_LHS_AXI_D_CLK		22
+#define CLK_GOUT_APM_LHS_AXI_LP_SHUB_CLK	23
+#define CLK_GOUT_APM_MAILBOX_AP2CP_PCLK		24
+#define CLK_GOUT_APM_MAILBOX_AP2CP_S_PCLK	25
+#define CLK_GOUT_APM_MAILBOX_AP2GNSS_PCLK	26
+#define CLK_GOUT_APM_MAILBOX_AP2SHUB_PCLK	27
+#define CLK_GOUT_APM_MAILBOX_AP2WLBT_PCLK	28
+#define CLK_GOUT_APM_MAILBOX_APM2AP_PCLK	29
+#define CLK_GOUT_APM_MAILBOX_APM2CP_PCLK	30
+#define CLK_GOUT_APM_MAILBOX_APM2GNSS_PCLK	31
+#define CLK_GOUT_APM_MAILBOX_APM2SHUB_PCLK	32
+#define CLK_GOUT_APM_MAILBOX_APM2WLBT_PCLK	33
+#define CLK_GOUT_APM_MAILBOX_CP2GNSS_PCLK	34
+#define CLK_GOUT_APM_MAILBOX_CP2SHUB_PCLK	35
+#define CLK_GOUT_APM_MAILBOX_CP2WLBT_PCLK	36
+#define CLK_GOUT_APM_MAILBOX_SHUB2GNSS_PCLK	37
+#define CLK_GOUT_APM_MAILBOX_SHUB2WLBT_PCLK	38
+#define CLK_GOUT_APM_MAILBOX_WLBT2ABOX_PCLK	39
+#define CLK_GOUT_APM_MAILBOX_WLBT2GNSS_PCLK	40
+#define CLK_GOUT_APM_PEM_CLK			41
+#define CLK_GOUT_APM_PGEN_LITE_CLK		42
+#define CLK_GOUT_APM_PMU_INTR_GEN_PCLK		43
+#define CLK_GOUT_APM_BUS_CLK			44
+#define CLK_GOUT_APM_GREBE_CLK			45
+#define CLK_GOUT_APM_SPEEDY_PCLK		46
+#define CLK_GOUT_APM_SYSREG_PCLK		47
+#define CLK_GOUT_APM_WDT_PCLK			48
+#define CLK_GOUT_APM_XIU_DP_ACLK		49
+
+/* CMU_CAM muxes */
+#define CLK_MOUT_PLL_CAM_BUS_USER			1
+
+/* CMU_CAM dividers */
+#define CLK_DIV_CLK_CAM_BUSP				2
+
+/* CMU_CAM gates */
+#define CLK_GAT_CLK_CAM_CMU_PCLK			3
+#define CLK_GAT_CLK_CAM_OSCCLK_CLK			4
+#define CLK_GOUT_CAM_BUSD				5
+#define CLK_GOUT_CAM_BTM_ACLK				6
+#define CLK_GOUT_CAM_BTM_PCLK				7
+#define CLK_GOUT_CAM_LHS_ATB_CAMISP_CLK			8
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_3AA			9
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS0		10
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS1		11
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS2		12
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS3		13
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_RDMA			14
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS0		15
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS1		16
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS2		17
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS3		18
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_PAFSTAT_CORE		19
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_PPMU_CAM		20
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_DMA			21
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_SMMU_CAM		22
+#define CLK_GOUT_CAM_IS6P10P0_ACLK_XIU_D_CAM		23
+#define CLK_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM0	24
+#define CLK_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM1	25
+#define CLK_GOUT_CAM_IS6P10P0_PCLK_PPMU_CAM		26
+#define CLK_GOUT_CAM_LHM_AXI_P_CLK			27
+#define CLK_GOUT_CAM_LHS_ACEL_D_CLK			28
+#define CLK_GOUT_CAM_BUSD_CLK				29
+#define CLK_GOUT_CAM_BUSP_CLK				30
+#define CLK_GOUT_CAM_SYSREG_PCLK			31
+
+/* CMU_CMGP muxes */
+#define CLK_MOUT_CLK_CMGP_ADC			0
+#define CLK_MOUT_CLK_CMGP_I2C			1
+#define CLK_MOUT_CLK_CMGP_USI00			2
+#define CLK_MOUT_CLK_CMGP_USI01			3
+#define CLK_MOUT_CLK_CMGP_USI02			4
+#define CLK_MOUT_CLK_CMGP_USI03			5
+#define CLK_MOUT_CLK_CMGP_USI04			6
+
+/* CMU_CMGP dividers */
+#define CLK_DOUT_CLK_CMGP_ADC			0
+#define CLK_DOUT_CLK_CMGP_I2C			1
+#define CLK_DOUT_CLK_CMGP_USI00			2
+#define CLK_DOUT_CLK_CMGP_USI01			3
+#define CLK_DOUT_CLK_CMGP_USI02			4
+#define CLK_DOUT_CLK_CMGP_USI03			5
+#define CLK_DOUT_CLK_CMGP_USI04			6
+
+/* CMU_CMGP gates */
+#define CLK_GOUT_CMGP_CMU_PCLK			7
+#define CLK_GOUT_CLK_CMGP_OSCCLK_RCO_CLK	8
+#define CLK_GOUT_CMGP_ADC_PCLK_S0		9
+#define CLK_GOUT_CMGP_ADC_PCLK_S1		10
+#define CLK_GOUT_CMGP_GPIO_PCLK			11
+#define CLK_GOUT_CMGP_I2C_CMGP00_IPCLK		12
+#define CLK_GOUT_CMGP_I2C_CMGP00_PCLK		13
+#define CLK_GOUT_CMGP_I2C_CMGP01_IPCLK		14
+#define CLK_GOUT_CMGP_I2C_CMGP01_PCLK		15
+#define CLK_GOUT_CMGP_I2C_CMGP02_IPCLK		16
+#define CLK_GOUT_CMGP_I2C_CMGP02_PCLK		17
+#define CLK_GOUT_CMGP_I2C_CMGP03_IPCLK		18
+#define CLK_GOUT_CMGP_I2C_CMGP03_PCLK		19
+#define CLK_GOUT_CMGP_I2C_CMGP04_IPCLK		20
+#define CLK_GOUT_CMGP_I2C_CMGP04_PCLK		21
+#define CLK_GOUT_CMGP_BUS_CLK			22
+#define CLK_GOUT_CMGP_I2C_CLK			23
+#define CLK_GOUT_CMGP_USI00_CLK			24
+#define CLK_GOUT_CMGP_USI01_CLK			25
+#define CLK_GOUT_CMGP_USI02_CLK			26
+#define CLK_GOUT_CMGP_USI03_CLK			27
+#define CLK_GOUT_CMGP_USI04_CLK			28
+#define CLK_GOUT_CMGP_SYSREG_CMGP2CP_PCLK	29
+#define CLK_GOUT_CMGP_SYSREG_CMGP2GNSS_PCLK	30
+#define CLK_GOUT_CMGP_SYSREG_CMGP2PMU_AP_PCLK	31
+#define CLK_GOUT_CMGP_SYSREG_CMGP2PMU_SHUB_PCLK	32
+#define CLK_GOUT_CMGP_SYSREG_CMGP2SHUB_PCLK	33
+#define CLK_GOUT_CMGP_SYSREG_CMGP2WLBT_PCLK	34
+#define CLK_GOUT_CMGP_SYSREG_PCLK		35
+#define CLK_GOUT_CMGP_USI_CMGP00_IPCLK		36
+#define CLK_GOUT_CMGP_USI_CMGP00_PCLK		37
+#define CLK_GOUT_CMGP_USI_CMGP01_IPCLK		38
+#define CLK_GOUT_CMGP_USI_CMGP01_PCLK		39
+#define CLK_GOUT_CMGP_USI_CMGP02_IPCLK		40
+#define CLK_GOUT_CMGP_USI_CMGP02_PCLK		41
+#define CLK_GOUT_CMGP_USI_CMGP03_IPCLK		42
+#define CLK_GOUT_CMGP_USI_CMGP03_PCLK		43
+#define CLK_GOUT_CMGP_USI_CMGP04_IPCLK		44
+#define CLK_GOUT_CMGP_USI_CMGP04_PCLK		45
+
+/* CMU_CORE muxes */
+#define CLK_MOUT_PLL_CORE_BUS_USER			1
+#define CLK_MOUT_PLL_CORE_CCI_USER			2
+#define CLK_MOUT_PLL_CORE_G3D_USER			3
+#define CLK_MOUT_CLK_CORE_GIC				4
+
+/* CMU_CORE dividers */
+#define CLK_DOUT_CLK_CORE_BUSP				5
+
+/* CMU_CORE gates */
+#define CLK_GOUT_CLK_CORE_CMU_PCLK			6
+#define CLK_GOUT_CORE_AD_APB_CCI_550_PCLKM		7
+#define CLK_GOUT_CORE_AD_APB_DIT_PCLKM			8
+#define CLK_GOUT_CORE_AD_APB_PDMA0_PCLKM		9
+#define CLK_GOUT_CORE_AD_APB_PGEN_PDMA_PCLKM		10
+#define CLK_GOUT_CORE_AD_APB_PPFW_MEM0_PCLKM		11
+#define CLK_GOUT_CORE_AD_APB_PPFW_MEM1_PCLKM		12
+#define CLK_GOUT_CORE_AD_APB_PPFW_PERI_PCLKM		13
+#define CLK_GOUT_CORE_AD_APB_SPDMA_PCLKM		14
+#define CLK_GOUT_CORE_AD_AXI_GIC_ACLKM			15
+#define CLK_GOUT_CORE_ASYNCSFR_WR_DMC0_PCLK		16
+#define CLK_GOUT_CORE_ASYNCSFR_WR_DMC1_PCLK		17
+#define CLK_GOUT_CORE_AXI_US_A40_64TO128_DIT_ACLK	18
+#define CLK_GOUT_CORE_BAAW_P_GNSS_PCLK			19
+#define CLK_GOUT_CORE_BAAW_P_MODEM_PCLK			20
+#define CLK_GOUT_CORE_BAAW_P_SHUB_PCLK			21
+#define CLK_GOUT_CORE_BAAW_P_WLBT_PCLK			22
+#define CLK_GOUT_CORE_CCI_550_ACLK			23
+#define CLK_GOUT_CORE_DIT_ICLKL2A			24
+#define CLK_GOUT_CORE_GIC400_AIHWACG_CLK		25
+#define CLK_GOUT_CORE_LHM_ACEL_D0_ISP_CLK		26
+#define CLK_GOUT_CORE_LHM_ACEL_D0_MFC_CLK		27
+#define CLK_GOUT_CORE_LHM_ACEL_D1_ISP_CLK		28
+#define CLK_GOUT_CORE_LHM_ACEL_D1_MFC_CLK		29
+#define CLK_GOUT_CORE_LHM_ACEL_D_CAM_CLK		30
+#define CLK_GOUT_CORE_LHM_ACEL_D_DPU_CLK		31
+#define CLK_GOUT_CORE_LHM_ACEL_D_FSYS_CLK		32
+#define CLK_GOUT_CORE_LHM_ACEL_D_G2D_CLK		33
+#define CLK_GOUT_CORE_LHM_ACEL_D_USB_CLK		34
+#define CLK_GOUT_CORE_LHM_ACEL_D_VIPX1_CLK		35
+#define CLK_GOUT_CORE_LHM_ACEL_D_VIPX2_CLK		36
+#define CLK_GOUT_CORE_LHM_ACE_D_CPUCL0_CLK		37
+#define CLK_GOUT_CORE_LHM_ACE_D_CPUCL1_CLK		38
+#define CLK_GOUT_CORE_LHM_AXI_D0_MODEM_CLK		39
+#define CLK_GOUT_CORE_LHM_AXI_D1_MODEM_CLK		40
+#define CLK_GOUT_CORE_LHM_AXI_D_ABOX_CLK		41
+#define CLK_GOUT_CORE_LHM_AXI_D_APM_CLK			42
+#define CLK_GOUT_CORE_LHM_AXI_D_CSSYS_CLK		43
+#define CLK_GOUT_CORE_LHM_AXI_D_G3D_CLK			44
+#define CLK_GOUT_CORE_LHM_AXI_D_GNSS_CLK		45
+#define CLK_GOUT_CORE_LHM_AXI_D_SHUB_CLK		46
+#define CLK_GOUT_CORE_LHM_AXI_D_WLBT_CLK		47
+#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_CPU_CLK		48
+#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_CP_CLK		49
+#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_NRT_CLK		50
+#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_RT_CLK		51
+#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_CPU_CLK		52
+#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_CP_CLK		53
+#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_NRT_CLK		54
+#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_RT_CLK		55
+#define CLK_GOUT_CORE_LHS_AXI_P_APM_CLK			56
+#define CLK_GOUT_CORE_LHS_AXI_P_CAM_CLK			57
+#define CLK_GOUT_CORE_LHS_AXI_P_CPUCL0_CLK		58
+#define CLK_GOUT_CORE_LHS_AXI_P_CPUCL1_CLK		59
+#define CLK_GOUT_CORE_LHS_AXI_P_DISPAUD_CLK		60
+#define CLK_GOUT_CORE_LHS_AXI_P_FSYS_CLK		61
+#define CLK_GOUT_CORE_LHS_AXI_P_G2D_CLK			62
+#define CLK_GOUT_CORE_LHS_AXI_P_G3D_CLK			63
+#define CLK_GOUT_CORE_LHS_AXI_P_GNSS_CLK		64
+#define CLK_GOUT_CORE_LHS_AXI_P_ISP_CLK			65
+#define CLK_GOUT_CORE_LHS_AXI_P_MFC_CLK			66
+#define CLK_GOUT_CORE_LHS_AXI_P_MIF0_CLK		67
+#define CLK_GOUT_CORE_LHS_AXI_P_MIF1_CLK		68
+#define CLK_GOUT_CORE_LHS_AXI_P_MODEM_CLK		69
+#define CLK_GOUT_CORE_LHS_AXI_P_PERI_CLK		70
+#define CLK_GOUT_CORE_LHS_AXI_P_SHUB_CLK		71
+#define CLK_GOUT_CORE_LHS_AXI_P_USB_CLK			72
+#define CLK_GOUT_CORE_LHS_AXI_P_VIPX1_CLK		73
+#define CLK_GOUT_CORE_LHS_AXI_P_VIPX2_CLK		74
+#define CLK_GOUT_CORE_LHS_AXI_P_WLBT_CLK		75
+#define CLK_GOUT_CORE_PDMA_CORE_ACLK_PDMA0		76
+#define CLK_GOUT_CORE_PGEN_LITE_SIREX_CLK		77
+#define CLK_GOUT_CORE_PGEN_PDMA_CLK			78
+#define CLK_GOUT_CORE_PPCFW_G3D_ACLK			79
+#define CLK_GOUT_CORE_PPCFW_G3D_PCLK			80
+#define CLK_GOUT_CORE_PPFW_CORE_MEM0_CLK		81
+#define CLK_GOUT_CORE_PPFW_CORE_MEM1_CLK		82
+#define CLK_GOUT_CORE_PPFW_CORE_PERI_CLK		83
+#define CLK_GOUT_CORE_PPMU_ACE_CPUCL0_ACLK		84
+#define CLK_GOUT_CORE_PPMU_ACE_CPUCL0_PCLK		85
+#define CLK_GOUT_CORE_PPMU_ACE_CPUCL1_ACLK		86
+#define CLK_GOUT_CORE_PPMU_ACE_CPUCL1_PCLK		87
+#define CLK_GOUT_CORE_BUSD_CLK				88
+#define CLK_GOUT_CORE_BUSP_G3D_OCC_CLK			89
+#define CLK_GOUT_CORE_BUSP_CLK				90
+#define CLK_GOUT_CORE_BUSP_OCC_CLK			91
+#define CLK_GOUT_CORE_CCI_CLK				92
+#define CLK_GOUT_CORE_CCI_OCC_CLK			93
+#define CLK_GOUT_CORE_G3D_CLK				94
+#define CLK_GOUT_CORE_G3D_OCC_CLK			95
+#define CLK_GOUT_CORE_GIC_CLK				96
+#define CLK_GOUT_CORE_OSCCLK_CLK			97
+#define CLK_GOUT_CORE_SFR_APBIF_CMU_TOPC_PCLK		98
+#define CLK_GOUT_CORE_SIREX_ACLK			99
+#define CLK_GOUT_CORE_SIREX_PCLK			100
+#define CLK_GOUT_CORE_SPDMA_CORE_ACLK_PDMA1		101
+#define CLK_GOUT_CORE_SYSREG_PCLK			102
+#define CLK_GOUT_CORE_TREX_D_ACLK			103
+#define CLK_GOUT_CORE_TREX_D_CCLK			104
+#define CLK_GOUT_CORE_TREX_D_GCLK			105
+#define CLK_GOUT_CORE_TREX_D_PCLK			106
+#define CLK_GOUT_CORE_TREX_D_NRT_ACLK			107
+#define CLK_GOUT_CORE_TREX_D_NRT_PCLK			108
+#define CLK_GOUT_CORE_TREX_P_ACLK_P_CORE		109
+#define CLK_GOUT_CORE_TREX_P_CCLK_P_CORE		110
+#define CLK_GOUT_CORE_TREX_P_PCLK			111
+#define CLK_GOUT_CORE_TREX_P_PCLK_P_CORE		112
+#define CLK_GOUT_CORE_XIU_D_ACLK			113
+
+/* CMU_CPUCL0 PLLs */
+#define CLK_FOUT_CPUCL0_PLL				1
+
+/* CMU_CPUCL0 muxes */
+#define CLK_MOUT_PLL_CPUCL0_DBG_USER			2
+#define CLK_MOUT_PLL_CPUCL0_SWITCH_USER			3
+#define CLK_MOUT_CLK_CPUCL0_PLL				4
+
+/* CMU_CPUCL0 dividers */
+#define CLK_DOUT_CLK_CLUSTER0_ACLK			5
+#define CLK_DOUT_CLK_CLUSTER0_CNTCLK			6
+#define CLK_DOUT_CLK_CLUSTER0_PCLKDBG			7
+#define CLK_DOUT_CLK_CPUCL0_CMUREF			8
+#define CLK_DOUT_CLK_CPUCL0_CPU				9
+#define CLK_DOUT_CLK_CPUCL0_PCLK			10
+
+/* CMU_CPUCL0 gates */
+#define CLK_GOUT_CLK_CPUCL0_CMU_PCLK			11
+#define CLK_GOUT_CLK_CPUCL0_HPM_TARGETCLK_C		12
+#define CLK_GOUT_CLK_CPUCL0_OSCCLK_CLK			13
+#define CLK_GOUT_CLK_CLUSTER0_CPU			14
+#define CLK_GOUT_CPUCL0_ADM_APB_G_CSSYS_CORE_PCLKM	15
+#define CLK_GOUT_CPUCL0_ADS_AHB_G_CSSYS_FSYS_HCLKS	16
+#define CLK_GOUT_CPUCL0_ADS_APB_G_CSSYS_CPUCL1_PCLKS	17
+#define CLK_GOUT_CPUCL0_ADS_APB_G_P8Q_PCLKS		18
+#define CLK_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL0_PCLKM	19
+#define CLK_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL1_PCLKM	20
+#define CLK_GOUT_CPUCL0_BUSIF_HPMCPUCL0_PCLK		21
+#define CLK_GOUT_CPUCL0_CSSYS_DBG_PCLKDBG		22
+#define CLK_GOUT_CPUCL0_DUMP_PC_CPUCL0_PCLK		23
+#define CLK_GOUT_CPUCL0_DUMP_PC_CPUCL1_PCLK		24
+#define CLK_GOUT_CPUCL0_LHM_AXI_P_CPUCL0_CLK		25
+#define CLK_GOUT_CPUCL0_LHS_AXI_D_CSSYS_CLK		26
+#define CLK_GOUT_CPUCL0_DBG_CLK				27
+#define CLK_GOUT_CPUCL0_PCLK_CLK			28
+#define CLK_GOUT_CPUCL0_SECJTAG_CLK			29
+#define CLK_GOUT_CPUCL0_SYSREG_PCLK			30
+
+/* CMU_CPUCL1 PLLs */
+#define CLK_FOUT_CPUCL1_PLL				1
+
+/* CMU_CPUCL1 muxes */
+#define CLK_MOUT_PLL_CPUCL1_SWITCH_USER			2
+#define CLK_MOUT_CLK_CPUCL1_PLL				3
+
+/* CMU_CPUCL1 dividers */
+#define CLK_DOUT_CLK_CLUSTER1_ACLK			4
+#define CLK_DOUT_CLK_CLUSTER1_CNTCLK			5
+#define CLK_DOUT_CLK_CPUCL1_CMUREF			6
+#define CLK_DOUT_CLK_CPUCL1_CPU				7
+#define CLK_DOUT_CLK_CPUCL1_PCLK			8
+#define CLK_DOUT_CLK_CPUCL1_PCLKDBG			9
+
+/* CMU_CPUCL1 gates */
+#define CLK_GOUT_CLK_CPUCL1_CMU_PCLK			10
+#define CLK_GOUT_CLK_CPUCL1_HPM_TARGETCLK_C		11
+#define CLK_GOUT_CLK_CPUCL1_OSCCLK_CLK			12
+#define CLK_GOUT_CLK_CLUSTER1_CPU			13
+#define CLK_GOUT_CPUCL1_ADM_APB_G_CSSYS_CPUCL1_PCLKM	14
+#define CLK_GOUT_CPUCL1_BUSIF_HPMCPUCL1_PCLK		15
+#define CLK_GOUT_CPUCL1_LHM_AXI_P_CPUCL1_CLK		16
+#define CLK_GOUT_CPUCL1_LHS_ACE_D_CLK			17
+#define CLK_GOUT_CPUCL1_ACLK_CLK			18
+#define CLK_GOUT_CPUCL1_PCLKDBG_CLK			19
+#define CLK_GOUT_CPUCL1_PCLK_CLK			20
+#define CLK_GOUT_CPUCL1_SYSREG_PCLK			21
+
+/* CMU_DISPAUD PLLs */
+#define CLK_FOUT_AUD_PLL				1
+
+/* CMU_DISPAUD muxes */
+#define CLK_MOUT_PLL_DISPAUD_AUD_USER			2
+#define CLK_MOUT_PLL_DISPAUD_CPU_USER			3
+#define CLK_MOUT_PLL_DISPAUD_DISP_USER			4
+#define CLK_MOUT_CLK_AUD_BUS				5
+#define CLK_MOUT_CLK_AUD_CPU				6
+#define CLK_MOUT_CLK_AUD_CPU_HCH			7
+#define CLK_MOUT_CLK_AUD_FM				8
+#define CLK_MOUT_CLK_AUD_UAIF0				9
+#define CLK_MOUT_CLK_AUD_UAIF1				10
+#define CLK_MOUT_CLK_AUD_UAIF2				11
+
+/* CMU_DISPAUD dividers */
+#define CLK_DOUT_CLK_AUD_AUDIF				12
+#define CLK_DOUT_CLK_AUD_BUS				13
+#define CLK_DOUT_CLK_AUD_CPU				14
+#define CLK_DOUT_CLK_AUD_CPU_ACLK			15
+#define CLK_DOUT_CLK_AUD_CPU_PCLKDBG			16
+#define CLK_DOUT_CLK_AUD_DSIF				17
+#define CLK_DOUT_CLK_AUD_FM				18
+#define CLK_DOUT_CLK_AUD_FM_SPDY			19
+#define CLK_DOUT_CLK_AUD_UAIF0				20
+#define CLK_DOUT_CLK_AUD_UAIF1				21
+#define CLK_DOUT_CLK_AUD_UAIF2				22
+#define CLK_DOUT_CLK_DISPAUD_BUSP			23
+
+/* CMU_DISPAUD gates */
+#define CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF0		24
+#define CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF1		25
+#define CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF2		26
+#define CLK_GOUT_CLK_DISPAUD_CMU_PCLK			27
+#define CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF0_CLK		28
+#define CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF1_CLK		29
+#define CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF2_CLK		30
+#define CLK_GOUT_CLK_DISPAUD_OSCCLK_CLK			31
+#define CLK_GOUT_DISPAUD_ABOX_ACLK			32
+#define CLK_GOUT_DISPAUD_ABOX_BCLK_DSIF			33
+#define CLK_GOUT_DISPAUD_ABOX_BCLK_SPDY			34
+#define CLK_GOUT_DISPAUD_ABOX_CCLK_ASB			35
+#define CLK_GOUT_DISPAUD_ABOX_CCLK_CA7			36
+#define CLK_GOUT_DISPAUD_ABOX_CCLK_DBG			37
+#define CLK_GOUT_DISPAUD_ABOX_OSC_SPDY			38
+#define CLK_GOUT_DISPAUD_AXI_US_32TO128_ACLK		39
+#define CLK_GOUT_DISPAUD_CLK_DISPAUD_AUD		40
+#define CLK_GOUT_DISPAUD_CLK_DISPAUD_DISP		41
+#define CLK_GOUT_DISPAUD_BTM_ABOX_ACLK			42
+#define CLK_GOUT_DISPAUD_BTM_ABOX_PCLK			43
+#define CLK_GOUT_DISPAUD_BTM_DPU_ACLK			44
+#define CLK_GOUT_DISPAUD_BTM_DPU_PCLK			45
+#define CLK_GOUT_DISPAUD_DFTMUX_AUD_CODEC_MCLK		46
+#define CLK_GOUT_DISPAUD_DPU_ACLK_DECON			47
+#define CLK_GOUT_DISPAUD_DPU_ACLK_DMA			48
+#define CLK_GOUT_DISPAUD_DPU_ACLK_DPP			49
+#define CLK_GOUT_DISPAUD_GPIO_DISPAUD_PCLK		50
+#define CLK_GOUT_DISPAUD_LHM_AXI_P_DISPAUD_CLK		51
+#define CLK_GOUT_DISPAUD_LHS_ACEL_D_DPU_CLK		52
+#define CLK_GOUT_DISPAUD_LHS_AXI_D_ABOX_CLK		53
+#define CLK_GOUT_DISPAUD_PERI_AXI_ASB_ACLKM		54
+#define CLK_GOUT_DISPAUD_PERI_AXI_ASB_PCLK		55
+#define CLK_GOUT_DISPAUD_PPMU_ABOX_ACLK			56
+#define CLK_GOUT_DISPAUD_PPMU_ABOX_PCLK			57
+#define CLK_GOUT_DISPAUD_PPMU_DPU_ACLK			58
+#define CLK_GOUT_DISPAUD_PPMU_DPU_PCLK			59
+#define CLK_GOUT_DISPAUD_CLK_AUD_CPU_ACLK_CLK		60
+#define CLK_GOUT_DISPAUD_CLK_AUD_CPU_CLKIN_CLK		61
+#define CLK_GOUT_DISPAUD_CLK_AUD_CPU_PCLKDBG_CLK	62
+#define CLK_GOUT_DISPAUD_CLK_AUD_DSIF_CLK		63
+#define CLK_GOUT_DISPAUD_CLK_AUD_CLK			64
+#define CLK_GOUT_DISPAUD_CLK_BUSP_CLK			65
+#define CLK_GOUT_DISPAUD_CLK_DISP_CLK			66
+#define CLK_GOUT_DISPAUD_SMMU_ABOX_CLK			67
+#define CLK_GOUT_DISPAUD_SMMU_DPU_CLK			68
+#define CLK_GOUT_DISPAUD_SYSREG_PCLK			69
+#define CLK_GOUT_DISPAUD_WDT_AUD_PCLK			70
+
+/* CMU_FSYS muxes */
+#define CLK_MOUT_PLL_FSYS_BUS_USER		1
+#define CLK_MOUT_PLL_FSYS_MMC_CARD_USER		2
+#define CLK_MOUT_PLL_FSYS_MMC_EMBD_USER		3
+#define CLK_MOUT_PLL_FSYS_UFS_EMBD_USER		4
+
+/* CMU_FSYS gates */
+#define CLK_GOUT_FSYS_CMU_PCLK			5
+#define CLK_GOUT_FSYS_OSCCLK_CLK		6
+#define CLK_GOUT_FSYS_ADM_AHB_SSS_HCLKM		7
+#define CLK_GOUT_FSYS_BTM_ACLK			8
+#define CLK_GOUT_FSYS_BTM_PCLK			9
+#define CLK_GOUT_FSYS_GPIO_PCLK			10
+#define CLK_GOUT_FSYS_LHM_AXI_P_CLK		11
+#define CLK_GOUT_FSYS_LHS_ACEL_D_CLK		12
+#define CLK_GOUT_FSYS_MMC_CARD_ACLK		13
+#define CLK_GOUT_FSYS_MMC_CARD_SDCLKIN		14
+#define CLK_GOUT_FSYS_MMC_EMBD_ACLK		15
+#define CLK_GOUT_FSYS_MMC_EMBD_SDCLKIN		16
+#define CLK_GOUT_FSYS_PGEN_LITE_CLK		17
+#define CLK_GOUT_FSYS_PPMU_ACLK			18
+#define CLK_GOUT_FSYS_PPMU_PCLK			19
+#define CLK_GOUT_FSYS_BUS_CLK			20
+#define CLK_GOUT_FSYS_SYSREG_PCLK		21
+#define CLK_GOUT_FSYS_UFS_EMBD_ACLK		22
+#define CLK_GOUT_FSYS_UFS_EMBD_CLK_UNIPRO	23
+#define CLK_GOUT_FSYS_UFS_EMBD_FMP_CLK		24
+#define CLK_GOUT_FSYS_XIU_D_ACLK		25
+
+/* CMU_G2D muxes */
+#define CLK_MOUT_PLL_G2D_G2D_USER	1
+#define CLK_MOUT_PLL_G2D_MSCL_USER	2
+
+/* CMU_G2D dividers */
+#define CLK_DOUT_CLK_G2D_BUSP		3
+
+/* CMU_G2D gates */
+#define CLK_GOUT_CLK_G2D_CMU_PCLK	4
+#define CLK_GOUT_CLK_G2D_OSCCLK_CLK	5
+#define CLK_GOUT_G2D_AS_AXI_JPEG_ACLKM	6
+#define CLK_GOUT_G2D_AS_AXI_JPEG_ACLKS	7
+#define CLK_GOUT_G2D_AS_AXI_MSCL_ACLKM	8
+#define CLK_GOUT_G2D_AS_AXI_MSCL_ACLKS	9
+#define CLK_GOUT_G2D_CLK_G2D_G2D	10
+#define CLK_GOUT_G2D_CLK_G2D_MSCL	11
+#define CLK_GOUT_G2D_BTM_G2D_ACLK	12
+#define CLK_GOUT_G2D_BTM_G2D_PCLK	13
+#define CLK_GOUT_G2D_G2D_ACLK		14
+#define CLK_GOUT_G2D_JPEG_FIMP_CLK	15
+#define CLK_GOUT_G2D_LHM_AXI_P_CLK	16
+#define CLK_GOUT_G2D_LHS_ACEL_D_CLK	17
+#define CLK_GOUT_G2D_MSCL_ACLK		18
+#define CLK_GOUT_G2D_PGEN100_LITE_CLK	19
+#define CLK_GOUT_G2D_PPMU_ACLK		20
+#define CLK_GOUT_G2D_PPMU_PCLK		21
+#define CLK_GOUT_G2D_BUSP_CLK		22
+#define CLK_GOUT_G2D_SYSMMU_CLK		23
+#define CLK_GOUT_G2D_SYSREG_PCLK	24
+#define CLK_GOUT_G2D_XIU_D_MSCL_ACLK	25
+
+/* CMU_G3D PLLs */
+#define CLK_FOUT_G3D_PLL			1
+
+/* CMU_G3D muxes */
+#define CLK_MOUT_G3D_SWITCH_USER		2
+#define CLK_MOUT_CLK_G3D_BUSD			3
+
+/* CMU_G3D dividers */
+#define CLK_DOUT_CLK_G3D_BUSD			4
+#define CLK_DOUT_CLK_G3D_BUSP			5
+
+/* CMU_G3D gates */
+#define CLK_GOUT_CLK_G3D_CMU_PCLK		6
+#define CLK_GOUT_CLK_G3D_G3D_CLK		7
+#define CLK_GOUT_CLK_G3D_HPM_TARGETCLK_C	8
+#define CLK_GOUT_CLK_G3D_OSCCLK_CLK		9
+#define CLK_GOUT_G3D_BTM_G3D_ACLK		10
+#define CLK_GOUT_G3D_BTM_G3D_PCLK		11
+#define CLK_GOUT_G3D_BUSIF_HPMG3D_PCLK		12
+#define CLK_GOUT_G3D_GRAY2BIN_G3D_CLK		13
+#define CLK_GOUT_G3D_LHM_AXI_G3DSFR_CLK		14
+#define CLK_GOUT_G3D_LHM_AXI_P_G3D_CLK		15
+#define CLK_GOUT_G3D_LHS_AXI_D_G3D_CLK		16
+#define CLK_GOUT_G3D_LHS_AXI_G3DSFR_CLK		17
+#define CLK_GOUT_G3D_PGEN_LITE_G3D_CLK		18
+#define CLK_GOUT_G3D_BUSD_CLK			19
+#define CLK_GOUT_G3D_BUSP_CLK			20
+#define CLK_GOUT_G3D_SYSREG_PCLK		21
+
+/* CMU_PERI muxes */
+#define CLK_MOUT_PLL_PERI_BUS_USER		1
+#define CLK_MOUT_PLL_PERI_IP_USER		2
+#define CLK_MOUT_PLL_PERI_UART_USER		3
+
+/* CMU_PERI dividers */
+#define CLK_DOUT_CLK_PERI_I2C			4
+#define CLK_DOUT_CLK_PERI_SPI0			5
+#define CLK_DOUT_CLK_PERI_SPI1			6
+#define CLK_DOUT_CLK_PERI_SPI2			7
+#define CLK_DOUT_CLK_PERI_USI_I2C		8
+#define CLK_DOUT_CLK_PERI_USI_USI		9
+
+/* CMU_PERI gates */
+#define CLK_GOUT_CLK_PERI_I2C			10
+#define CLK_GOUT_CLK_PERI_SPI0			11
+#define CLK_GOUT_CLK_PERI_SPI1			12
+#define CLK_GOUT_CLK_PERI_SPI2			13
+#define CLK_GOUT_CLK_PERI_USI_I2C		14
+#define CLK_GOUT_CLK_PERI_USI_USI		15
+#define CLK_GOUT_PERI_AXI2AHB_MSD32_ACLK	16
+#define CLK_GOUT_PERI_BUSIF_TMU_PCLK		17
+#define CLK_GOUT_PERI_CAMI2C_0_IPCLK		18
+#define CLK_GOUT_PERI_CAMI2C_0_PCLK		19
+#define CLK_GOUT_PERI_CAMI2C_1_IPCLK		20
+#define CLK_GOUT_PERI_CAMI2C_1_PCLK		21
+#define CLK_GOUT_PERI_CAMI2C_2_IPCLK		22
+#define CLK_GOUT_PERI_CAMI2C_2_PCLK		23
+#define CLK_GOUT_PERI_CAMI2C_3_IPCLK		24
+#define CLK_GOUT_PERI_CAMI2C_3_PCLK		25
+#define CLK_GOUT_PERI_I2C_0_PCLK		26
+#define CLK_GOUT_PERI_I2C_1_PCLK		27
+#define CLK_GOUT_PERI_I2C_2_PCLK		28
+#define CLK_GOUT_PERI_I2C_3_PCLK		29
+#define CLK_GOUT_PERI_I2C_4_PCLK		30
+#define CLK_GOUT_PERI_I2C_5_PCLK		31
+#define CLK_GOUT_PERI_I2C_6_PCLK		32
+#define CLK_GOUT_PERI_GPIO_PCLK			33
+#define CLK_GOUT_PERI_LHM_AXI_P_PERI_CLK	34
+#define CLK_GOUT_PERI_MCT_PCLK			35
+#define CLK_GOUT_PERI_OTP_CON_TOP_PCLK		36
+#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0		37
+#define CLK_GOUT_PERI_BUS_CLK			38
+#define CLK_GOUT_PERI_I2C_CLK			39
+#define CLK_GOUT_PERI_SPI_0_CLK			40
+#define CLK_GOUT_PERI_SPI_1_CLK			41
+#define CLK_GOUT_PERI_SPI_2_CLK			42
+#define CLK_GOUT_PERI_UART_CLK			43
+#define CLK_GOUT_PERI_USI00_I2C_CLK		44
+#define CLK_GOUT_PERI_USI00_USI_CLK		45
+#define CLK_GOUT_PERI_SPI_0_PCLK		46
+#define CLK_GOUT_PERI_SPI_0_IPCLK		47
+#define CLK_GOUT_PERI_SPI_1_PCLK		48
+#define CLK_GOUT_PERI_SPI_1_IPCLK		49
+#define CLK_GOUT_PERI_SPI_2_PCLK		50
+#define CLK_GOUT_PERI_SPI_2_IPCLK		51
+#define CLK_GOUT_PERI_SYSREG_PCLK		52
+#define CLK_GOUT_PERI_UART_IPCLK		53
+#define CLK_GOUT_PERI_UART_PCLK			54
+#define CLK_GOUT_PERI_USI00_I2C_IPCLK		55
+#define CLK_GOUT_PERI_USI00_I2C_PCLK		56
+#define CLK_GOUT_PERI_USI00_USI_IPCLK		57
+#define CLK_GOUT_PERI_USI00_USI_PCLK		58
+#define CLK_GOUT_PERI_WDT_CLUSTER0_PCLK		59
+#define CLK_GOUT_PERI_WDT_CLUSTER1_PCLK		60

-- 
2.47.3

Re: [PATCH 1/8] dt-bindings: clock: samsung: Add Exynos9610 CMU bindings

[Rob Herring (Arm)]

On Sun, 14 Sep 2025 21:19:19 +0000, Alexandru Chimac wrote:
> This clock management unit has a topmost block (CMU_TOP)
> that generates top clocks for other blocks, alongside 20
> other blocks, out of which 11 are currently implemented.
> 
> Signed-off-by: Alexandru Chimac <alex@chimac.ro>
> ---
>  .../bindings/clock/samsung,exynos9610-clock.yaml   | 344 ++++++++++
>  include/dt-bindings/clock/samsung,exynos9610.h     | 720 +++++++++++++++++++++
>  2 files changed, 1064 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml:250:13: [warning] wrong indentation: expected 14 but found 12 (indentation)

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/samsung,exynos9610-clock.yaml: $id: 'http://devicetree.org/schemas/clock/samsung,exynos9610-clock.yaml' does not match 'http://devicetree.org/schemas(/[^/ ]+)+\\.yaml#'
	from schema $id: http://devicetree.org/meta-schemas/base.yaml#
Error: Documentation/devicetree/bindings/clock/samsung,exynos9610-clock.example.dts:25.13-14 syntax error
FATAL ERROR: Unable to parse input tree
make[2]: *** [scripts/Makefile.dtbs:131: Documentation/devicetree/bindings/clock/samsung,exynos9610-clock.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1527: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250915-exynos9610-clocks-v1-1-3f615022b178@chimac.ro

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH 2/8] clk: samsung: clk-pll: Add support for pll_1061x

[Alexandru Chimac]

These PLLs are found in the Exynos9610 and Exynos9810 SoCs, and
are similar to pll_1460x, so the code for that can handle this
PLL with a few small adaptations.

Signed-off-by: Alexandru Chimac <alex@chimac.ro>
---
 drivers/clk/samsung/clk-pll.c | 29 ++++++++++++++++++++++-------
 drivers/clk/samsung/clk-pll.h |  1 +
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 7bea7be1d7e45c32f0b303ffa55ce9cde4a4f71d..5fa553eab8e4b53a8854848737f619ef6a9c645a 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -785,15 +785,20 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
 	u64 fvco = parent_rate;
 
 	pll_con0 = readl_relaxed(pll->con_reg);
-	pll_con1 = readl_relaxed(pll->con_reg + 4);
-	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
+	if (pll->type == pll_1061x)
+		pll_con1 = readl_relaxed(pll->con_reg + 12);
+	else
+		pll_con1 = readl_relaxed(pll->con_reg + 4);
+	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & (((pll->type == pll_1460x)
+				|| (pll->type == pll_1061x)) ?
 				PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
 	pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
 	sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
 	kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
 					pll_con1 & PLL46XX_KDIV_MASK;
 
-	shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
+	shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)
+		 || (pll->type == pll_1061x)) ? 16 : 10;
 
 	fvco *= (mdiv << shift) + kdiv;
 	do_div(fvco, (pdiv << sdiv));
@@ -831,7 +836,10 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	}
 
 	con0 = readl_relaxed(pll->con_reg);
-	con1 = readl_relaxed(pll->con_reg + 0x4);
+	if (pll->type == pll_1061x)
+		con1 = readl_relaxed(pll->con_reg + 0xc);
+	else
+		con1 = readl_relaxed(pll->con_reg + 0x4);
 
 	if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
 		/* If only s change, change just s value only*/
@@ -849,7 +857,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
 		lock = 0xffff;
 
 	/* Set PLL PMS and VSEL values. */
-	if (pll->type == pll_1460x) {
+	if ((pll->type == pll_1460x) || (pll->type == pll_1061x)) {
 		con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
 			(PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
 			(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
@@ -866,7 +874,10 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
 			(rate->sdiv << PLL46XX_SDIV_SHIFT);
 
 	/* Set PLL K, MFR and MRR values. */
-	con1 = readl_relaxed(pll->con_reg + 0x4);
+	if (pll->type == pll_1061x)
+		con1 = readl_relaxed(pll->con_reg + 0xc);
+	else
+		con1 = readl_relaxed(pll->con_reg + 0x4);
 	con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
 			(PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
 			(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
@@ -877,7 +888,10 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	/* Write configuration to PLL */
 	writel_relaxed(lock, pll->lock_reg);
 	writel_relaxed(con0, pll->con_reg);
-	writel_relaxed(con1, pll->con_reg + 0x4);
+	if (pll->type == pll_1061x)
+		writel_relaxed(con1, pll->con_reg + 0xc);
+	else
+		writel_relaxed(con1, pll->con_reg + 0x4);
 
 	/* Wait for PLL lock */
 	return samsung_pll_lock_wait(pll, PLL46XX_LOCKED);
@@ -1563,6 +1577,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
 	case pll_4650:
 	case pll_4650c:
 	case pll_1460x:
+	case pll_1061x:
 		if (!pll->rate_table)
 			init.ops = &samsung_pll46xx_clk_min_ops;
 		else
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 6c8bb7f26da5436dfccae89a95d1b0025f7f3e0b..7f36d1d03dcf5888027ce9b6f75ccc9a7a135be2 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -45,6 +45,7 @@ enum samsung_pll_type {
 	pll_531x,
 	pll_1051x,
 	pll_1052x,
+	pll_1061x,
 	pll_0717x,
 	pll_0718x,
 	pll_0732x,

-- 
2.47.3

Re: [PATCH 2/8] clk: samsung: clk-pll: Add support for pll_1061x

[Peng Fan]

On Sun, Sep 14, 2025 at 09:19:32PM +0000, Alexandru Chimac wrote:
>These PLLs are found in the Exynos9610 and Exynos9810 SoCs, and
>are similar to pll_1460x, so the code for that can handle this
>PLL with a few small adaptations.
>
>Signed-off-by: Alexandru Chimac <alex@chimac.ro>
>---
> drivers/clk/samsung/clk-pll.c | 29 ++++++++++++++++++++++-------
> drivers/clk/samsung/clk-pll.h |  1 +
> 2 files changed, 23 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
>index 7bea7be1d7e45c32f0b303ffa55ce9cde4a4f71d..5fa553eab8e4b53a8854848737f619ef6a9c645a 100644
>--- a/drivers/clk/samsung/clk-pll.c
>+++ b/drivers/clk/samsung/clk-pll.c
>@@ -785,15 +785,20 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
> 	u64 fvco = parent_rate;
> 
> 	pll_con0 = readl_relaxed(pll->con_reg);
>-	pll_con1 = readl_relaxed(pll->con_reg + 4);
>-	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
>+	if (pll->type == pll_1061x)
>+		pll_con1 = readl_relaxed(pll->con_reg + 12);
>+	else
>+		pll_con1 = readl_relaxed(pll->con_reg + 4);

Nit: it would be better to use hex value for the two magic numbers.

>+	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & (((pll->type == pll_1460x)
>+				|| (pll->type == pll_1061x)) ?
> 				PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);

FIELD_GET is preferred. But to align the coding style, it should be fine.

Regards
Peng

[PATCH 3/8] clk: samsung: Introduce Exynos9610 clock controller driver

[Alexandru Chimac]

The current implementation contains support for:
- CMU_TOP - which generates clocks for other blocks
- CMU_APM - which generates clocks for APM and CMU_CMGP
- CMU_CAM
- CMU_CMGP
- CMU_CORE
- CMU_CPUCL0/1
- CMU_DISPAUD - which generates clocks for display and ABOX
- CMU_FSYS - which generates clocks for MMC/UFS
- CMU_G2D, G3D
- CMU_PERI - which generates clocks for peripherals

Signed-off-by: Alexandru Chimac <alex@chimac.ro>
---
 drivers/clk/samsung/Makefile         |    1 +
 drivers/clk/samsung/clk-exynos9610.c | 3652 ++++++++++++++++++++++++++++++++++
 2 files changed, 3653 insertions(+)

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index ef464f434740f96623f9df62f94e2903e14e2226..2605bdecb5fff6b5a8f73cad50e8c1a618cfba63 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7870.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7885.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos850.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos8895.o
+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos9610.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos990.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov9.o
 obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov920.o
diff --git a/drivers/clk/samsung/clk-exynos9610.c b/drivers/clk/samsung/clk-exynos9610.c
new file mode 100644
index 0000000000000000000000000000000000000000..637daae1e4969dba15518f73da74648981351dcb
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos9610.c
@@ -0,0 +1,3652 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common clock framework for Exynos9610
+ *
+ * Copyright (c) 2025, Alexandru Chimac <alex@chimac.ro>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/samsung,exynos9610.h>
+
+#include "clk.h"
+#include "clk-exynos-arm64.h"
+#include "clk-pll.h"
+
+#define CLKS_NR_TOP	(CLK_GOUT_CMU_VIPX2_BUS + 1)
+#define CLKS_NR_APM	(CLK_GOUT_APM_XIU_DP_ACLK + 1)
+#define CLKS_NR_CAM	(CLK_GOUT_CAM_SYSREG_PCLK + 1)
+#define CLKS_NR_CMGP	(CLK_GOUT_CMGP_USI_CMGP04_PCLK + 1)
+#define CLKS_NR_CORE	(CLK_GOUT_CORE_XIU_D_ACLK + 1)
+#define CLKS_NR_CPUCL0	(CLK_GOUT_CPUCL0_SYSREG_PCLK + 1)
+#define CLKS_NR_CPUCL1	(CLK_GOUT_CPUCL1_SYSREG_PCLK + 1)
+#define CLKS_NR_DISPAUD	(CLK_GOUT_DISPAUD_WDT_AUD_PCLK + 1)
+#define CLKS_NR_FSYS	(CLK_GOUT_FSYS_XIU_D_ACLK + 1)
+#define CLKS_NR_G2D	(CLK_GOUT_G2D_XIU_D_MSCL_ACLK + 1)
+#define CLKS_NR_G3D	(CLK_GOUT_G3D_SYSREG_PCLK + 1)
+#define CLKS_NR_PERI	(CLK_GOUT_PERI_WDT_CLUSTER1_PCLK + 1)
+
+/* TOP (0x12100000) */
+#define PLL_LOCKTIME_PLL_MMC				0x0000
+#define PLL_LOCKTIME_PLL_SHARED0			0x0004
+#define PLL_LOCKTIME_PLL_SHARED1			0x0008
+#define PLL_CON0_PLL_MMC				0x0100
+#define PLL_CON3_PLL_MMC				0x010c
+#define PLL_CON0_PLL_SHARED0				0x0120
+#define PLL_CON0_PLL_SHARED1				0x0140
+#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS			0x1000
+#define CLK_CON_MUX_MUX_CLKCMU_CAM_BUS			0x1004
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0			0x1008
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1			0x100c
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2			0x1010
+#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3			0x1014
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS			0x1018
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI			0x101c
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D			0x1020
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG		0x1024
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH		0x1028
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH		0x102c
+#define CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD		0x1030
+#define CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU		0x1034
+#define CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP		0x1038
+#define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS			0x103c
+#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD		0x1040
+#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD		0x1044
+#define CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD		0x1048
+#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D			0x104c
+#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL			0x1050
+#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH		0x1054
+#define CLK_CON_MUX_MUX_CLKCMU_HPM			0x1058
+#define CLK_CON_MUX_MUX_CLKCMU_ISP_BUS			0x105c
+#define CLK_CON_MUX_MUX_CLKCMU_ISP_GDC			0x1060
+#define CLK_CON_MUX_MUX_CLKCMU_ISP_VRA			0x1064
+#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC			0x1068
+#define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD			0x106c
+#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP			0x1070
+#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH		0x1074
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS			0x1078
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP			0x107c
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART		0x1080
+#define CLK_CON_MUX_MUX_CLKCMU_USB_BUS			0x1084
+#define CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC		0x1088
+#define CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD		0x108c
+#define CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS		0x1090
+#define CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS		0x1094
+#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF			0x1098
+#define CLK_CON_MUX_MUX_CMU_CMUREF			0x109c
+#define CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK		0x1800
+#define CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK		0x1804
+#define CLK_CON_DIV_CLKCMU_APM_BUS			0x1808
+#define CLK_CON_DIV_CLKCMU_CAM_BUS			0x180c
+#define CLK_CON_DIV_CLKCMU_CIS_CLK0			0x1810
+#define CLK_CON_DIV_CLKCMU_CIS_CLK1			0x1814
+#define CLK_CON_DIV_CLKCMU_CIS_CLK2			0x1818
+#define CLK_CON_DIV_CLKCMU_CIS_CLK3			0x181c
+#define CLK_CON_DIV_CLKCMU_CORE_BUS			0x1820
+#define CLK_CON_DIV_CLKCMU_CORE_CCI			0x1824
+#define CLK_CON_DIV_CLKCMU_CORE_G3D			0x1828
+#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG			0x182c
+#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH		0x1830
+#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH		0x1834
+#define CLK_CON_DIV_CLKCMU_DISPAUD_AUD			0x1838
+#define CLK_CON_DIV_CLKCMU_DISPAUD_CPU			0x183c
+#define CLK_CON_DIV_CLKCMU_DISPAUD_DISP			0x1840
+#define CLK_CON_DIV_CLKCMU_FSYS_BUS			0x1844
+#define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD		0x1848
+#define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD		0x184c
+#define CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD		0x1850
+#define CLK_CON_DIV_CLKCMU_G2D_G2D			0x1854
+#define CLK_CON_DIV_CLKCMU_G2D_MSCL			0x1858
+#define CLK_CON_DIV_CLKCMU_G3D_SWITCH			0x185c
+#define CLK_CON_DIV_CLKCMU_HPM				0x1860
+#define CLK_CON_DIV_CLKCMU_ISP_BUS			0x1864
+#define CLK_CON_DIV_CLKCMU_ISP_GDC			0x1868
+#define CLK_CON_DIV_CLKCMU_ISP_VRA			0x186c
+#define CLK_CON_DIV_CLKCMU_MFC_MFC			0x1870
+#define CLK_CON_DIV_CLKCMU_MFC_WFD			0x1874
+#define CLK_CON_DIV_CLKCMU_MIF_BUSP			0x1878
+#define CLK_CON_DIV_CLKCMU_OTP				0x187c
+#define CLK_CON_DIV_CLKCMU_PERI_BUS			0x1880
+#define CLK_CON_DIV_CLKCMU_PERI_IP			0x1884
+#define CLK_CON_DIV_CLKCMU_PERI_UART			0x1888
+#define CLK_CON_DIV_CLKCMU_USB_BUS			0x188c
+#define CLK_CON_DIV_CLKCMU_USB_DPGTC			0x1890
+#define CLK_CON_DIV_CLKCMU_USB_USB30DRD			0x1894
+#define CLK_CON_DIV_CLKCMU_VIPX1_BUS			0x1898
+#define CLK_CON_DIV_CLKCMU_VIPX2_BUS			0x189c
+#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF			0x18a0
+#define CLK_CON_DIV_PLL_MMC_DIV2			0x18a4
+#define CLK_CON_DIV_PLL_SHARED0_DIV2			0x18a8
+#define CLK_CON_DIV_PLL_SHARED0_DIV3			0x18ac
+#define CLK_CON_DIV_PLL_SHARED0_DIV4			0x18b0
+#define CLK_CON_DIV_PLL_SHARED1_DIV2			0x18b4
+#define CLK_CON_DIV_PLL_SHARED1_DIV3			0x18b8
+#define CLK_CON_DIV_PLL_SHARED1_DIV4			0x18bc
+#define CLK_CON_GAT_CLKCMU_MIF_SWITCH			0x2000
+#define CLK_CON_GAT_CLK_CMU_OTP_CLK			0x2004
+#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS			0x2008
+#define CLK_CON_GAT_GATE_CLKCMU_CAM_BUS			0x200c
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0		0x2010
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1		0x2014
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2		0x2018
+#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3		0x201c
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS		0x2020
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI		0x2024
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D		0x2028
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG		0x202c
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH		0x2030
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH		0x2034
+#define CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD		0x2038
+#define CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU		0x203c
+#define CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP		0x2040
+#define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS		0x2044
+#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD		0x2048
+#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD		0x204c
+#define CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD		0x2050
+#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D			0x2054
+#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL		0x2058
+#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH		0x205c
+#define CLK_CON_GAT_GATE_CLKCMU_HPM			0x2060
+#define CLK_CON_GAT_GATE_CLKCMU_ISP_BUS			0x2064
+#define CLK_CON_GAT_GATE_CLKCMU_ISP_GDC			0x2068
+#define CLK_CON_GAT_GATE_CLKCMU_ISP_VRA			0x206c
+#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC			0x2070
+#define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD			0x2074
+#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP		0x2078
+#define CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0		0x207c
+#define CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1		0x2080
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS		0x2084
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP			0x2088
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART		0x208c
+#define CLK_CON_GAT_GATE_CLKCMU_USB_BUS			0x2090
+#define CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC		0x2094
+#define CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD		0x2098
+#define CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS		0x209c
+#define CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS		0x20a0
+
+static const unsigned long top_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_MMC,
+	PLL_LOCKTIME_PLL_SHARED0,
+	PLL_LOCKTIME_PLL_SHARED1,
+	PLL_CON0_PLL_MMC,
+	PLL_CON3_PLL_MMC,
+	PLL_CON0_PLL_SHARED0,
+	PLL_CON0_PLL_SHARED1,
+	CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_CAM_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
+	CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
+	CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
+	CLK_CON_MUX_MUX_CLKCMU_CORE_G3D,
+	CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
+	CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
+	CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
+	CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD,
+	CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU,
+	CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP,
+	CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD,
+	CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD,
+	CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD,
+	CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
+	CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
+	CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
+	CLK_CON_MUX_MUX_CLKCMU_HPM,
+	CLK_CON_MUX_MUX_CLKCMU_ISP_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_ISP_GDC,
+	CLK_CON_MUX_MUX_CLKCMU_ISP_VRA,
+	CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
+	CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
+	CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
+	CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
+	CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
+	CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
+	CLK_CON_MUX_MUX_CLKCMU_USB_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC,
+	CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD,
+	CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS,
+	CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS,
+	CLK_CON_MUX_MUX_CLK_CMU_CMUREF,
+	CLK_CON_MUX_MUX_CMU_CMUREF,
+	CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK,
+	CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK,
+	CLK_CON_DIV_CLKCMU_APM_BUS,
+	CLK_CON_DIV_CLKCMU_CAM_BUS,
+	CLK_CON_DIV_CLKCMU_CORE_BUS,
+	CLK_CON_DIV_CLKCMU_CORE_CCI,
+	CLK_CON_DIV_CLKCMU_CORE_G3D,
+	CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
+	CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
+	CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
+	CLK_CON_DIV_CLKCMU_DISPAUD_AUD,
+	CLK_CON_DIV_CLKCMU_DISPAUD_CPU,
+	CLK_CON_DIV_CLKCMU_DISPAUD_DISP,
+	CLK_CON_DIV_CLKCMU_FSYS_BUS,
+	CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD,
+	CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD,
+	CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD,
+	CLK_CON_DIV_CLKCMU_G2D_G2D,
+	CLK_CON_DIV_CLKCMU_G2D_MSCL,
+	CLK_CON_DIV_CLKCMU_G3D_SWITCH,
+	CLK_CON_DIV_CLKCMU_HPM,
+	CLK_CON_DIV_CLKCMU_ISP_BUS,
+	CLK_CON_DIV_CLKCMU_ISP_GDC,
+	CLK_CON_DIV_CLKCMU_ISP_VRA,
+	CLK_CON_DIV_CLKCMU_MFC_MFC,
+	CLK_CON_DIV_CLKCMU_MFC_WFD,
+	CLK_CON_DIV_CLKCMU_MIF_BUSP,
+	CLK_CON_DIV_CLKCMU_OTP,
+	CLK_CON_DIV_CLKCMU_PERI_BUS,
+	CLK_CON_DIV_CLKCMU_PERI_IP,
+	CLK_CON_DIV_CLKCMU_PERI_UART,
+	CLK_CON_DIV_CLKCMU_USB_BUS,
+	CLK_CON_DIV_CLKCMU_USB_DPGTC,
+	CLK_CON_DIV_CLKCMU_USB_USB30DRD,
+	CLK_CON_DIV_CLKCMU_VIPX1_BUS,
+	CLK_CON_DIV_CLKCMU_VIPX2_BUS,
+	CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
+	CLK_CON_DIV_PLL_SHARED0_DIV2,
+	CLK_CON_DIV_PLL_SHARED0_DIV3,
+	CLK_CON_DIV_PLL_SHARED0_DIV4,
+	CLK_CON_DIV_PLL_SHARED1_DIV2,
+	CLK_CON_DIV_PLL_SHARED1_DIV3,
+	CLK_CON_DIV_PLL_SHARED1_DIV4,
+	CLK_CON_GAT_CLKCMU_MIF_SWITCH,
+	CLK_CON_GAT_CLK_CMU_OTP_CLK,
+	CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_CAM_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
+	CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
+	CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
+	CLK_CON_GAT_GATE_CLKCMU_CORE_G3D,
+	CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG,
+	CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
+	CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
+	CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD,
+	CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU,
+	CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP,
+	CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD,
+	CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD,
+	CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD,
+	CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
+	CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
+	CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
+	CLK_CON_GAT_GATE_CLKCMU_HPM,
+	CLK_CON_GAT_GATE_CLKCMU_ISP_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_ISP_GDC,
+	CLK_CON_GAT_GATE_CLKCMU_ISP_VRA,
+	CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
+	CLK_CON_GAT_GATE_CLKCMU_MFC_WFD,
+	CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
+	CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0,
+	CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1,
+	CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
+	CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
+	CLK_CON_GAT_GATE_CLKCMU_USB_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC,
+	CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD,
+	CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS,
+	CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS,
+};
+
+static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = {
+	PLL_35XX_RATE(26 * MHZ, 1599000000U, 246, 4, 0),
+};
+
+static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = {
+	PLL_35XX_RATE(26 * MHZ, 1332500000U, 205, 4, 0),
+};
+
+static const struct samsung_pll_rate_table pll_mmc_rate_table[] __initconst = {
+	PLL_36XX_RATE(26 * MHZ, 799999877, 31, 1, 0, -15124),
+};
+
+static const struct samsung_pll_clock top_pll_clks[] __initconst = {
+	PLL(pll_1051x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, pll_shared0_rate_table),
+	PLL(pll_1051x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, pll_shared1_rate_table),
+	PLL(pll_1061x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_MMC, PLL_CON0_PLL_MMC, pll_mmc_rate_table),
+};
+
+/* Parent clock list for TOP muxes */
+PNAME(mout_pll_shared0_p)	= { "oscclk", "fout_shared0_pll" };
+PNAME(mout_pll_shared1_p)	= { "oscclk", "fout_shared1_pll" };
+PNAME(mout_pll_mmc_p)		= { "oscclk", "fout_mmc_pll" };
+PNAME(mout_cmu_apm_bus_p)	= { "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4" };
+PNAME(mout_cmu_cam_bus_p)	= { "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_cmu_cis_clk0_p)	= { "oscclk",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_cmu_cis_clk1_p)	= { "oscclk",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_cmu_cis_clk2_p)	= { "oscclk",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_cmu_cis_clk3_p)	= { "oscclk",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_cmu_core_bus_p)	= { "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_mmc_div2" };
+PNAME(mout_cmu_core_cci_p)	= { "dout_cmu_shared0_div2",
+				    "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_mmc_div2" };
+PNAME(mout_cmu_core_g3d_p)	= { "dout_cmu_shared0_div2",
+				    "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_mmc_div2" };
+PNAME(mout_cmu_cpucl0_dbg_p)	= { "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4" };
+PNAME(mout_cmu_cpucl0_switch_p)	= { "dout_cmu_shared0_div2",
+				    "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3" };
+PNAME(mout_cmu_cpucl1_switch_p)	= { "dout_cmu_shared0_div2",
+				    "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3" };
+PNAME(mout_cmu_dispaud_aud_p)	= { "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_cmu_dispaud_cpu_p)	= { "fout_shared1_pll",
+				    "dout_cmu_shared0_div2",
+				    "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "fout_mmc_pll",
+				    "oscclk", "oscclk" };
+PNAME(mout_cmu_dispaud_disp_p)	= { "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_cmu_fsys_bus_p)	= { "dout_cmu_shared0_div2",
+				    "dout_cmu_shared1_div2" };
+PNAME(mout_cmu_fsys_mmc_card_p)	= { "oscclk",
+				    "dout_cmu_shared0_div2",
+				    "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "fout_mmc_pll",
+				    "oscclk", "oscclk" };
+PNAME(mout_cmu_fsys_mmc_embd_p)	= { "oscclk",
+				    "dout_cmu_shared0_div2",
+				    "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "fout_mmc_pll",
+				    "oscclk", "oscclk" };
+PNAME(mout_cmu_fsys_ufs_embd_p) = { "oscclk",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4",
+				    "oscclk" };
+PNAME(mout_cmu_g2d_g2d_p)	= { "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_cmu_g2d_mscl_p)	= { "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4" };
+PNAME(mout_cmu_g3d_switch_p)	= { "dout_cmu_shared0_div2",
+				    "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3" };
+PNAME(mout_cmu_hpm_p)		= { "oscclk",
+				    "dout_cmu_shared0_div2",
+				    "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_mmc_div2",
+				    "oscclk", "oscclk", "oscclk" };
+PNAME(mout_cmu_isp_bus_p)	= { "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_cmu_isp_gdc_p)	= { "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4" };
+PNAME(mout_cmu_isp_vra_p)	= { "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4" };
+PNAME(mout_cmu_mfc_mfc_p)	= { "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_cmu_mfc_wfd_p)	= { "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4" };
+PNAME(mout_cmu_mif_busp_p)	= { "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4",
+				    "dout_cmu_mmc_div2",
+				    "oscclk" };
+PNAME(mout_cmu_mif_switch_p)	= { "fout_shared0_pll",
+				    "fout_shared1_pll",
+				    "dout_cmu_shared0_div2",
+				    "fout_mmc_pll",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4" };
+PNAME(mout_cmu_peri_bus_p)	= { "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4" };
+PNAME(mout_cmu_peri_ip_p)	= { "oscclk",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4",
+				    "oscclk" };
+PNAME(mout_cmu_peri_uart_p)	= { "oscclk",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4",
+				    "oscclk" };
+PNAME(mout_cmu_usb_bus_p)	= { "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4" };
+PNAME(mout_cmu_usb_dpgtc_p)	= { "oscclk",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4",
+				    "oscclk" };
+PNAME(mout_cmu_usb_usb30drd_p)	= { "oscclk",
+				    "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4",
+				    "oscclk" };
+PNAME(mout_cmu_vipx1_bus_p)	= { "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_cmu_vipx2_bus_p)	= { "dout_cmu_shared1_div2",
+				    "dout_cmu_shared0_div3",
+				    "dout_cmu_shared1_div3",
+				    "dout_cmu_shared0_div4" };
+PNAME(mout_clk_cmu_cmuref_p)	= { "dout_cmu_shared0_div4",
+				    "dout_cmu_shared1_div4" };
+PNAME(mout_cmu_cmuref_p)	= { "oscclk",
+				    "dout_clk_cmu_cmuref" };
+
+/*
+ * Register name to clock name mangling strategy used in this file
+ *
+ * Replace PLL_CON{0,3}_PLL	   with CLK_MOUT_PLL and mout_pll
+ * Replace CLK_CON_MUX_MUX_CLKCMU  with CLK_MOUT_CMU and mout_cmu
+ * Replace CLK_CON_DIV_CLKCMU      with CLK_DOUT_CMU_CMU and dout_cmu_cmu
+ * Replace CLK_CON_DIV_DIV_CLKCMU  with CLK_DOUT_CMU_CMU and dout_cmu_cmu
+ * Replace CLK_CON_DIV_PLL_CLKCMU  with CLK_DOUT_CMU_CMU and dout_cmu_cmu
+ * Replace CLK_CON_GAT_CLKCMU      with CLK_GOUT_CMU and gout_cmu
+ * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu
+ *
+ * For gates remove _UID _BLK _IPCLKPORT, _I and _RSTNSYNC
+ */
+
+static const struct samsung_mux_clock top_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
+	    PLL_CON0_PLL_SHARED0, 4, 1),
+	MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
+	    PLL_CON0_PLL_SHARED1, 4, 1),
+	MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,
+	    PLL_CON0_PLL_MMC, 4, 1),
+
+	MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus", mout_cmu_apm_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
+	MUX(CLK_MOUT_CMU_CAM_BUS, "mout_cmu_cam_bus", mout_cmu_cam_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CAM_BUS, 0, 2),
+	MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 1),
+	MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk1_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 1),
+	MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk2_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 1),
+	MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk2_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 1),
+	MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
+	MUX(CLK_MOUT_CMU_CORE_CCI, "mout_cmu_core_cci", mout_cmu_core_cci_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
+	MUX(CLK_MOUT_CMU_CORE_G3D, "mout_cmu_core_g3d", mout_cmu_core_g3d_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2),
+	MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0, 1),
+	MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0_switch_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 1),
+	MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1_switch_p,
+	    CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
+	MUX(CLK_MOUT_CMU_DISPAUD_AUD, "mout_cmu_dispaud_aud", mout_cmu_dispaud_aud_p,
+	    CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD, 0, 2),
+	MUX(CLK_MOUT_CMU_DISPAUD_CPU, "mout_cmu_dispaud_cpu", mout_cmu_dispaud_cpu_p,
+	    CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU, 0, 3),
+	MUX(CLK_MOUT_CMU_DISPAUD_DISP, "mout_cmu_dispaud_disp", mout_cmu_dispaud_disp_p,
+	    CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP, 0, 2),
+	MUX(CLK_MOUT_CMU_FSYS_BUS, "mout_cmu_fsys_bus", mout_cmu_fsys_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1),
+	MUX(CLK_MOUT_CMU_FSYS_MMC_CARD, "mout_cmu_fsys_mmc_card", mout_cmu_fsys_mmc_card_p,
+	    CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 3),
+	MUX(CLK_MOUT_CMU_FSYS_MMC_EMBD, "mout_cmu_fsys_mmc_embd", mout_cmu_fsys_mmc_embd_p,
+	    CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 3),
+	MUX(CLK_MOUT_CMU_FSYS_UFS_EMBD, "mout_cmu_fsys_ufs_embd", mout_cmu_fsys_ufs_embd_p,
+	    CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD, 0, 2),
+	MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
+	    CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
+	MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
+	    CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
+	MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_SWITCH", mout_cmu_g3d_switch_p,
+	    CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
+	MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
+	    CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 3),
+	MUX(CLK_MOUT_CMU_ISP_BUS, "mout_cmu_isp_bus", mout_cmu_isp_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_ISP_BUS, 0, 2),
+	MUX(CLK_MOUT_CMU_ISP_GDC, "mout_cmu_isp_gdc", mout_cmu_isp_gdc_p,
+	    CLK_CON_MUX_MUX_CLKCMU_ISP_GDC, 0, 2),
+	MUX(CLK_MOUT_CMU_ISP_VRA, "mout_cmu_isp_vra", mout_cmu_isp_vra_p,
+	    CLK_CON_MUX_MUX_CLKCMU_ISP_VRA, 0, 2),
+	MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
+	    CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
+	MUX(CLK_MOUT_CMU_MFC_WFD, "mout_cmu_mfc_wfd", mout_cmu_mfc_wfd_p,
+	    CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
+	MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
+	    CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
+	MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p,
+	    CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
+	MUX(CLK_MOUT_CMU_PERI_BUS, "mout_cmu_peri_bus", mout_cmu_peri_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
+	MUX(CLK_MOUT_CMU_PERI_IP, "mout_cmu_peri_ip", mout_cmu_peri_ip_p,
+	    CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
+	MUX(CLK_MOUT_CMU_PERI_UART, "mout_cmu_peri_uart", mout_cmu_peri_uart_p,
+	    CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
+	MUX(CLK_MOUT_CMU_USB_BUS, "mout_cmu_usb_bus", mout_cmu_usb_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_USB_BUS, 0, 2),
+	MUX(CLK_MOUT_CMU_USB_DPGTC, "mout_cmu_usb_dpgtc", mout_cmu_usb_dpgtc_p,
+	    CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC, 0, 2),
+	MUX(CLK_MOUT_CMU_USB_USB30DRD, "mout_cmu_usb_usb30drd", mout_cmu_usb_usb30drd_p,
+	    CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD, 0, 2),
+	MUX(CLK_MOUT_CMU_VIPX1_BUS, "mout_cmu_vipx1_bus", mout_cmu_vipx1_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS, 0, 2),
+	MUX(CLK_MOUT_CMU_VIPX2_BUS, "mout_cmu_vipx2_bus", mout_cmu_vipx2_bus_p,
+	    CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS, 0, 2),
+	MUX(CLK_MOUT_CLK_CMU_CMUREF, "mout_clk_cmu_cmuref", mout_clk_cmu_cmuref_p,
+	    CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 1),
+	MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p,
+	    CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
+};
+
+static const struct samsung_div_clock top_div_clks[] __initconst = {
+	/* shared0 */
+	DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0",
+	    CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
+	DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0",
+	    CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
+	DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2",
+	    CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
+
+	/* shared1 */
+	DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1",
+	    CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
+	DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1",
+	    CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
+	DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2",
+	    CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
+
+	/* mmc */
+	DIV(CLK_DOUT_CMU_MMC_DIV2, "dout_cmu_mmc_div2", "mout_pll_mmc",
+	    CLK_CON_DIV_PLL_MMC_DIV2, 0, 1),
+
+	DIV(CLK_DOUT_AP2CP_SHARED0_PLL_CLK, "dout_ap2cp_shared0_pll_clk",
+	    "gout_cmu_modem_shared0", CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK,
+	    0, 4),
+	DIV(CLK_DOUT_AP2CP_SHARED1_PLL_CLK, "dout_ap2cp_shared1_pll_clk",
+	    "gout_cmu_modem_shared1", CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK,
+	    0, 4),
+	DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
+	    CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
+	DIV(CLK_DOUT_CMU_CAM_BUS, "dout_cmu_cam_bus", "gout_cmu_cam_bus",
+	    CLK_CON_DIV_CLKCMU_CAM_BUS, 0, 4),
+	DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0",
+	    CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
+	DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1",
+	    CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
+	DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2",
+	    CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
+	DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3",
+	    CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
+	DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
+	    CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
+	DIV(CLK_DOUT_CMU_CORE_CCI, "dout_cmu_core_cci", "gout_cmu_core_cci",
+	    CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
+	DIV(CLK_DOUT_CMU_CORE_G3D, "dout_cmu_core_g3d", "gout_cmu_core_g3d",
+	    CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 4),
+	DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg",
+	    CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
+	DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl1_switch",
+	    CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
+	DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", "gout_cmu_cpucl1_switch",
+	    CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
+	DIV(CLK_DOUT_CMU_DISPAUD_AUD, "dout_cmu_dispaud_aud", "gout_cmu_dispaud_aud",
+	    CLK_CON_DIV_CLKCMU_DISPAUD_AUD, 0, 4),
+	DIV(CLK_DOUT_CMU_DISPAUD_CPU, "dout_cmu_dispaud_cpu", "gout_cmu_dispaud_cpu",
+	    CLK_CON_DIV_CLKCMU_DISPAUD_CPU, 0, 4),
+	DIV(CLK_DOUT_CMU_DISPAUD_DISP, "dout_cmu_dispaud_disp", "gout_cmu_dispaud_disp",
+	    CLK_CON_DIV_CLKCMU_DISPAUD_DISP, 0, 4),
+	DIV(CLK_DOUT_CMU_FSYS_BUS, "dout_cmu_fsys_bus", "gout_cmu_fsys_bus",
+	    CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4),
+	DIV(CLK_DOUT_CMU_FSYS_MMC_CARD, "dout_cmu_fsys_mmc_card", "gout_cmu_fsys_mmc_card",
+	    CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9),
+	DIV(CLK_DOUT_CMU_FSYS_MMC_EMBD, "dout_cmu_fsys_mmc_embd", "gout_cmu_fsys_mmc_embd",
+	    CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9),
+	DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
+	    CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
+	DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
+	    CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
+	DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch",
+	    CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
+	DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
+	    CLK_CON_DIV_CLKCMU_HPM, 0, 2),
+	DIV(CLK_DOUT_CMU_ISP_BUS, "dout_cmu_isp_bus", "gout_cmu_isp_bus",
+	    CLK_CON_DIV_CLKCMU_ISP_BUS, 0, 4),
+	DIV(CLK_DOUT_CMU_ISP_GDC, "dout_cmu_isp_gdc", "gout_cmu_isp_gdc",
+	    CLK_CON_DIV_CLKCMU_ISP_GDC, 0, 4),
+	DIV(CLK_DOUT_CMU_ISP_VRA, "dout_cmu_isp_vra", "gout_cmu_isp_vra",
+	    CLK_CON_DIV_CLKCMU_ISP_VRA, 0, 4),
+	DIV(CLK_DOUT_CMU_MFD_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
+	    CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
+	DIV(CLK_DOUT_CMU_MFD_WFD, "dout_cmu_mfc_wfd", "gout_cmu_mfc_wfd",
+	    CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
+	DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
+	    CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 3),
+	DIV(CLK_DOUT_CMU_PERI_BUS, "dout_cmu_peri_bus", "gout_cmu_peri_bus",
+	    CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
+	DIV(CLK_DOUT_CMU_PERI_IP, "dout_cmu_peri_ip", "gout_cmu_peri_ip",
+	    CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
+	DIV(CLK_DOUT_CMU_PERI_UART, "dout_cmu_peri_uart", "gout_cmu_peri_uart",
+	    CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
+	DIV(CLK_DOUT_CMU_USB_BUS, "dout_cmu_usb_bus", "gout_cmu_usb_bus",
+	    CLK_CON_DIV_CLKCMU_USB_BUS, 0, 4),
+	DIV(CLK_DOUT_CMU_USB_DPGTC, "dout_cmu_usb_dpgtc", "gout_cmu_usb_dpgtc",
+	    CLK_CON_DIV_CLKCMU_USB_DPGTC, 0, 4),
+	DIV(CLK_DOUT_CMU_USB_BUS, "dout_cmu_usb_usb30drd", "gout_cmu_usb_usb30drd",
+	    CLK_CON_DIV_CLKCMU_USB_USB30DRD, 0, 4),
+	DIV(CLK_DOUT_CMU_VIPX1_BUS, "dout_cmu_vipx1_bus", "gout_cmu_vipx1_bus",
+	    CLK_CON_DIV_CLKCMU_VIPX1_BUS, 0, 4),
+	DIV(CLK_DOUT_CMU_VIPX2_BUS, "dout_cmu_vipx2_bus", "gout_cmu_vipx2_bus",
+	    CLK_CON_DIV_CLKCMU_VIPX2_BUS, 0, 4),
+	DIV(CLK_DOUT_CLK_CMU_CMUREF, "dout_clk_cmu_cmuref", "mout_clk_cmu_cmuref",
+	    CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
+};
+
+static const struct samsung_fixed_factor_clock top_ffactor_clks[] __initconst = {
+	FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 7, 0),
+};
+
+static const struct samsung_gate_clock top_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",
+	     "mux_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_CMU_OTP_CLK, "gout_clk_cmu_otp_clk", "dout_cmu_otp",
+	     CLK_CON_GAT_CLK_CMU_OTP_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_APM_BUS, "gout_cmu_apm_bus", "mout_cmu_apm_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_CAM_BUS, "gout_cmu_cam_bus", "mout_cmu_cam_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_CAM_BUS, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
+	     CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_CMU_CORE_CCI, "gout_cmu_core_cci", "mout_cmu_core_cci",
+	     CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_CMU_CORE_G3D, "gout_cmu_core_g3d", "mout_cmu_core_g3d",
+	     CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, CLK_IS_CRITICAL, 0),
+	GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg",
+	     CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpucl0_switch",
+	     CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpucl1_switch",
+	     CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_DISPAUD_AUD, "gout_cmu_dispaud_aud", "mout_cmu_dispaud_aud",
+	     CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_DISPAUD_CPU, "gout_cmu_dispaud_cpu", "mout_cmu_dispaud_cpu",
+	     CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_DISPAUD_DISP, "gout_cmu_dispaud_disp", "mout_cmu_dispaud_disp",
+	     CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_FSYS_BUS, "gout_cmu_fsys_bus", "mout_cmu_fsys_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_FSYS_MMC_CARD, "gout_cmu_fsys_mmc_card", "mout_cmu_fsys_mmc_card",
+	     CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_FSYS_MMC_EMBD, "gout_cmu_fsys_mmc_embd", "mout_cmu_fsys_mmc_embd",
+	     CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_FSYS_UFS_EMBD, "gout_cmu_fsys_ufs_embd", "mout_cmu_fsys_ufs_embd",
+	     CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
+	     CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
+	     CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch",
+	     CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
+	     CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_ISP_BUS, "gout_cmu_isp_bus", "mout_cmu_isp_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_ISP_BUS, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_ISP_GDC, "gout_cmu_isp_gdc", "mout_cmu_isp_gdc",
+	     CLK_CON_GAT_GATE_CLKCMU_ISP_GDC, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_ISP_VRA, "gout_cmu_isp_vra", "mout_cmu_isp_vra",
+	     CLK_CON_GAT_GATE_CLKCMU_ISP_VRA, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
+	     CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_MFC_WFD, "gout_cmu_mfc_wfd", "mout_cmu_mfc_wfd",
+	     CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
+	     CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_MODEM_SHARED0, "gout_cmu_modem_shared0", "dout_cmu_shared0_div2",
+	     CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_MODEM_SHARED1, "gout_cmu_modem_shared1", "dout_cmu_shared1_div2",
+	     CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_PERI_BUS, "gout_cmu_peri_bus", "mout_cmu_peri_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_PERI_IP, "gout_cmu_peri_ip", "mout_cmu_peri_ip",
+	     CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_PERI_UART, "gout_cmu_peri_uart", "mout_cmu_peri_uart",
+	     CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
+	GATE(CLK_GOUT_CMU_USB_BUS, "gout_cmu_usb_bus", "mout_cmu_usb_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_USB_BUS, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_USB_DPGTC, "gout_cmu_usb_dpgtc", "mout_cmu_usb_dpgtc",
+	     CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_USB_USB30DRD, "gout_cmu_usb_usb30drd", "mout_cmu_usb_usb30drd",
+	     CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_VIPX1_BUS, "gout_cmu_vipx1_bus", "mout_cmu_vipx1_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMU_VIPX2_BUS, "gout_cmu_vipx2_bus", "mout_cmu_vipx2_bus",
+	     CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info top_cmu_info __initconst = {
+	.pll_clks = top_pll_clks,
+	.nr_pll_clks = ARRAY_SIZE(top_pll_clks),
+	.mux_clks = top_mux_clks,
+	.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
+	.div_clks = top_div_clks,
+	.nr_div_clks = ARRAY_SIZE(top_div_clks),
+	.fixed_factor_clks = top_ffactor_clks,
+	.nr_fixed_factor_clks = ARRAY_SIZE(top_ffactor_clks),
+	.gate_clks = top_gate_clks,
+	.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
+	.nr_clk_ids = CLKS_NR_TOP,
+	.clk_regs = top_clk_regs,
+	.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
+};
+
+static void __init exynos9610_cmu_top_init(struct device_node *np)
+{
+	exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
+}
+
+/* Register CMU_TOP early, as it's a dependency for other early domains */
+CLK_OF_DECLARE(exynos9610_cmu_top, "samsung,exynos9610-cmu-top",
+	       exynos9610_cmu_top_init);
+
+/* CMU_CPUCL0 */
+#define PLL_LOCKTIME_PLL_CPUCL0					0x0000
+#define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER			0x0100
+#define PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_USER			0x0108
+#define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER			0x0120
+#define PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER			0x0128
+#define PLL_CON0_PLL_CPUCL0					0x0140
+#define CLK_CON_MUX_MUX_CLK_CPUCL0_PLL				0x1000
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK			0x1800
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK			0x1804
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG			0x1808
+#define CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF			0x180c
+#define CLK_CON_DIV_DIV_CLK_CPUCL0_CPU				0x1810
+#define CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK				0x1814
+#define CLK_CON_GAT_CLK_CPUCL0_CMU_PCLK				0x2000
+#define CLK_CON_GAT_CLK_CPUCL0_HPM_TARGETCLK_C			0x2004
+#define CLK_CON_GAT_CLK_CPUCL0_OSCCLK_CLK			0x2008
+#define CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU			0x2010
+#define CLK_CON_GAT_GOUT_CPUCL0_ADM_APB_G_CSSYS_CORE_PCLKM	0x2014
+#define CLK_CON_GAT_GOUT_CPUCL0_ADS_AHB_G_CSSYS_FSYS_HCLKS	0x2018
+#define CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_CSSYS_CPUCL1_PCLKS	0x201c
+#define CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_P8Q_PCLKS		0x2020
+#define CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL0_PCLKM	0x2024
+#define CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL1_PCLKM	0x2028
+#define CLK_CON_GAT_GOUT_CPUCL0_BUSIF_HPMCPUCL0_PCLK		0x202c
+#define CLK_CON_GAT_GOUT_CPUCL0_CSSYS_DBG_PCLKDBG		0x2030
+#define CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL0_PCLK		0x2034
+#define CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL1_PCLK		0x2038
+#define CLK_CON_GAT_GOUT_CPUCL0_LHM_AXI_P_CPUCL0_CLK		0x203c
+#define CLK_CON_GAT_GOUT_CPUCL0_LHS_AXI_D_CSSYS_CLK		0x2040
+#define CLK_CON_GAT_GOUT_CPUCL0_DBG_CLK				0x2044
+#define CLK_CON_GAT_GOUT_CPUCL0_PCLK_CLK			0x2048
+#define CLK_CON_GAT_GOUT_CPUCL0_SECJTAG_CLK			0x204c
+#define CLK_CON_GAT_GOUT_CPUCL0_SYSREG_PCLK			0x2050
+
+static const unsigned long cpucl0_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_CPUCL0,
+	PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
+	PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_USER,
+	PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
+	PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER,
+	PLL_CON0_PLL_CPUCL0,
+	CLK_CON_MUX_MUX_CLK_CPUCL0_PLL,
+	CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
+	CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK,
+	CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG,
+	CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF,
+	CLK_CON_DIV_DIV_CLK_CPUCL0_CPU,
+	CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK,
+	CLK_CON_GAT_CLK_CPUCL0_CMU_PCLK,
+	CLK_CON_GAT_CLK_CPUCL0_HPM_TARGETCLK_C,
+	CLK_CON_GAT_CLK_CPUCL0_OSCCLK_CLK,
+	CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU,
+	CLK_CON_GAT_GOUT_CPUCL0_ADM_APB_G_CSSYS_CORE_PCLKM,
+	CLK_CON_GAT_GOUT_CPUCL0_ADS_AHB_G_CSSYS_FSYS_HCLKS,
+	CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_CSSYS_CPUCL1_PCLKS,
+	CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_P8Q_PCLKS,
+	CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL0_PCLKM,
+	CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL1_PCLKM,
+	CLK_CON_GAT_GOUT_CPUCL0_BUSIF_HPMCPUCL0_PCLK,
+	CLK_CON_GAT_GOUT_CPUCL0_CSSYS_DBG_PCLKDBG,
+	CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL0_PCLK,
+	CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL1_PCLK,
+	CLK_CON_GAT_GOUT_CPUCL0_LHM_AXI_P_CPUCL0_CLK,
+	CLK_CON_GAT_GOUT_CPUCL0_LHS_AXI_D_CSSYS_CLK,
+	CLK_CON_GAT_GOUT_CPUCL0_DBG_CLK,
+	CLK_CON_GAT_GOUT_CPUCL0_PCLK_CLK,
+	CLK_CON_GAT_GOUT_CPUCL0_SECJTAG_CLK,
+	CLK_CON_GAT_GOUT_CPUCL0_SYSREG_PCLK,
+};
+
+static const struct samsung_pll_rate_table pll_cpucl0_rate_table[] __initconst = {
+	PLL_35XX_RATE(26 * MHZ, 1049750000U, 323, 4, 1),
+	PLL_35XX_RATE(26 * MHZ, 1449500000U, 223, 4, 0),
+	PLL_35XX_RATE(26 * MHZ, 1850333333U, 427, 6, 0),
+	PLL_35XX_RATE(26 * MHZ, 300083333U, 277, 6, 2),
+	PLL_35XX_RATE(26 * MHZ, 600166666U, 277, 6, 1),
+};
+
+static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
+	PLL(pll_1051x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_CPUCL0, PLL_CON0_PLL_CPUCL0, pll_cpucl0_rate_table),
+};
+
+PNAME(mout_pll_cpucl0_dbg_user_p)	= { "oscclk",
+					    "dout_cmu_cpucl0_dbg" };
+PNAME(mout_pll_cpucl0_switch_user_p)	= { "oscclk",
+					    "dout_cmu_cpucl0_switch" };
+PNAME(mout_clk_cpucl0_pll_p)		= { "fout_cpucl0_pll",
+					    "mout_pll_cpucl0_switch_user" };
+
+static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PLL_CPUCL0_DBG_USER, "mout_pll_cpucl0_dbg_user", mout_pll_cpucl0_dbg_user_p,
+	    PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_CPUCL0_SWITCH_USER, "mout_pll_cpucl0_switch_user",
+	    mout_pll_cpucl0_switch_user_p, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1),
+	MUX(CLK_MOUT_CLK_CPUCL0_PLL, "mout_clk_cpucl0_pll", mout_clk_cpucl0_pll_p,
+	    CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0, 1),
+};
+
+static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
+	DIV(CLK_DOUT_CLK_CLUSTER0_ACLK, "dout_clk_cluster0_aclk", "gout_clk_cluster0_cpu",
+	    CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4),
+	DIV(CLK_DOUT_CLK_CLUSTER0_CNTCLK, "dout_clk_cluster0_cntclk", "gout_clk_cluster0_cpu",
+	    CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK, 0, 4),
+	DIV(CLK_DOUT_CLK_CLUSTER0_PCLKDBG, "dout_clk_cluster0_pclkdbg", "gout_clk_cluster0_cpu",
+	    CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0, 4),
+	DIV(CLK_DOUT_CLK_CPUCL0_CMUREF, "dout_clk_cpucl0_cmuref", "dout_clk_cpucl0_cpu",
+	    CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0, 3),
+	DIV(CLK_DOUT_CLK_CPUCL0_CPU, "dout_clk_cpucl0_cpu", "mout_clk_cpucl0_pll",
+	    CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 0),
+	DIV(CLK_DOUT_CLK_CPUCL0_PCLK, "dout_clk_cpucl0_pclk", "dout_clk_cpucl0_cpu",
+	    CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0, 4),
+};
+
+static const struct samsung_gate_clock cpucl0_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_CLK_CPUCL0_CMU_PCLK, "gout_clk_cpucl0_cmu_pclk",
+	     "dout_clk_cpucl0_pclk", CLK_CON_GAT_CLK_CPUCL0_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_CPUCL0_HPM_TARGETCLK_C, "gout_clk_cpucl0_hpm_targetclk_c",
+	     "dout_cmu_hpm", CLK_CON_GAT_CLK_CPUCL0_HPM_TARGETCLK_C, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_CPUCL0_OSCCLK_CLK, "gout_clk_cpucl0_oscclk_clk",
+	     "oscclk", CLK_CON_GAT_CLK_CPUCL0_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_CLUSTER0_CPU, "gout_clk_cluster0_cpu",
+	     "dout_clk_cpucl0_cpu", CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_ADM_APB_G_CSSYS_CORE_PCLKM, "gout_cpucl0_adm_apb_g_cssys_core_pclkm",
+	     "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_ADM_APB_G_CSSYS_CORE_PCLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_ADS_AHB_G_CSSYS_FSYS_HCLKS, "gout_cpucl0_ads_ahb_g_cssys_fsys_hclks",
+	     "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_ADS_AHB_G_CSSYS_FSYS_HCLKS,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_ADS_APB_G_CSSYS_CPUCL1_PCLKS,
+	     "gout_cpucl0_ads_apb_g_cssys_cpucl1_pclks", "mout_pll_cpucl0_dbg_user",
+	     CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_CSSYS_CPUCL1_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_ADS_APB_G_P8Q_PCLKS, "gout_cpucl0_ads_apb_g_p8q_pclks",
+	     "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_P8Q_PCLKS,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL0_PCLKM,
+	     "gout_cpucl0_ad_apb_p_dump_pc_cpucl0_pclkm", "mout_pll_cpucl0_dbg_user",
+	     CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL0_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL1_PCLKM,
+	     "gout_cpucl0_ad_apb_p_dump_pc_cpucl1_pclkm", "mout_pll_cpucl0_dbg_user",
+	     CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL1_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_BUSIF_HPMCPUCL0_PCLK, "gout_cpucl0_busif_hpmcpucl0_pclk",
+	     "dout_clk_cpucl0_pclk", CLK_CON_GAT_GOUT_CPUCL0_BUSIF_HPMCPUCL0_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_CSSYS_DBG_PCLKDBG, "gout_cpucl0_cssys_dbg_pclkdbg",
+	     "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_CSSYS_DBG_PCLKDBG,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_DUMP_PC_CPUCL0_PCLK, "gout_cpucl0_dump_pc_cpucl0_pclk",
+	     "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL0_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_DUMP_PC_CPUCL1_PCLK, "gout_cpucl0_dump_pc_cpucl1_pclk",
+	     "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL1_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_LHM_AXI_P_CPUCL0_CLK, "gout_cpucl0_lhm_axi_p_cpucl0_clk",
+	     "dout_clk_cpucl0_pclk", CLK_CON_GAT_GOUT_CPUCL0_LHM_AXI_P_CPUCL0_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_LHS_AXI_D_CSSYS_CLK, "gout_cpucl0_lhs_axi_d_cssys_clk",
+	     "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_LHS_AXI_D_CSSYS_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_DBG_CLK, "gout_cpucl0_dbg_clk",
+	     "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_DBG_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_PCLK_CLK, "gout_cpucl0_pclk_clk",
+	     "dout_clk_cpucl0_pclk", CLK_CON_GAT_GOUT_CPUCL0_PCLK_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_SECJTAG_CLK, "gout_cpucl0_secjtag_clk", "mout_pll_cpucl0_dbg_user",
+	     CLK_CON_GAT_GOUT_CPUCL0_SECJTAG_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL0_SYSREG_PCLK, "gout_cpucl0_sysreg_pclk",
+	     "dout_clk_cpucl0_pclk", CLK_CON_GAT_GOUT_CPUCL0_SYSREG_PCLK, 21, 0, 0),
+};
+
+static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
+	.pll_clks = cpucl0_pll_clks,
+	.nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
+	.mux_clks = cpucl0_mux_clks,
+	.nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
+	.div_clks = cpucl0_div_clks,
+	.nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
+	.gate_clks = cpucl0_gate_clks,
+	.nr_gate_clks = ARRAY_SIZE(cpucl0_gate_clks),
+	.nr_clk_ids = CLKS_NR_CPUCL0,
+	.clk_regs = cpucl0_clk_regs,
+	.nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
+};
+
+static void __init exynos9610_cmu_cpucl0_init(struct device_node *np)
+{
+	exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos9610_cmu_cpucl0, "samsung,exynos9610-cmu-cpucl0",
+	       exynos9610_cmu_cpucl0_init);
+
+/* CMU_CPUCL1 */
+#define PLL_LOCKTIME_PLL_CPUCL1					0x0000
+#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER			0x0100
+#define PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER			0x0108
+#define PLL_CON0_PLL_CPUCL1					0x0120
+#define CLK_CON_MUX_MUX_CLK_CPUCL1_PLL				0x1000
+#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK			0x1800
+#define CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK			0x1804
+#define CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF			0x180c
+#define CLK_CON_DIV_DIV_CLK_CPUCL1_CPU				0x1810
+#define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK				0x1814
+#define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG			0x1818
+#define CLK_CON_GAT_CLK_CPUCL1_CMU_PCLK				0x2000
+#define CLK_CON_GAT_CLK_CPUCL1_HPM_TARGETCLK_C			0x2004
+#define CLK_CON_GAT_CLK_CPUCL1_OSCCLK_CLK			0x2008
+#define CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU			0x2010
+#define CLK_CON_GAT_GOUT_CPUCL1_ADM_APB_G_CSSYS_CPUCL1_PCLKM	0x2014
+#define CLK_CON_GAT_GOUT_CPUCL1_BUSIF_HPMCPUCL1_PCLK		0x2018
+#define CLK_CON_GAT_GOUT_CPUCL1_LHM_AXI_P_CPUCL1_CLK		0x201c
+#define CLK_CON_GAT_GOUT_CPUCL1_LHS_ACE_D_CLK			0x2020
+#define CLK_CON_GAT_GOUT_CPUCL1_ACLK_CLK			0x2024
+#define CLK_CON_GAT_GOUT_CPUCL1_PCLKDBG_CLK			0x2028
+#define CLK_CON_GAT_GOUT_CPUCL1_PCLK_CLK			0x202c
+#define CLK_CON_GAT_GOUT_CPUCL1_SYSREG_PCLK			0x2030
+
+static const unsigned long cpucl1_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_CPUCL1,
+	PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
+	PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER,
+	PLL_CON0_PLL_CPUCL1,
+	CLK_CON_MUX_MUX_CLK_CPUCL1_PLL,
+	CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
+	CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK,
+	CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF,
+	CLK_CON_DIV_DIV_CLK_CPUCL1_CPU,
+	CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK,
+	CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG,
+	CLK_CON_GAT_CLK_CPUCL1_CMU_PCLK,
+	CLK_CON_GAT_CLK_CPUCL1_HPM_TARGETCLK_C,
+	CLK_CON_GAT_CLK_CPUCL1_OSCCLK_CLK,
+	CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU,
+	CLK_CON_GAT_GOUT_CPUCL1_ADM_APB_G_CSSYS_CPUCL1_PCLKM,
+	CLK_CON_GAT_GOUT_CPUCL1_BUSIF_HPMCPUCL1_PCLK,
+	CLK_CON_GAT_GOUT_CPUCL1_LHM_AXI_P_CPUCL1_CLK,
+	CLK_CON_GAT_GOUT_CPUCL1_LHS_ACE_D_CLK,
+	CLK_CON_GAT_GOUT_CPUCL1_ACLK_CLK,
+	CLK_CON_GAT_GOUT_CPUCL1_PCLKDBG_CLK,
+	CLK_CON_GAT_GOUT_CPUCL1_PCLK_CLK,
+	CLK_CON_GAT_GOUT_CPUCL1_SYSREG_PCLK,
+};
+
+static const struct samsung_pll_rate_table pll_cpucl1_rate_table[] __initconst = {
+	PLL_35XX_RATE(26 * MHZ, 1499333333U, 346, 3, 1),
+	PLL_35XX_RATE(26 * MHZ, 1898000000U, 292, 4, 0),
+	PLL_35XX_RATE(26 * MHZ, 2400666666U, 277, 3, 0),
+	PLL_35XX_RATE(26 * MHZ, 549900000U, 423, 5, 2),
+	PLL_35XX_RATE(26 * MHZ, 850200000U, 327, 5, 1),
+};
+
+static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
+	PLL(pll_1051x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_CPUCL1, PLL_CON0_PLL_CPUCL1, pll_cpucl1_rate_table),
+};
+
+PNAME(mout_pll_cpucl1_switch_user_p)	= { "oscclk",
+					    "dout_cmu_cpucl1_switch" };
+PNAME(mout_clk_cpucl1_pll_p)		= { "fout_cpucl1_pll",
+					    "mout_pll_cpucl1_switch_user" };
+
+static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PLL_CPUCL1_SWITCH_USER, "mout_pll_cpucl1_switch_user",
+	    mout_pll_cpucl1_switch_user_p, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
+	    4, 1),
+	MUX(CLK_MOUT_CLK_CPUCL1_PLL, "mout_clk_cpucl1_pll", mout_clk_cpucl1_pll_p,
+	    CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0, 1),
+};
+
+static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
+	DIV(CLK_DOUT_CLK_CLUSTER1_ACLK, "dout_clk_cluster1_aclk", "gout_clk_cluster1_cpu",
+	    CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4),
+	DIV(CLK_DOUT_CLK_CLUSTER1_CNTCLK, "dout_clk_cluster1_cntclk", "gout_clk_cluster1_cpu",
+	    CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK, 0, 4),
+	DIV(CLK_DOUT_CLK_CPUCL1_CMUREF, "dout_clk_cpucl1_cmuref", "dout_clk_cpucl1_cpu",
+	    CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0, 4),
+	DIV(CLK_DOUT_CLK_CPUCL1_CPU, "dout_clk_cpucl1_cpu", "mout_clk_cpucl1_pll",
+	    CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 0),
+	DIV(CLK_DOUT_CLK_CPUCL1_PCLK, "dout_clk_cpucl1_pclk", "dout_clk_cpucl1_cpu",
+	    CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0, 4),
+	DIV(CLK_DOUT_CLK_CPUCL1_PCLKDBG, "dout_clk_cpucl1_pclkdbg", "dout_clk_cpucl1_cpu",
+	    CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG, 0, 4),
+};
+
+static const struct samsung_gate_clock cpucl1_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_CLK_CPUCL1_CMU_PCLK, "gout_clk_cpucl1_cmu_pclk",
+	     "dout_clk_cpucl1_pclk", CLK_CON_GAT_CLK_CPUCL0_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_CPUCL1_HPM_TARGETCLK_C, "gout_clk_cpucl1_hpm_targetclk_c",
+	     "dout_cmu_hpm", CLK_CON_GAT_CLK_CPUCL1_HPM_TARGETCLK_C, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_CPUCL1_OSCCLK_CLK, "gout_clk_cpucl1_oscclk_clk",
+	     "oscclk", CLK_CON_GAT_CLK_CPUCL1_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_CLUSTER1_CPU, "gout_clk_cluster1_cpu",
+	     "dout_clk_cpucl1_cpu", CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL1_ADM_APB_G_CSSYS_CPUCL1_PCLKM,
+	     "gout_cpucl1_adm_apb_g_cssys_cpucl1_pclkm", "dout_clk_cpucl1_pclkdbg",
+	     CLK_CON_GAT_GOUT_CPUCL1_ADM_APB_G_CSSYS_CPUCL1_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL1_BUSIF_HPMCPUCL1_PCLK, "gout_cpucl0_busif_hpmcpucl1_pclk",
+	     "dout_clk_cpucl1_pclk", CLK_CON_GAT_GOUT_CPUCL1_BUSIF_HPMCPUCL1_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL1_LHM_AXI_P_CPUCL1_CLK, "gout_cpucl1_lhm_axi_p_cpucl1_clk",
+	     "dout_clk_cpucl1_pclk", CLK_CON_GAT_GOUT_CPUCL1_LHM_AXI_P_CPUCL1_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL1_LHS_ACE_D_CLK, "gout_cpucl1_lhs_ace_d_clk",
+	     "dout_clk_cluster1_aclk", CLK_CON_GAT_GOUT_CPUCL1_LHS_ACE_D_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL1_ACLK_CLK, "gout_cpucl1_aclk_clk",
+	     "dout_clk_cluster1_aclk", CLK_CON_GAT_GOUT_CPUCL1_ACLK_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL1_PCLKDBG_CLK, "gout_cpucl1_pclkdbg_clk",
+	     "dout_clk_cpucl1_pclkdbg", CLK_CON_GAT_GOUT_CPUCL1_PCLKDBG_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL1_PCLK_CLK, "gout_cpucl1_pclk_clk",
+	     "dout_clk_cpucl1_pclk", CLK_CON_GAT_GOUT_CPUCL1_PCLK_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CPUCL1_SYSREG_PCLK, "gout_cpucl1_sysreg_pclk",
+	     "dout_clk_cpucl1_pclk", CLK_CON_GAT_GOUT_CPUCL1_SYSREG_PCLK,
+	     21, 0, 0),
+};
+
+static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
+	.pll_clks = cpucl1_pll_clks,
+	.nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
+	.mux_clks = cpucl1_mux_clks,
+	.nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
+	.div_clks = cpucl1_div_clks,
+	.nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
+	.gate_clks = cpucl1_gate_clks,
+	.nr_gate_clks = ARRAY_SIZE(cpucl1_gate_clks),
+	.nr_clk_ids = CLKS_NR_CPUCL1,
+	.clk_regs = cpucl1_clk_regs,
+	.nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
+};
+
+static void __init exynos9610_cmu_cpucl1_init(struct device_node *np)
+{
+	exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos9610_cmu_cpucl1, "samsung,exynos9610-cmu-cpucl1",
+	       exynos9610_cmu_cpucl1_init);
+
+/* CMU_PERI */
+#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER			0x0100 // old
+#define PLL_CON2_MUX_CLKCMU_PERI_BUS_USER			0x0108
+#define PLL_CON0_MUX_CLKCMU_PERI_IP_USER			0x0120 // old
+#define PLL_CON2_MUX_CLKCMU_PERI_IP_USER			0x0128
+#define PLL_CON0_MUX_CLKCMU_PERI_UART_USER			0x0140
+#define PLL_CON2_MUX_CLKCMU_PERI_UART_USER			0x0148
+#define CLK_CON_DIV_DIV_CLK_PERI_I2C				0x1800
+#define CLK_CON_DIV_DIV_CLK_PERI_SPI0				0x1804 // old
+#define CLK_CON_DIV_DIV_CLK_PERI_SPI1				0x1808 // old
+#define CLK_CON_DIV_DIV_CLK_PERI_SPI2				0x180c // old
+#define CLK_CON_DIV_DIV_CLK_PERI_USI_I2C			0x1814
+#define CLK_CON_DIV_DIV_CLK_PERI_USI_USI			0x1818
+#define CLK_CON_GAT_CLK_PERI_CMU_PCLK				0x2000
+#define CLK_CON_GAT_CLK_PERI_OSCCLK_CLK				0x2004
+#define CLK_CON_GAT_GATE_CLK_PERI_I2C				0x2008
+#define CLK_CON_GAT_GATE_CLK_PERI_SPI0				0x200c // old
+#define CLK_CON_GAT_GATE_CLK_PERI_SPI1				0x2010 // old
+#define CLK_CON_GAT_GATE_CLK_PERI_SPI2				0x2014 // old
+#define CLK_CON_GAT_GATE_CLK_PERI_USI_I2C			0x2018
+#define CLK_CON_GAT_GATE_CLK_PERI_USI_USI			0x201c
+#define CLK_CON_GAT_GOUT_PERI_AXI2AHB_MSD32_ACLK		0x2020
+#define CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK			0x2024
+#define CLK_CON_GAT_GOUT_PERI_CAMI2C_0_IPCLK			0x2028
+#define CLK_CON_GAT_GOUT_PERI_CAMI2C_0_PCLK			0x202c
+#define CLK_CON_GAT_GOUT_PERI_CAMI2C_1_IPCLK			0x2030
+#define CLK_CON_GAT_GOUT_PERI_CAMI2C_1_PCLK			0x2034
+#define CLK_CON_GAT_GOUT_PERI_CAMI2C_2_IPCLK			0x2038
+#define CLK_CON_GAT_GOUT_PERI_CAMI2C_2_PCLK			0x203c
+#define CLK_CON_GAT_GOUT_PERI_CAMI2C_3_IPCLK			0x2040
+#define CLK_CON_GAT_GOUT_PERI_CAMI2C_3_PCLK			0x2044
+#define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK			0x204c
+#define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK			0x2050
+#define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK			0x2054
+#define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK			0x2058
+#define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK			0x205c
+#define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK			0x2060
+#define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK			0x2064
+#define CLK_CON_GAT_GOUT_PERI_GPIO_PCLK				0x2048
+#define CLK_CON_GAT_GOUT_PERI_LHM_AXI_P_PERI_CLK		0x2068
+#define CLK_CON_GAT_GOUT_PERI_MCT_PCLK				0x206c // old
+#define CLK_CON_GAT_GOUT_PERI_OTP_CON_TOP_PCLK			0x2070
+#define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK_S0			0x2074
+#define CLK_CON_GAT_GOUT_PERI_BUS_CLK				0x2078
+#define CLK_CON_GAT_GOUT_PERI_I2C_CLK				0x207c
+#define CLK_CON_GAT_GOUT_PERI_SPI_0_CLK				0x2080
+#define CLK_CON_GAT_GOUT_PERI_SPI_1_CLK				0x2084
+#define CLK_CON_GAT_GOUT_PERI_SPI_2_CLK				0x2088
+#define CLK_CON_GAT_GOUT_PERI_UART_CLK				0x208c
+#define CLK_CON_GAT_GOUT_PERI_USI00_I2C_CLK			0x2090
+#define CLK_CON_GAT_GOUT_PERI_USI00_USI_CLK			0x2094
+#define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK			0x2098 // old
+#define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK			0x209c // old
+#define CLK_CON_GAT_GOUT_PERI_SPI_1_IPCLK			0x20a0 // old
+#define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK			0x20a4 // old
+#define CLK_CON_GAT_GOUT_PERI_SPI_2_IPCLK			0x20a8 // old
+#define CLK_CON_GAT_GOUT_PERI_SPI_2_PCLK			0x20ac // old
+#define CLK_CON_GAT_GOUT_PERI_SYSREG_PCLK			0x20b0
+#define CLK_CON_GAT_GOUT_PERI_UART_IPCLK			0x20b4
+#define CLK_CON_GAT_GOUT_PERI_UART_PCLK				0x20b8
+#define CLK_CON_GAT_GOUT_PERI_USI00_I2C_IPCLK			0x20bc
+#define CLK_CON_GAT_GOUT_PERI_USI00_I2C_PCLK			0x20c0
+#define CLK_CON_GAT_GOUT_PERI_USI00_USI_IPCLK			0x20c4
+#define CLK_CON_GAT_GOUT_PERI_USI00_USI_PCLK			0x20c8
+#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK			0x20cc
+#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK			0x20d0
+
+static const unsigned long peri_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
+	PLL_CON2_MUX_CLKCMU_PERI_BUS_USER,
+	PLL_CON0_MUX_CLKCMU_PERI_IP_USER,
+	PLL_CON2_MUX_CLKCMU_PERI_IP_USER,
+	PLL_CON0_MUX_CLKCMU_PERI_UART_USER,
+	PLL_CON2_MUX_CLKCMU_PERI_UART_USER,
+	CLK_CON_DIV_DIV_CLK_PERI_I2C,
+	CLK_CON_DIV_DIV_CLK_PERI_SPI0,
+	CLK_CON_DIV_DIV_CLK_PERI_SPI1,
+	CLK_CON_DIV_DIV_CLK_PERI_SPI2,
+	CLK_CON_DIV_DIV_CLK_PERI_USI_I2C,
+	CLK_CON_DIV_DIV_CLK_PERI_USI_USI,
+	CLK_CON_GAT_CLK_PERI_CMU_PCLK,
+	CLK_CON_GAT_CLK_PERI_OSCCLK_CLK,
+	CLK_CON_GAT_GATE_CLK_PERI_I2C,
+	CLK_CON_GAT_GATE_CLK_PERI_SPI0,
+	CLK_CON_GAT_GATE_CLK_PERI_SPI1,
+	CLK_CON_GAT_GATE_CLK_PERI_SPI2,
+	CLK_CON_GAT_GATE_CLK_PERI_USI_I2C,
+	CLK_CON_GAT_GATE_CLK_PERI_USI_USI,
+	CLK_CON_GAT_GOUT_PERI_AXI2AHB_MSD32_ACLK,
+	CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK,
+	CLK_CON_GAT_GOUT_PERI_CAMI2C_0_IPCLK,
+	CLK_CON_GAT_GOUT_PERI_CAMI2C_0_PCLK,
+	CLK_CON_GAT_GOUT_PERI_CAMI2C_1_IPCLK,
+	CLK_CON_GAT_GOUT_PERI_CAMI2C_1_PCLK,
+	CLK_CON_GAT_GOUT_PERI_CAMI2C_2_IPCLK,
+	CLK_CON_GAT_GOUT_PERI_CAMI2C_2_PCLK,
+	CLK_CON_GAT_GOUT_PERI_CAMI2C_3_IPCLK,
+	CLK_CON_GAT_GOUT_PERI_CAMI2C_3_PCLK,
+	CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
+	CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
+	CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
+	CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
+	CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
+	CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
+	CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
+	CLK_CON_GAT_GOUT_PERI_GPIO_PCLK,
+	CLK_CON_GAT_GOUT_PERI_LHM_AXI_P_PERI_CLK,
+	CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
+	CLK_CON_GAT_GOUT_PERI_OTP_CON_TOP_PCLK,
+	CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK_S0,
+	CLK_CON_GAT_GOUT_PERI_BUS_CLK,
+	CLK_CON_GAT_GOUT_PERI_I2C_CLK,
+	CLK_CON_GAT_GOUT_PERI_SPI_0_CLK,
+	CLK_CON_GAT_GOUT_PERI_SPI_1_CLK,
+	CLK_CON_GAT_GOUT_PERI_SPI_2_CLK,
+	CLK_CON_GAT_GOUT_PERI_UART_CLK,
+	CLK_CON_GAT_GOUT_PERI_USI00_I2C_CLK,
+	CLK_CON_GAT_GOUT_PERI_USI00_USI_CLK,
+	CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK,
+	CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
+	CLK_CON_GAT_GOUT_PERI_SPI_1_IPCLK,
+	CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK,
+	CLK_CON_GAT_GOUT_PERI_SPI_2_IPCLK,
+	CLK_CON_GAT_GOUT_PERI_SPI_2_PCLK,
+	CLK_CON_GAT_GOUT_PERI_SYSREG_PCLK,
+	CLK_CON_GAT_GOUT_PERI_UART_IPCLK,
+	CLK_CON_GAT_GOUT_PERI_UART_PCLK,
+	CLK_CON_GAT_GOUT_PERI_USI00_I2C_IPCLK,
+	CLK_CON_GAT_GOUT_PERI_USI00_I2C_PCLK,
+	CLK_CON_GAT_GOUT_PERI_USI00_USI_IPCLK,
+	CLK_CON_GAT_GOUT_PERI_USI00_USI_PCLK,
+	CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK,
+	CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK,
+};
+
+PNAME(mout_pll_peri_bus_user_p)		= { "oscclk", "dout_cmu_peri_bus" };
+PNAME(mout_pll_peri_ip_user_p)		= { "oscclk", "dout_cmu_peri_ip" };
+PNAME(mout_pll_peri_uart_user_p)	= { "oscclk", "dout_cmu_peri_uart" };
+
+static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PLL_PERI_BUS_USER, "mout_pll_peri_bus_user", mout_pll_peri_bus_user_p,
+	    PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_PERI_IP_USER, "mout_pll_peri_ip_user", mout_pll_peri_ip_user_p,
+	    PLL_CON0_MUX_CLKCMU_PERI_IP_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_PERI_UART_USER, "mout_pll_peri_uart_user", mout_pll_peri_uart_user_p,
+	    PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1),
+};
+
+static const struct samsung_div_clock peri_div_clks[] __initconst = {
+	DIV(CLK_DOUT_CLK_PERI_I2C, "dout_clk_peri_i2c", "gout_clk_peri_i2c",
+	    CLK_CON_DIV_DIV_CLK_PERI_I2C, 0, 8),
+	DIV(CLK_DOUT_CLK_PERI_SPI0, "dout_clk_peri_spi0", "gout_clk_peri_spi0",
+	    CLK_CON_DIV_DIV_CLK_PERI_SPI0, 0, 8),
+	DIV(CLK_DOUT_CLK_PERI_SPI1, "dout_clk_peri_spi1", "gout_clk_peri_spi1",
+	    CLK_CON_DIV_DIV_CLK_PERI_SPI1, 0, 8),
+	DIV(CLK_DOUT_CLK_PERI_SPI2, "dout_clk_peri_spi2", "gout_clk_peri_spi2",
+	    CLK_CON_DIV_DIV_CLK_PERI_SPI2, 0, 8),
+	DIV(CLK_DOUT_CLK_PERI_USI_I2C, "dout_clk_peri_usi_i2c", "gout_clk_peri_usi_i2c",
+	    CLK_CON_DIV_DIV_CLK_PERI_USI_I2C, 0, 4),
+	DIV(CLK_DOUT_CLK_PERI_USI_USI, "dout_clk_peri_usi_usi", "gout_clk_peri_usi_usi",
+	    CLK_CON_DIV_DIV_CLK_PERI_USI_USI, 0, 8),
+};
+
+static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_CLK_PERI_I2C, "gout_clk_peri_i2c", "mout_pll_peri_ip_user",
+	     CLK_CON_GAT_GATE_CLK_PERI_I2C, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_PERI_SPI0, "gout_clk_peri_spi0", "mout_pll_peri_ip_user",
+	     CLK_CON_GAT_GATE_CLK_PERI_SPI0, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_PERI_SPI1, "gout_clk_peri_spi1", "mout_pll_peri_ip_user",
+	     CLK_CON_GAT_GATE_CLK_PERI_SPI1, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_PERI_SPI2, "gout_clk_peri_spi2", "mout_pll_peri_ip_user",
+	     CLK_CON_GAT_GATE_CLK_PERI_SPI2, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_PERI_USI_I2C, "gout_clk_peri_usi_i2c", "mout_pll_peri_ip_user",
+	     CLK_CON_GAT_GATE_CLK_PERI_USI_I2C, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_PERI_USI_USI, "gout_clk_peri_usi_usi", "mout_pll_peri_ip_user",
+	     CLK_CON_GAT_GATE_CLK_PERI_USI_USI, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_AXI2AHB_MSD32_ACLK, "gout_peri_axi2ahb_msd32_aclk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_AXI2AHB_MSD32_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_BUSIF_TMU_PCLK, "gout_peri_busif_tmu_pclk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_CAMI2C_0_IPCLK, "gout_peri_cami2c_0_ipclk",
+	     "dout_clk_peri_i2c", CLK_CON_GAT_GOUT_PERI_CAMI2C_0_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_CAMI2C_0_PCLK, "gout_peri_cami2c_0_pclk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_CAMI2C_0_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_CAMI2C_1_IPCLK, "gout_peri_cami2c_1_ipclk",
+	     "dout_clk_peri_i2c", CLK_CON_GAT_GOUT_PERI_CAMI2C_1_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_CAMI2C_1_PCLK, "gout_peri_cami2c_1_pclk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_CAMI2C_1_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_CAMI2C_2_IPCLK, "gout_peri_cami2c_2_ipclk",
+	     "dout_clk_peri_i2c", CLK_CON_GAT_GOUT_PERI_CAMI2C_2_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_CAMI2C_2_PCLK, "gout_peri_cami2c_2_pclk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_CAMI2C_2_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_CAMI2C_3_IPCLK, "gout_peri_cami2c_3_ipclk",
+	     "dout_clk_peri_i2c", CLK_CON_GAT_GOUT_PERI_CAMI2C_3_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_CAMI2C_3_PCLK, "gout_peri_cami2c_3_pclk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_CAMI2C_3_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_I2C_0_PCLK, "gout_peri_i2c_0_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_I2C_1_PCLK, "gout_peri_i2c_1_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_I2C_2_PCLK, "gout_peri_i2c_2_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_I2C_3_PCLK, "gout_peri_i2c_3_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_I2C_4_PCLK, "gout_peri_i2c_4_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_I2C_5_PCLK, "gout_peri_i2c_5_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_I2C_6_PCLK, "gout_peri_i2c_6_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_GPIO_PCLK, "gout_peri_gpio_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_LHM_AXI_P_PERI_CLK, "gout_peri_lhm_axi_p_peri_clk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_LHM_AXI_P_PERI_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_MCT_PCLK, "gout_peri_mct_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
+	GATE(CLK_GOUT_PERI_OTP_CON_TOP_PCLK, "gout_peri_otp_con_top_pclk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_OTP_CON_TOP_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0, "gout_peri_pwm_motor_pclk_s0",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK_S0,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_BUS_CLK, "gout_peri_bus_clk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_BUS_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_I2C_CLK, "gout_peri_i2c_clk", "dout_clk_peri_i2c",
+	     CLK_CON_GAT_GOUT_PERI_I2C_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_SPI_0_CLK, "gout_peri_spi_0_clk", "dout_clk_peri_spi0",
+	     CLK_CON_GAT_GOUT_PERI_SPI_0_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_SPI_1_CLK, "gout_peri_spi_1_clk", "dout_clk_peri_spi1",
+	     CLK_CON_GAT_GOUT_PERI_SPI_1_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_SPI_2_CLK, "gout_peri_spi_2_clk", "dout_clk_peri_spi2",
+	     CLK_CON_GAT_GOUT_PERI_SPI_2_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_UART_CLK, "gout_peri_uart_clk", "mout_pll_peri_uart_user",
+	     CLK_CON_GAT_GOUT_PERI_UART_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_USI00_I2C_CLK, "gout_peri_usi00_i2c_clk",
+	     "dout_clk_peri_usi_i2c", CLK_CON_GAT_GOUT_PERI_USI00_I2C_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_USI00_USI_CLK, "gout_peri_usi00_usi_clk",
+	     "dout_clk_peri_usi_usi", CLK_CON_GAT_GOUT_PERI_USI00_USI_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_SPI_0_PCLK, "gout_peri_spi_0_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_SPI_0_IPCLK, "gout_peri_spi_0_ipclk", "dout_cmu_peri_spi0",
+	     CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_SPI_1_PCLK, "gout_peri_spi_1_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_SPI_1_IPCLK, "gout_peri_spi_1_ipclk", "dout_cmu_peri_spi1",
+	     CLK_CON_GAT_GOUT_PERI_SPI_1_IPCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_SPI_2_PCLK, "gout_peri_spi_2_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_SPI_2_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_SPI_2_IPCLK, "gout_peri_spi_2_ipclk", "dout_cmu_peri_spi1",
+	     CLK_CON_GAT_GOUT_PERI_SPI_2_IPCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_SYSREG_PCLK, "gout_peri_sysreg_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_SYSREG_PCLK, 21, 0, 0),
+	GATE(CLK_GOUT_PERI_UART_IPCLK, "gout_peri_uart_ipclk", "mout_pll_peri_uart_user",
+	     CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_UART_PCLK, "gout_peri_uart_pclk", "mout_pll_peri_bus_user",
+	     CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_USI00_I2C_IPCLK, "gout_peri_usi00_i2c_ipclk",
+	     "dout_clk_peri_usi_i2c_user", CLK_CON_GAT_GOUT_PERI_USI00_I2C_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_USI00_I2C_PCLK, "gout_peri_usi00_i2c_pclk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_USI00_I2C_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_USI00_USI_IPCLK, "gout_peri_usi00_usi_ipclk",
+	     "dout_clk_peri_usi_usi_user", CLK_CON_GAT_GOUT_PERI_USI00_USI_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_USI00_USI_PCLK, "gout_peri_usi00_usi_pclk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_USI00_USI_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_WDT_CLUSTER0_PCLK, "gout_peri_wdt_cluster0_pclk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_PERI_WDT_CLUSTER1_PCLK, "gout_peri_wdt_cluster1_pclk",
+	     "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info peri_cmu_info __initconst = {
+	.mux_clks		= peri_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(peri_mux_clks),
+	.div_clks		= peri_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(peri_div_clks),
+	.gate_clks		= peri_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(peri_gate_clks),
+	.clk_regs		= peri_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(peri_clk_regs),
+	.nr_clk_ids		= CLKS_NR_PERI,
+};
+
+static void __init exynos9610_cmu_peri_init(struct device_node *np)
+{
+	exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos9610_cmu_peri, "samsung,exynos9610-cmu-peri",
+	       exynos9610_cmu_peri_init);
+
+/* CMU_APM */
+#define PLL_CON0_MUX_CLKCMU_APM_BUS_USER		0x0100
+#define PLL_CON2_MUX_CLKCMU_APM_BUS_USER		0x0108
+#define PLL_CON0_MUX_DLL_USER				0x0120
+#define PLL_CON2_MUX_DLL_USER				0x0128
+#define CLK_CON_MUX_CLKCMU_SHUB_BUS			0x1000
+#define CLK_CON_MUX_CLK_APM_BUS				0x1004
+#define CLK_CON_DIV_CLKCMU_SHUB_BUS			0x1800
+#define CLK_CON_DIV_CLK_APM_BUS				0x1804
+#define CLK_CON_GAT_CLKCMU_CMGP_BUS			0x2000
+#define CLK_CON_GAT_CLK_APM_CMU_PCLK			0x2004
+#define CLK_CON_GAT_CLK_APM_OSCCLK_CLK			0x2008
+#define CLK_CON_GAT_CLK_APM_OSCCLK_RCO_CLK		0x200c
+#define CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS		0x2010
+#define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK	0x2014
+#define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK	0x2018
+#define CLK_CON_GAT_GOUT_APM_APBIF_RTC_ALIVE_PCLK	0x201c
+#define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_ALIVE_PCLK	0x2020
+#define CLK_CON_GAT_GOUT_APM_GREBEINTEGRATION_HCLK	0x2024
+#define CLK_CON_GAT_GOUT_APM_INTMEM_ACLK		0x2028
+#define CLK_CON_GAT_GOUT_APM_INTMEM_PCLK		0x202c
+#define CLK_CON_GAT_GOUT_APM_LHM_AXI_P_GNSS_CLK		0x2030
+#define CLK_CON_GAT_GOUT_APM_LHM_AXI_P_CLK		0x2034
+#define CLK_CON_GAT_GOUT_APM_LHM_AXI_P_MODEM_CLK	0x2038
+#define CLK_CON_GAT_GOUT_APM_LHM_AXI_P_SHUB_CLK		0x203c
+#define CLK_CON_GAT_GOUT_APM_LHM_AXI_P_WLBT_CLK		0x2040
+#define CLK_CON_GAT_GOUT_APM_LHS_AXI_D_CLK		0x2044
+#define CLK_CON_GAT_GOUT_APM_LHS_AXI_LP_SHUB_CLK	0x2048
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_PCLK		0x204c
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_S_PCLK	0x2050
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_AP2GNSS_PCLK	0x2054
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_AP2SHUB_PCLK	0x2058
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_AP2WLBT_PCLK	0x205c
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM2AP_PCLK	0x2060
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM2CP_PCLK	0x2064
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM2GNSS_PCLK	0x2068
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM2SHUB_PCLK	0x206c
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM2WLBT_PCLK	0x2070
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_CP2GNSS_PCLK	0x2074
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_CP2SHUB_PCLK	0x2078
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_CP2WLBT_PCLK	0x207c
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2GNSS_PCLK	0x2080
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2WLBT_PCLK	0x2084
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2ABOX_PCLK	0x2088
+#define CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2GNSS_PCLK	0x208c
+#define CLK_CON_GAT_GOUT_APM_PEM_CLK			0x2090
+#define CLK_CON_GAT_GOUT_APM_PGEN_LITE_CLK		0x2094
+#define CLK_CON_GAT_GOUT_APM_PMU_INTR_GEN_PCLK		0x2098
+#define CLK_CON_GAT_GOUT_APM_BUS_CLK			0x209c
+#define CLK_CON_GAT_GOUT_APM_GREBE_CLK			0x20a0
+#define CLK_CON_GAT_GOUT_APM_SPEEDY_PCLK		0x20a4
+#define CLK_CON_GAT_GOUT_APM_SYSREG_PCLK		0x20a8
+#define CLK_CON_GAT_GOUT_APM_WDT_PCLK			0x20ac
+#define CLK_CON_GAT_GOUT_APM_XIU_DP_ACLK		0x20b0
+
+static const unsigned long apm_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
+	PLL_CON2_MUX_CLKCMU_APM_BUS_USER,
+	PLL_CON0_MUX_DLL_USER,
+	PLL_CON2_MUX_DLL_USER,
+	CLK_CON_MUX_CLKCMU_SHUB_BUS,
+	CLK_CON_MUX_CLK_APM_BUS,
+	CLK_CON_DIV_CLKCMU_SHUB_BUS,
+	CLK_CON_DIV_CLK_APM_BUS,
+	CLK_CON_GAT_CLKCMU_CMGP_BUS,
+	CLK_CON_GAT_CLK_APM_CMU_PCLK,
+	CLK_CON_GAT_CLK_APM_OSCCLK_CLK,
+	CLK_CON_GAT_CLK_APM_OSCCLK_RCO_CLK,
+	CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS,
+	CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
+	CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
+	CLK_CON_GAT_GOUT_APM_APBIF_RTC_ALIVE_PCLK,
+	CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_ALIVE_PCLK,
+	CLK_CON_GAT_GOUT_APM_GREBEINTEGRATION_HCLK,
+	CLK_CON_GAT_GOUT_APM_INTMEM_ACLK,
+	CLK_CON_GAT_GOUT_APM_INTMEM_PCLK,
+	CLK_CON_GAT_GOUT_APM_LHM_AXI_P_GNSS_CLK,
+	CLK_CON_GAT_GOUT_APM_LHM_AXI_P_CLK,
+	CLK_CON_GAT_GOUT_APM_LHM_AXI_P_MODEM_CLK,
+	CLK_CON_GAT_GOUT_APM_LHM_AXI_P_SHUB_CLK,
+	CLK_CON_GAT_GOUT_APM_LHM_AXI_P_WLBT_CLK,
+	CLK_CON_GAT_GOUT_APM_LHS_AXI_D_CLK,
+	CLK_CON_GAT_GOUT_APM_LHS_AXI_LP_SHUB_CLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_S_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_AP2GNSS_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_AP2SHUB_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_AP2WLBT_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_APM2AP_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_APM2CP_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_APM2GNSS_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_APM2SHUB_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_APM2WLBT_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_CP2GNSS_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_CP2SHUB_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_CP2WLBT_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2GNSS_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2WLBT_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2ABOX_PCLK,
+	CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2GNSS_PCLK,
+	CLK_CON_GAT_GOUT_APM_PEM_CLK,
+	CLK_CON_GAT_GOUT_APM_PGEN_LITE_CLK,
+	CLK_CON_GAT_GOUT_APM_PMU_INTR_GEN_PCLK,
+	CLK_CON_GAT_GOUT_APM_BUS_CLK,
+	CLK_CON_GAT_GOUT_APM_GREBE_CLK,
+	CLK_CON_GAT_GOUT_APM_SPEEDY_PCLK,
+	CLK_CON_GAT_GOUT_APM_SYSREG_PCLK,
+	CLK_CON_GAT_GOUT_APM_WDT_PCLK,
+	CLK_CON_GAT_GOUT_APM_XIU_DP_ACLK,
+};
+
+PNAME(mout_pll_apm_bus_user_p)		= { "oscclk", "dout_cmu_apm_bus" };
+PNAME(mout_pll_dll_user_p)		= { "oscclk", "dll_dco" };
+PNAME(mout_cmu_shub_bus_p)		= { "oscclk", "mout_pll_dll_user" };
+PNAME(mout_clk_apm_bus_p)		= { "mout_pll_apm_bus_user",
+					    "dll_dco" };
+
+static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PLL_APM_BUS_USER, "mout_pll_apm_bus_user", mout_pll_apm_bus_user_p,
+	    PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_DLL_USER, "mout_pll_dll_user", mout_pll_dll_user_p,
+	    PLL_CON0_MUX_DLL_USER, 4, 1),
+	MUX(CLK_MOUT_CMU_SHUB_BUS, "mout_cmu_shub_bus", mout_cmu_shub_bus_p,
+	    CLK_CON_MUX_CLKCMU_SHUB_BUS, 0, 1),
+	MUX(CLK_MOUT_CLK_APM_BUS, "mout_clk_apm_bus", mout_clk_apm_bus_p,
+	    CLK_CON_MUX_CLK_APM_BUS, 0, 1),
+};
+
+static const struct samsung_div_clock apm_div_clks[] __initconst = {
+	DIV(CLK_DOUT_CMU_SHUB_BUS, "dout_cmu_shub_bus", "gout_cmu_shub_bus",
+	    CLK_CON_DIV_CLKCMU_SHUB_BUS, 0, 3),
+	DIV(CLK_DOUT_CLK_APM_BUS, "dout_clk_apm_bus", "mout_clk_apm_bus",
+	    CLK_CON_DIV_CLK_APM_BUS, 0, 3),
+};
+
+static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_CMU_CMGP_BUS, "gout_cmu_cmgp_bus", "dout_clk_apm_bus",
+	     CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_APM_CMU_PCLK, "gout_clk_apm_cmu_pclk", "dout_clk_apm_bus",
+	     CLK_CON_GAT_CLK_APM_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_APM_OSCCLK_CLK, "gat_clk_apm_oscclk_clk", "oscclk",
+	     CLK_CON_GAT_CLK_APM_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_APM_OSCCLK_RCO_CLK, "gat_clk_apm_oscclk_rco_clk", "oscclk",
+	     CLK_CON_GAT_CLK_APM_OSCCLK_RCO_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, "gout_apm_apbif_gpio_alive_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK, "gout_apm_apbif_pmu_alive_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_APBIF_RTC_ALIVE_PCLK, "gout_apm_apbif_rtc_alive_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_APBIF_RTC_ALIVE_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_APBIF_TOP_RTC_ALIVE_PCLK, "gout_apm_apbif_top_rtc_alive_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_ALIVE_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK, "gout_apm_grebeintegration_hclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_GREBEINTEGRATION_HCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_INTMEM_ACLK, "gout_apm_intmem_aclk", "dout_clk_apm_bus",
+	     CLK_CON_GAT_GOUT_APM_INTMEM_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_INTMEM_PCLK, "gout_apm_intmem_pclk", "dout_clk_apm_bus",
+	     CLK_CON_GAT_GOUT_APM_INTMEM_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_LHM_AXI_P_GNSS_CLK, "gout_apm_lhm_axi_p_gnss_clk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHM_AXI_P_GNSS_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_LHM_AXI_P_CLK, "gout_apm_lhm_axi_p_clk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHM_AXI_P_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_LHM_AXI_P_MODEM_CLK, "gout_apm_lhm_axi_p_modem_clk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHM_AXI_P_MODEM_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_LHM_AXI_P_SHUB_CLK, "gout_apm_lhm_axi_p_shub_clk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHM_AXI_P_SHUB_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_LHM_AXI_P_WLBT_CLK, "gout_apm_lhm_axi_p_wlbt_clk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHM_AXI_P_WLBT_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_LHS_AXI_D_CLK, "gout_apm_lhs_axi_d_clk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHS_AXI_D_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_LHS_AXI_LP_SHUB_CLK, "gout_apm_lhs_axi_lp_shub_clk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHS_AXI_LP_SHUB_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_AP2CP_PCLK, "gout_apm_mailbox_ap2cp_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_AP2CP_S_PCLK, "gout_apm_mailbox_ap2cp_s_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_S_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_AP2GNSS_PCLK, "gout_apm_mailbox_ap2gnss_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_AP2GNSS_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_AP2SHUB_PCLK, "gout_apm_mailbox_ap2shub_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_AP2SHUB_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_AP2WLBT_PCLK, "gout_apm_mailbox_ap2wlbt_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_AP2WLBT_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_APM2AP_PCLK, "gout_apm_mailbox_apm2ap_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_APM2AP_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_APM2CP_PCLK, "gout_apm_mailbox_apm2cp_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_APM2CP_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_APM2GNSS_PCLK, "gout_apm_mailbox_apm2gnss_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_APM2GNSS_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_APM2SHUB_PCLK, "gout_apm_mailbox_apm2shub_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_APM2SHUB_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_APM2WLBT_PCLK, "gout_apm_mailbox_apm2wlbt_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_APM2WLBT_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_CP2GNSS_PCLK, "gout_apm_mailbox_cp2gnss_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_CP2GNSS_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_CP2SHUB_PCLK, "gout_apm_mailbox_cp2shub_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_CP2SHUB_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_CP2WLBT_PCLK, "gout_apm_mailbox_cp2wlbt_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_CP2WLBT_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_SHUB2GNSS_PCLK, "gout_apm_mailbox_shub2gnss_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2GNSS_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_SHUB2WLBT_PCLK, "gout_apm_mailbox_shub2wlbt_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2WLBT_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_WLBT2ABOX_PCLK, "gout_apm_mailbox_wlbt2abox_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2ABOX_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_MAILBOX_WLBT2GNSS_PCLK, "gout_apm_mailbox_wlbt2gnss_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2GNSS_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_PEM_CLK, "gout_apm_pem_clk", "dout_clk_apm_bus",
+	     CLK_CON_GAT_GOUT_APM_PEM_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_PGEN_LITE_CLK, "gout_apm_pgen_lite_clk", "dout_clk_apm_bus",
+	     CLK_CON_GAT_GOUT_APM_PGEN_LITE_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK, "gout_apm_pmu_intr_gen_pclk",
+	     "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_PMU_INTR_GEN_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_BUS_CLK, "gout_apm_bus_clk", "dout_clk_apm_bus",
+	     CLK_CON_GAT_GOUT_APM_BUS_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_GREBE_CLK, "gout_apm_grebe_clk", "dout_clk_apm_bus",
+	     CLK_CON_GAT_GOUT_APM_GREBE_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_SPEEDY_PCLK, "gout_apm_speedy_pclk", "dout_clk_apm_bus",
+	     CLK_CON_GAT_GOUT_APM_SPEEDY_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_SYSREG_PCLK, "gout_apm_sysreg_pclk", "dout_clk_apm_bus",
+	     CLK_CON_GAT_GOUT_APM_SYSREG_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_WDT_PCLK, "gout_apm_wdt_pclk", "dout_clk_apm_bus",
+	     CLK_CON_GAT_GOUT_APM_WDT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_APM_XIU_DP_ACLK, "gout_apm_xiu_dp_aclk", "dout_clk_apm_bus",
+	     CLK_CON_GAT_GOUT_APM_XIU_DP_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info apm_cmu_info __initconst = {
+	.mux_clks		= apm_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(apm_mux_clks),
+	.div_clks		= apm_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(apm_div_clks),
+	.gate_clks		= apm_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(apm_gate_clks),
+	.clk_regs		= apm_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(apm_clk_regs),
+	.nr_clk_ids		= CLKS_NR_APM,
+};
+
+static void __init exynos9610_cmu_apm_init(struct device_node *np)
+{
+	exynos_arm64_register_cmu(NULL, np, &apm_cmu_info);
+}
+
+// Register APM early, as it's a dependency of CMU_CMGP
+CLK_OF_DECLARE(exynos9610_cmu_apm, "samsung,exynos9610-cmu-apm",
+	       exynos9610_cmu_apm_init);
+
+/* CMU_CAM */
+#define PLL_CON0_MUX_CLKCMU_CAM_BUS_USER			0x0100
+#define PLL_CON2_MUX_CLKCMU_CAM_BUS_USER			0x0108
+#define CLK_CON_DIV_DIV_CLK_CAM_BUSP				0x1800
+#define CLK_CON_GAT_CLK_CAM_CMU_PCLK				0x2000
+#define CLK_CON_GAT_CLK_CAM_OSCCLK_CLK				0x2004
+#define CLK_CON_GAT_GOUT_CAM_BUSD				0x2008
+#define CLK_CON_GAT_GOUT_CAM_BTM_ACLK				0x200c
+#define CLK_CON_GAT_GOUT_CAM_BTM_PCLK				0x2010
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_3AA			0x2014
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS0		0x2018
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS1		0x201c
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS2		0x2020
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS3		0x2024
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_DMA			0x2028
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS0		0x202c
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS1		0x2030
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS2		0x2034
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS3		0x2038
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PAFSTAT_CORE		0x203c
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PPMU_CAM		0x2040
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_RDMA			0x2044
+// #define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_SMMU_CAM		0x2048
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_XIU_D_CAM		0x204c
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM0	0x2050
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM1	0x2054
+#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PPMU_CAM		0x2058
+#define CLK_CON_GAT_GOUT_CAM_LHM_AXI_P_CLK			0x205c
+#define CLK_CON_GAT_GOUT_CAM_LHS_ACEL_D_CLK			0x2060
+#define CLK_CON_GAT_GOUT_CAM_LHS_ATB_CAMISP_CLK			0x2064
+#define CLK_CON_GAT_GOUT_CAM_BUSD_CLK				0x2068
+#define CLK_CON_GAT_GOUT_CAM_BUSP_CLK				0x206c
+#define CLK_CON_GAT_GOUT_CAM_SYSREG_PCLK			0x2070
+
+static const unsigned long cam_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLKCMU_CAM_BUS_USER,
+	PLL_CON2_MUX_CLKCMU_CAM_BUS_USER,
+	CLK_CON_DIV_DIV_CLK_CAM_BUSP,
+	CLK_CON_GAT_CLK_CAM_CMU_PCLK,
+	CLK_CON_GAT_CLK_CAM_OSCCLK_CLK,
+	CLK_CON_GAT_GOUT_CAM_BUSD,
+	CLK_CON_GAT_GOUT_CAM_BTM_ACLK,
+	CLK_CON_GAT_GOUT_CAM_BTM_PCLK,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_3AA,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS0,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS1,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS2,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS3,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_DMA,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS0,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS1,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS2,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS3,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PAFSTAT_CORE,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PPMU_CAM,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_RDMA,
+	// CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_SMMU_CAM,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_XIU_D_CAM,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM0,
+	CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PPMU_CAM,
+	CLK_CON_GAT_GOUT_CAM_LHM_AXI_P_CLK,
+	CLK_CON_GAT_GOUT_CAM_LHS_ATB_CAMISP_CLK,
+	CLK_CON_GAT_GOUT_CAM_BUSD_CLK,
+	CLK_CON_GAT_GOUT_CAM_BUSP_CLK,
+	CLK_CON_GAT_GOUT_CAM_SYSREG_PCLK,
+};
+
+PNAME(mout_pll_cam_bus_user_p) = { "oscclk", "dout_cmu_cam_bus" };
+
+static const struct samsung_mux_clock cam_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PLL_CAM_BUS_USER, "mout_pll_cam_bus_user", mout_pll_cam_bus_user_p,
+	    PLL_CON0_MUX_CLKCMU_CAM_BUS_USER, 4, 1),
+};
+
+static const struct samsung_div_clock cam_div_clks[] __initconst = {
+	DIV(CLK_DIV_CLK_CAM_BUSP, "dout_clk_cam_busp", "mout_pll_cam_bus_user",
+	    CLK_CON_DIV_DIV_CLK_CAM_BUSP, 0, 2),
+};
+
+static const struct samsung_gate_clock cam_gate_clks[] __initconst = {
+	GATE(CLK_GAT_CLK_CAM_CMU_PCLK, "gat_clk_cam_cmu_pclk", "dout_clk_cam_busp",
+	     CLK_CON_GAT_CLK_CAM_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GAT_CLK_CAM_OSCCLK_CLK, "gat_clk_cam_oscclk_clk", "oscclk",
+	     CLK_CON_GAT_CLK_CAM_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_BUSD, "gout_cam_busd", "mout_pll_cam_bus_user",
+	     CLK_CON_GAT_GOUT_CAM_BUSD, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_BTM_ACLK, "gout_cam_btm_aclk", "mout_pll_cam_bus_user",
+	     CLK_CON_GAT_GOUT_CAM_BTM_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_BTM_PCLK, "gout_cam_btm_pclk", "dout_clk_cam_busp",
+	     CLK_CON_GAT_GOUT_CAM_BTM_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_GOUT_CAM_LHS_ATB_CAMISP_CLK, "gout_cam_lhs_atb_camisp_clk",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_LHS_ATB_CAMISP_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_3AA, "gout_cam_is6p10p0_aclk_3aa",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_3AA,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS0, "gout_cam_is6p10p0_aclk_csis0",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS0,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS1, "gout_cam_is6p10p0_aclk_csis1",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS1,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS2, "gout_cam_is6p10p0_aclk_csis2",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS2,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS3, "gout_cam_is6p10p0_aclk_csis3",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS3,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_RDMA, "gout_cam_is6p10p0_aclk_rdma",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_RDMA,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS0, "gout_cam_is6p10p0_aclk_glue_csis0",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS0,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS1, "gout_cam_is6p10p0_aclk_glue_csis1",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS1,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS2, "gout_cam_is6p10p0_aclk_glue_csis2",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS2,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS3, "gout_cam_is6p10p0_aclk_glue_csis3",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS3,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_PAFSTAT_CORE, "gout_cam_is6p10p0_aclk_pafstat_core",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PAFSTAT_CORE,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_PPMU_CAM, "gout_cam_is6p10p0_aclk_ppmu_cam",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PPMU_CAM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_DMA, "gout_cam_is6p10p0_aclk_dma",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_DMA,
+	     21, CLK_IGNORE_UNUSED, 0),
+	// GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_SMMU_CAM, "gout_cam_is6p10p0_aclk_smmu_cam",
+	//      "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_SMMU_CAM,
+	//      21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_XIU_D_CAM, "gout_cam_is6p10p0_aclk_xiu_d_cam",
+	     "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_XIU_D_CAM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM0, "gout_cam_is6p10p0_pclk_pgen_lite_cam0",
+	     "dout_clk_cam_busp", CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM0,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM1, "gout_cam_is6p10p0_pclk_pgen_lite_cam1",
+	     "dout_clk_cam_busp", CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM1,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_IS6P10P0_PCLK_PPMU_CAM, "gout_cam_is6p10p0_pclk_ppmu_cam",
+	     "dout_clk_cam_busp", CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PPMU_CAM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_LHM_AXI_P_CLK, "gout_cam_lhm_axi_p_clk", "dout_clk_cam_busp",
+	     CLK_CON_GAT_GOUT_CAM_LHM_AXI_P_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_LHS_ACEL_D_CLK, "gout_cam_lhs_acel_d_clk", "mout_pll_cam_bus_user",
+	     CLK_CON_GAT_GOUT_CAM_LHS_ACEL_D_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_BUSD_CLK, "gout_cam_busd_clk", "mout_pll_cam_bus_user",
+	     CLK_CON_GAT_GOUT_CAM_BUSD_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_BUSP_CLK, "gout_cam_busp_clk", "dout_clk_cam_busp",
+	     CLK_CON_GAT_GOUT_CAM_BUSP_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CAM_SYSREG_PCLK, "gout_cam_sysreg_pclk", "dout_clk_cam_busp",
+	     CLK_CON_GAT_GOUT_CAM_SYSREG_PCLK, 21, 0, 0),
+};
+
+static const struct samsung_cmu_info cam_cmu_info __initconst = {
+	.mux_clks		= cam_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cam_mux_clks),
+	.div_clks		= cam_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cam_div_clks),
+	.gate_clks		= cam_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(cam_gate_clks),
+	.clk_regs		= cam_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cam_clk_regs),
+	.nr_clk_ids		= CLKS_NR_CAM,
+};
+
+/* CMU_CMGP */
+#define CLK_CON_MUX_MUX_CLK_CMGP_ADC			0x1000
+#define CLK_CON_MUX_MUX_CLK_CMGP_I2C			0x1004
+#define CLK_CON_MUX_MUX_CLK_CMGP_USI00			0x1008
+#define CLK_CON_MUX_MUX_CLK_CMGP_USI01			0x100c
+#define CLK_CON_MUX_MUX_CLK_CMGP_USI02			0x1010
+#define CLK_CON_MUX_MUX_CLK_CMGP_USI03			0x1014
+#define CLK_CON_MUX_MUX_CLK_CMGP_USI04			0x1018
+#define CLK_CON_DIV_DIV_CLK_CMGP_ADC			0x1800
+#define CLK_CON_DIV_DIV_CLK_CMGP_I2C			0x1804
+#define CLK_CON_DIV_DIV_CLK_CMGP_USI00			0x1808
+#define CLK_CON_DIV_DIV_CLK_CMGP_USI01			0x180c
+#define CLK_CON_DIV_DIV_CLK_CMGP_USI02			0x1810
+#define CLK_CON_DIV_DIV_CLK_CMGP_USI03			0x1814
+#define CLK_CON_DIV_DIV_CLK_CMGP_USI04			0x1818
+#define CLK_CON_GAT_CMGP_CMU_PCLK			0x2004
+#define CLK_CON_GAT_CLK_CMGP_OSCCLK_RCO_CLK		0x2008
+#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0		0x200c
+#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1		0x2010
+#define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK			0x2014
+#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_IPCLK		0x2018
+#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_PCLK		0x201c
+#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_IPCLK		0x2020
+#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_PCLK		0x2024
+#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_IPCLK		0x2028
+#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_PCLK		0x202c
+#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_IPCLK		0x2030
+#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_PCLK		0x2034
+#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_IPCLK		0x2038
+#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_PCLK		0x203c
+#define CLK_CON_GAT_GOUT_CMGP_BUS_CLK			0x2040
+#define CLK_CON_GAT_GOUT_CMGP_I2C_CLK			0x2044
+#define CLK_CON_GAT_GOUT_CMGP_USI00_CLK			0x2048
+#define CLK_CON_GAT_GOUT_CMGP_USI01_CLK			0x204c
+#define CLK_CON_GAT_GOUT_CMGP_USI02_CLK			0x2050
+#define CLK_CON_GAT_GOUT_CMGP_USI03_CLK			0x2054
+#define CLK_CON_GAT_GOUT_CMGP_USI04_CLK			0x2058
+#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2CP_PCLK	0x205c
+#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2GNSS_PCLK	0x2060
+#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_AP_PCLK	0x2064
+#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_SHUB_PCLK	0x2068
+#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2SHUB_PCLK	0x206c
+#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2WLBT_PCLK	0x2070
+#define CLK_CON_GAT_GOUT_CMGP_SYSREG_PCLK		0x2074
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_IPCLK		0x2078
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_PCLK		0x207c
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_IPCLK		0x2080
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_PCLK		0x2084
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_IPCLK		0x2088
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_PCLK		0x208c
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_IPCLK		0x2090
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_PCLK		0x2094
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_IPCLK		0x2098
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_PCLK		0x209c
+
+static const unsigned long cmgp_clk_regs[] __initconst = {
+	CLK_CON_MUX_MUX_CLK_CMGP_ADC,
+	CLK_CON_MUX_MUX_CLK_CMGP_I2C,
+	CLK_CON_MUX_MUX_CLK_CMGP_USI00,
+	CLK_CON_MUX_MUX_CLK_CMGP_USI01,
+	CLK_CON_MUX_MUX_CLK_CMGP_USI02,
+	CLK_CON_MUX_MUX_CLK_CMGP_USI03,
+	CLK_CON_MUX_MUX_CLK_CMGP_USI04,
+	CLK_CON_DIV_DIV_CLK_CMGP_ADC,
+	CLK_CON_DIV_DIV_CLK_CMGP_I2C,
+	CLK_CON_DIV_DIV_CLK_CMGP_USI00,
+	CLK_CON_DIV_DIV_CLK_CMGP_USI01,
+	CLK_CON_DIV_DIV_CLK_CMGP_USI02,
+	CLK_CON_DIV_DIV_CLK_CMGP_USI03,
+	CLK_CON_DIV_DIV_CLK_CMGP_USI04,
+	CLK_CON_GAT_CMGP_CMU_PCLK,
+	CLK_CON_GAT_CLK_CMGP_OSCCLK_RCO_CLK,
+	CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
+	CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
+	CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_IPCLK,
+	CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_IPCLK,
+	CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_IPCLK,
+	CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_IPCLK,
+	CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_IPCLK,
+	CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_BUS_CLK,
+	CLK_CON_GAT_GOUT_CMGP_I2C_CLK,
+	CLK_CON_GAT_GOUT_CMGP_USI00_CLK,
+	CLK_CON_GAT_GOUT_CMGP_USI01_CLK,
+	CLK_CON_GAT_GOUT_CMGP_USI02_CLK,
+	CLK_CON_GAT_GOUT_CMGP_USI03_CLK,
+	CLK_CON_GAT_GOUT_CMGP_USI04_CLK,
+	CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2CP_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2GNSS_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_AP_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_SHUB_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2SHUB_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2WLBT_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_SYSREG_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_IPCLK,
+	CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_IPCLK,
+	CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_IPCLK,
+	CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_IPCLK,
+	CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_PCLK,
+	CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_IPCLK,
+	CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_PCLK,
+};
+
+PNAME(mout_clk_cmgp_adc_p)	= { "oscclk", "dout_clk_cmgp_adc" };
+PNAME(mout_clk_cmgp_i2c_p)	= { "oscclk_rco",
+				    "gout_cmu_cmgp_bus" };
+PNAME(mout_clk_cmgp_usi00_p)	= { "oscclk_rco",
+				    "gout_cmu_cmgp_bus" };
+PNAME(mout_clk_cmgp_usi01_p)	= { "oscclk_rco",
+				    "gout_cmu_cmgp_bus" };
+PNAME(mout_clk_cmgp_usi02_p)	= { "oscclk_rco",
+				    "gout_cmu_cmgp_bus" };
+PNAME(mout_clk_cmgp_usi03_p)	= { "oscclk_rco",
+				    "gout_cmu_cmgp_bus" };
+PNAME(mout_clk_cmgp_usi04_p)	= { "oscclk_rco",
+				    "gout_cmu_cmgp_bus" };
+
+static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_CLK_CMGP_ADC, "mout_clk_cmgp_adc", mout_clk_cmgp_adc_p,
+	    CLK_CON_MUX_MUX_CLK_CMGP_ADC, 0, 1),
+	MUX(CLK_MOUT_CLK_CMGP_I2C, "mout_clk_cmgp_i2c", mout_clk_cmgp_i2c_p,
+	    CLK_CON_MUX_MUX_CLK_CMGP_I2C, 0, 1),
+	MUX(CLK_MOUT_CLK_CMGP_USI00, "mout_clk_cmgp_usi00", mout_clk_cmgp_usi00_p,
+	    CLK_CON_MUX_MUX_CLK_CMGP_USI00, 0, 1),
+	MUX(CLK_MOUT_CLK_CMGP_USI01, "mout_clk_cmgp_usi01", mout_clk_cmgp_usi01_p,
+	    CLK_CON_MUX_MUX_CLK_CMGP_USI01, 0, 1),
+	MUX(CLK_MOUT_CLK_CMGP_USI02, "mout_clk_cmgp_usi02", mout_clk_cmgp_usi02_p,
+	    CLK_CON_MUX_MUX_CLK_CMGP_USI02, 0, 1),
+	MUX(CLK_MOUT_CLK_CMGP_USI03, "mout_clk_cmgp_usi03", mout_clk_cmgp_usi03_p,
+	    CLK_CON_MUX_MUX_CLK_CMGP_USI03, 0, 1),
+	MUX(CLK_MOUT_CLK_CMGP_USI04, "mout_clk_cmgp_usi04", mout_clk_cmgp_usi04_p,
+	    CLK_CON_MUX_MUX_CLK_CMGP_USI04, 0, 1),
+};
+
+static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
+	DIV(CLK_DOUT_CLK_CMGP_ADC, "dout_clk_cmgp_adc", "gout_cmu_cmgp_bus",
+	    CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
+	DIV(CLK_DOUT_CLK_CMGP_I2C, "dout_clk_cmgp_i2c", "mout_clk_cmgp_i2c",
+	    CLK_CON_DIV_DIV_CLK_CMGP_I2C, 0, 4),
+	DIV(CLK_DOUT_CLK_CMGP_USI00, "dout_clk_cmgp_usi00", "mout_clk_cmgp_usi00",
+	    CLK_CON_DIV_DIV_CLK_CMGP_USI00, 0, 4),
+	DIV(CLK_DOUT_CLK_CMGP_USI01, "dout_clk_cmgp_usi01", "mout_clk_cmgp_usi01",
+	    CLK_CON_DIV_DIV_CLK_CMGP_USI01, 0, 4),
+	DIV(CLK_DOUT_CLK_CMGP_USI02, "dout_clk_cmgp_usi02", "mout_clk_cmgp_usi02",
+	    CLK_CON_DIV_DIV_CLK_CMGP_USI02, 0, 4),
+	DIV(CLK_DOUT_CLK_CMGP_USI03, "dout_clk_cmgp_usi03", "mout_clk_cmgp_usi03",
+	    CLK_CON_DIV_DIV_CLK_CMGP_USI03, 0, 4),
+	DIV(CLK_DOUT_CLK_CMGP_USI04, "dout_clk_cmgp_usi04", "mout_clk_cmgp_usi04",
+	    CLK_CON_DIV_DIV_CLK_CMGP_USI04, 0, 4),
+};
+
+static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_CMGP_CMU_PCLK, "gout_cmgp_cmu_pclk", "gout_cmu_cmgp_bus",
+	     CLK_CON_GAT_CMGP_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_CMGP_OSCCLK_RCO_CLK, "gout_clk_cmgp_oscclk_rco_clk",
+	     "oscclk_rco", CLK_CON_GAT_CLK_CMGP_OSCCLK_RCO_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_ADC_PCLK_S0, "gout_clk_cmgp_adc_pclk_s0",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_ADC_PCLK_S1, "gout_clk_cmgp_adc_pclk_s1",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_clk_cmgp_gpio_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_I2C_CMGP00_IPCLK, "gout_clk_cmgp_i2c_cmgp00_ipclk",
+	     "mout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_I2C_CMGP00_PCLK, "gout_clk_cmgp_i2c_cmgp00_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_I2C_CMGP01_IPCLK, "gout_clk_cmgp_i2c_cmgp01_ipclk",
+	     "mout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_I2C_CMGP01_PCLK, "gout_clk_cmgp_i2c_cmgp01_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_I2C_CMGP02_IPCLK, "gout_clk_cmgp_i2c_cmgp02_ipclk",
+	     "mout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_I2C_CMGP02_PCLK, "gout_clk_cmgp_i2c_cmgp02_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_I2C_CMGP03_IPCLK, "gout_clk_cmgp_i2c_cmgp03_ipclk",
+	     "mout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_I2C_CMGP03_PCLK, "gout_clk_cmgp_i2c_cmgp03_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_I2C_CMGP04_IPCLK, "gout_clk_cmgp_i2c_cmgp04_ipclk",
+	     "mout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_I2C_CMGP04_PCLK, "gout_clk_cmgp_i2c_cmgp04_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_BUS_CLK, "gout_cmgp_bus_clk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_BUS_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_I2C_CLK, "gout_cmgp_i2c_clk",
+	     "dout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI00_CLK, "gout_cmgp_usi00_clk",
+	     "mout_clk_cmgp_usi00", CLK_CON_GAT_GOUT_CMGP_USI00_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI01_CLK, "gout_cmgp_usi01_clk",
+	     "mout_clk_cmgp_usi01", CLK_CON_GAT_GOUT_CMGP_USI01_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI02_CLK, "gout_cmgp_usi02_clk",
+	     "mout_clk_cmgp_usi02", CLK_CON_GAT_GOUT_CMGP_USI02_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI03_CLK, "gout_cmgp_usi03_clk",
+	     "mout_clk_cmgp_usi03", CLK_CON_GAT_GOUT_CMGP_USI03_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI04_CLK, "gout_cmgp_usi04_clk",
+	     "mout_clk_cmgp_usi04", CLK_CON_GAT_GOUT_CMGP_USI04_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_SYSREG_CMGP2CP_PCLK,
+	     "gout_cmgp_sysreg_cmgp2cp_pclk", "gout_cmu_cmgp_bus",
+	     CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2CP_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_SYSREG_CMGP2GNSS_PCLK,
+	     "gout_cmgp_sysreg_cmgp2gnss_pclk", "gout_cmu_cmgp_bus",
+	     CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2GNSS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_SYSREG_CMGP2PMU_AP_PCLK,
+	     "gout_cmgp_sysreg_cmgp2pmu_ap_pclk", "gout_cmu_cmgp_bus",
+	     CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_AP_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_SYSREG_CMGP2PMU_SHUB_PCLK,
+	     "gout_cmgp_sysreg_cmgp2pmu_shub_pclk", "gout_cmu_cmgp_bus",
+	     CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_SHUB_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_SYSREG_CMGP2SHUB_PCLK,
+	     "gout_cmgp_sysreg_cmgp2shub_pclk", "gout_cmu_cmgp_bus",
+	     CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2SHUB_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_SYSREG_CMGP2WLBT_PCLK,
+	     "gout_cmgp_sysreg_cmgp2wlbt_pclk", "gout_cmu_cmgp_bus",
+	     CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2WLBT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_SYSREG_PCLK, "gout_cmgp_sysreg_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_SYSREG_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI_CMGP00_IPCLK, "gout_clk_cmgp_usi_cmgp00_ipclk",
+	     "mout_clk_cmgp_usi00", CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI_CMGP00_PCLK, "gout_clk_cmgp_usi_cmgp00_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI_CMGP01_IPCLK, "gout_clk_cmgp_usi_cmgp01_ipclk",
+	     "mout_clk_cmgp_usi01", CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI_CMGP01_PCLK, "gout_clk_cmgp_usi_cmgp01_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI_CMGP02_IPCLK, "gout_clk_cmgp_usi_cmgp02_ipclk",
+	     "mout_clk_cmgp_usi02", CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI_CMGP02_PCLK, "gout_clk_cmgp_usi_cmgp02_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI_CMGP03_IPCLK, "gout_clk_cmgp_usi_cmgp03_ipclk",
+	     "mout_clk_cmgp_usi03", CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI_CMGP03_PCLK, "gout_clk_cmgp_usi_cmgp03_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI_CMGP04_IPCLK, "gout_clk_cmgp_usi_cmgp04_ipclk",
+	     "mout_clk_cmgp_usi04", CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CMGP_USI_CMGP04_PCLK, "gout_clk_cmgp_usi_cmgp04_pclk",
+	     "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_IPCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
+	.mux_clks		= cmgp_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(cmgp_mux_clks),
+	.div_clks		= cmgp_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(cmgp_div_clks),
+	.gate_clks		= cmgp_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(cmgp_gate_clks),
+	.clk_regs		= cmgp_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(cmgp_clk_regs),
+	.nr_clk_ids		= CLKS_NR_CMGP,
+};
+
+/* CMU_CORE */
+#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER			0x0100
+#define PLL_CON2_MUX_CLKCMU_CORE_BUS_USER			0x0108
+#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER			0x0120
+#define PLL_CON2_MUX_CLKCMU_CORE_CCI_USER			0x0128
+#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER			0x0140
+#define PLL_CON2_MUX_CLKCMU_CORE_G3D_USER			0x0148
+#define CLK_CON_MUX_MUX_CLK_CORE_GIC				0x1000
+#define CLK_CON_DIV_DIV_CLK_CORE_BUSP				0x1800
+#define CLK_CON_GAT_CLK_CORE_CMU_PCLK				0x2000
+#define CLK_CON_GAT_GOUT_CORE_AD_APB_CCI_550_PCLKM		0x2004
+#define CLK_CON_GAT_GOUT_CORE_AD_APB_DIT_PCLKM			0x2008
+#define CLK_CON_GAT_GOUT_CORE_AD_APB_PDMA0_PCLKM		0x200c
+#define CLK_CON_GAT_GOUT_CORE_AD_APB_PGEN_PDMA_PCLKM		0x2010
+#define CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM0_PCLKM		0x2014
+#define CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM1_PCLKM		0x2018
+#define CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_PERI_PCLKM		0x201c
+#define CLK_CON_GAT_GOUT_CORE_AD_APB_SPDMA_PCLKM		0x2020
+#define CLK_CON_GAT_GOUT_CORE_AD_AXI_GIC_ACLKM			0x2024
+#define CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC0_PCLK		0x2028
+#define CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC1_PCLK		0x202c
+#define CLK_CON_GAT_GOUT_CORE_AXI_US_A40_64TO128_DIT_ACLK	0x2030
+#define CLK_CON_GAT_GOUT_CORE_BAAW_P_GNSS_PCLK			0x2034
+#define CLK_CON_GAT_GOUT_CORE_BAAW_P_MODEM_PCLK			0x2038
+#define CLK_CON_GAT_GOUT_CORE_BAAW_P_SHUB_PCLK			0x203c
+#define CLK_CON_GAT_GOUT_CORE_BAAW_P_WLBT_PCLK			0x2040
+#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK			0x2044
+#define CLK_CON_GAT_GOUT_CORE_DIT_ICLKL2A			0x2048
+#define CLK_CON_GAT_GOUT_CORE_GIC400_AIHWACG_CLK		0x204c
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_ISP_CLK		0x2050
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_MFC_CLK		0x2054
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_ISP_CLK		0x2058
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_MFC_CLK		0x205c
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_CAM_CLK		0x2060
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_DPU_CLK		0x2064
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_FSYS_CLK		0x2068
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_G2D_CLK		0x206c
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_USB_CLK		0x2070
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX1_CLK		0x2074
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX2_CLK		0x2078
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL0_CLK		0x207c
+#define CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL1_CLK		0x2080
+#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D0_MODEM_CLK		0x2084
+#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D1_MODEM_CLK		0x2088
+#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_ABOX_CLK		0x208c
+#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_APM_CLK			0x2090
+#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_CSSYS_CLK		0x2094
+#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_G3D_CLK			0x2098
+#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_GNSS_CLK		0x209c
+#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_SHUB_CLK		0x20a0
+#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_WLBT_CLK		0x20a4
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CPU_CLK		0x20a8
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CP_CLK		0x20ac
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_NRT_CLK		0x20b0
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_RT_CLK		0x20b4
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CPU_CLK		0x20b8
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CP_CLK		0x20bc
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_NRT_CLK		0x20c0
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_RT_CLK		0x20c4
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_APM_CLK			0x20c8
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CAM_CLK			0x20cc
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL0_CLK		0x20d0
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL1_CLK		0x20d4
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_DISPAUD_CLK		0x20d8
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_FSYS_CLK		0x20dc
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G2D_CLK			0x20e0
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G3D_CLK			0x20e4
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_GNSS_CLK		0x20e8
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_ISP_CLK			0x20ec
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MFC_CLK			0x20f0
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF0_CLK		0x20f4
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF1_CLK		0x20f8
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MODEM_CLK		0x20fc
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_PERI_CLK		0x2100
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_SHUB_CLK		0x2104
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_USB_CLK			0x2108
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX1_CLK		0x210c
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX2_CLK		0x2110
+#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_WLBT_CLK		0x2114
+#define CLK_CON_GAT_GOUT_CORE_PDMA_CORE_ACLK_PDMA0		0x2118
+#define CLK_CON_GAT_GOUT_CORE_PGEN_LITE_SIREX_CLK		0x211c
+#define CLK_CON_GAT_GOUT_CORE_PGEN_PDMA_CLK			0x2120
+#define CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_ACLK			0x2124
+#define CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_PCLK			0x2128
+#define CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM0_CLK		0x212c
+#define CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM1_CLK		0x2130
+#define CLK_CON_GAT_GOUT_CORE_PPFW_CORE_PERI_CLK		0x2134
+#define CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_ACLK		0x2138
+#define CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_PCLK		0x213c
+#define CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_ACLK		0x2140
+#define CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_PCLK		0x2144
+#define CLK_CON_GAT_GOUT_CORE_BUSD_CLK				0x2148
+#define CLK_CON_GAT_GOUT_CORE_BUSP_G3D_OCC_CLK			0x214c
+#define CLK_CON_GAT_GOUT_CORE_BUSP_CLK				0x2150
+#define CLK_CON_GAT_GOUT_CORE_BUSP_OCC_CLK			0x2154
+#define CLK_CON_GAT_GOUT_CORE_CCI_CLK				0x2158
+#define CLK_CON_GAT_GOUT_CORE_CCI_OCC_CLK			0x215c
+#define CLK_CON_GAT_GOUT_CORE_G3D_CLK				0x2160
+#define CLK_CON_GAT_GOUT_CORE_G3D_OCC_CLK			0x2164
+#define CLK_CON_GAT_GOUT_CORE_GIC_CLK				0x2168
+#define CLK_CON_GAT_GOUT_CORE_OSCCLK_CLK			0x216c
+#define CLK_CON_GAT_GOUT_CORE_SFR_APBIF_CMU_TOPC_PCLK		0x2170
+#define CLK_CON_GAT_GOUT_CORE_SIREX_ACLK			0x2174
+#define CLK_CON_GAT_GOUT_CORE_SIREX_PCLK			0x2178
+#define CLK_CON_GAT_GOUT_CORE_SPDMA_CORE_ACLK_PDMA1		0x217c
+#define CLK_CON_GAT_GOUT_CORE_SYSREG_PCLK			0x2180
+#define CLK_CON_GAT_GOUT_CORE_TREX_D_ACLK			0x2184
+#define CLK_CON_GAT_GOUT_CORE_TREX_D_CCLK			0x2188
+#define CLK_CON_GAT_GOUT_CORE_TREX_D_GCLK			0x218c
+#define CLK_CON_GAT_GOUT_CORE_TREX_D_PCLK			0x2190
+#define CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_ACLK			0x2194
+#define CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_PCLK			0x2198
+#define CLK_CON_GAT_GOUT_CORE_TREX_P_ACLK_P_CORE		0x219c
+#define CLK_CON_GAT_GOUT_CORE_TREX_P_CCLK_P_CORE		0x21a0
+#define CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK			0x21a4
+#define CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK_P_CORE		0x21a8
+#define CLK_CON_GAT_GOUT_CORE_XIU_D_ACLK			0x21ac
+
+static const unsigned long core_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
+	PLL_CON2_MUX_CLKCMU_CORE_BUS_USER,
+	PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
+	PLL_CON2_MUX_CLKCMU_CORE_CCI_USER,
+	PLL_CON0_MUX_CLKCMU_CORE_G3D_USER,
+	PLL_CON2_MUX_CLKCMU_CORE_G3D_USER,
+	CLK_CON_MUX_MUX_CLK_CORE_GIC,
+	CLK_CON_DIV_DIV_CLK_CORE_BUSP,
+	CLK_CON_GAT_CLK_CORE_CMU_PCLK,
+	CLK_CON_GAT_GOUT_CORE_AD_APB_CCI_550_PCLKM,
+	CLK_CON_GAT_GOUT_CORE_AD_APB_DIT_PCLKM,
+	CLK_CON_GAT_GOUT_CORE_AD_APB_PDMA0_PCLKM,
+	CLK_CON_GAT_GOUT_CORE_AD_APB_PGEN_PDMA_PCLKM,
+	CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM0_PCLKM,
+	CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM1_PCLKM,
+	CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_PERI_PCLKM,
+	CLK_CON_GAT_GOUT_CORE_AD_APB_SPDMA_PCLKM,
+	CLK_CON_GAT_GOUT_CORE_AD_AXI_GIC_ACLKM,
+	CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC0_PCLK,
+	CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC1_PCLK,
+	CLK_CON_GAT_GOUT_CORE_AXI_US_A40_64TO128_DIT_ACLK,
+	CLK_CON_GAT_GOUT_CORE_BAAW_P_GNSS_PCLK,
+	CLK_CON_GAT_GOUT_CORE_BAAW_P_MODEM_PCLK,
+	CLK_CON_GAT_GOUT_CORE_BAAW_P_SHUB_PCLK,
+	CLK_CON_GAT_GOUT_CORE_BAAW_P_WLBT_PCLK,
+	CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
+	CLK_CON_GAT_GOUT_CORE_DIT_ICLKL2A,
+	CLK_CON_GAT_GOUT_CORE_GIC400_AIHWACG_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_ISP_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_MFC_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_ISP_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_MFC_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_CAM_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_DPU_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_FSYS_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_G2D_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_USB_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX1_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX2_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL0_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL1_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_AXI_D0_MODEM_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_AXI_D1_MODEM_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_ABOX_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_APM_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_CSSYS_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_G3D_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_GNSS_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_SHUB_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_WLBT_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CPU_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CP_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_NRT_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_RT_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CPU_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CP_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_NRT_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_RT_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_APM_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CAM_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL0_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL1_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_DISPAUD_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_FSYS_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G2D_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G3D_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_GNSS_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_ISP_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MFC_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF0_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF1_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MODEM_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_PERI_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_SHUB_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_USB_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX1_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX2_CLK,
+	CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_WLBT_CLK,
+	CLK_CON_GAT_GOUT_CORE_PDMA_CORE_ACLK_PDMA0,
+	CLK_CON_GAT_GOUT_CORE_PGEN_LITE_SIREX_CLK,
+	CLK_CON_GAT_GOUT_CORE_PGEN_PDMA_CLK,
+	CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_ACLK,
+	CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_PCLK,
+	CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM0_CLK,
+	CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM1_CLK,
+	CLK_CON_GAT_GOUT_CORE_PPFW_CORE_PERI_CLK,
+	CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_ACLK,
+	CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_PCLK,
+	CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_ACLK,
+	CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_PCLK,
+	CLK_CON_GAT_GOUT_CORE_BUSD_CLK,
+	CLK_CON_GAT_GOUT_CORE_BUSP_G3D_OCC_CLK,
+	CLK_CON_GAT_GOUT_CORE_BUSP_CLK,
+	CLK_CON_GAT_GOUT_CORE_BUSP_OCC_CLK,
+	CLK_CON_GAT_GOUT_CORE_CCI_CLK,
+	CLK_CON_GAT_GOUT_CORE_CCI_OCC_CLK,
+	CLK_CON_GAT_GOUT_CORE_G3D_CLK,
+	CLK_CON_GAT_GOUT_CORE_G3D_OCC_CLK,
+	CLK_CON_GAT_GOUT_CORE_GIC_CLK,
+	CLK_CON_GAT_GOUT_CORE_OSCCLK_CLK,
+	CLK_CON_GAT_GOUT_CORE_SFR_APBIF_CMU_TOPC_PCLK,
+	CLK_CON_GAT_GOUT_CORE_SIREX_ACLK,
+	CLK_CON_GAT_GOUT_CORE_SIREX_PCLK,
+	CLK_CON_GAT_GOUT_CORE_SPDMA_CORE_ACLK_PDMA1,
+	CLK_CON_GAT_GOUT_CORE_SYSREG_PCLK,
+	CLK_CON_GAT_GOUT_CORE_TREX_D_ACLK,
+	CLK_CON_GAT_GOUT_CORE_TREX_D_CCLK,
+	CLK_CON_GAT_GOUT_CORE_TREX_D_GCLK,
+	CLK_CON_GAT_GOUT_CORE_TREX_D_PCLK,
+	CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_ACLK,
+	CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_PCLK,
+	CLK_CON_GAT_GOUT_CORE_TREX_P_ACLK_P_CORE,
+	CLK_CON_GAT_GOUT_CORE_TREX_P_CCLK_P_CORE,
+	CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK,
+	CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK_P_CORE,
+	CLK_CON_GAT_GOUT_CORE_XIU_D_ACLK,
+};
+
+PNAME(mout_pll_core_bus_user_p)		= { "oscclk",
+					    "dout_cmu_core_bus" };
+PNAME(mout_pll_core_cci_user_p)	=	 { "oscclk",
+					    "dout_cmu_core_cci" };
+PNAME(mout_pll_core_g3d_user_p)	=	 { "oscclk",
+					    "dout_cmu_core_g3d" };
+PNAME(mout_clk_core_gic_p)		= { "oscclk",
+					    "dout_clk_core_busp" };
+
+static const struct samsung_mux_clock core_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PLL_CORE_BUS_USER, "mout_pll_core_bus_user", mout_pll_core_bus_user_p,
+	    PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_CORE_CCI_USER, "mout_pll_core_cci_user", mout_pll_core_cci_user_p,
+	    PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_CORE_G3D_USER, "mout_pll_core_g3d_user", mout_pll_core_g3d_user_p,
+	    PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1),
+	MUX(CLK_MOUT_CLK_CORE_GIC, "mout_clk_core_gic", mout_clk_core_gic_p,
+	    CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
+};
+
+static const struct samsung_div_clock core_div_clks[] __initconst = {
+	DIV(CLK_DOUT_CLK_CORE_BUSP, "dout_clk_core_busp", "mout_pll_core_bus_user",
+	    CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
+};
+
+static const struct samsung_gate_clock core_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_CLK_CORE_CMU_PCLK, "gout_clk_core_cmu_pclk", "dout_clk_core_busp",
+	     CLK_CON_GAT_CLK_CORE_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_AD_APB_CCI_550_PCLKM, "gout_core_ad_apb_cci_550_pclkm",
+	     "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_AD_APB_CCI_550_PCLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_AD_APB_DIT_PCLKM, "gout_core_ad_apb_dit_pclkm",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_DIT_PCLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_AD_APB_PDMA0_PCLKM, "gout_core_ad_apb_pdma0_pclkm",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_PDMA0_PCLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_AD_APB_PGEN_PDMA_PCLKM, "gout_core_ad_apb_pgen_pdma_pclkm",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_PGEN_PDMA_PCLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_AD_APB_PPFW_MEM0_PCLKM, "gout_core_ad_apb_ppfw_mem0_pclkm",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM0_PCLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_AD_APB_PPFW_MEM1_PCLKM, "gout_core_ad_apb_ppfw_mem1_pclkm",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM1_PCLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_AD_APB_PPFW_PERI_PCLKM, "gout_core_ad_apb_ppfw_peri_pclkm",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_PERI_PCLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_AD_APB_SPDMA_PCLKM, "gout_core_ad_apb_spdma_pclkm",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_SPDMA_PCLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_AD_AXI_GIC_ACLKM, "gout_core_ad_axi_gic_aclkm",
+	     "mout_clk_core_gic", CLK_CON_GAT_GOUT_CORE_AD_AXI_GIC_ACLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_ASYNCSFR_WR_DMC0_PCLK, "gout_core_asyncsfr_wr_dmc0_pclk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC0_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_ASYNCSFR_WR_DMC1_PCLK, "gout_core_asyncsfr_wr_dmc1_pclk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC1_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_AXI_US_A40_64TO128_DIT_ACLK,
+	     "gout_core_axi_us_a40_64to128_dit_aclk", "mout_pll_core_bus_user",
+	     CLK_CON_GAT_GOUT_CORE_AXI_US_A40_64TO128_DIT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_BAAW_P_GNSS_PCLK, "gout_core_baaw_p_gnss_pclk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BAAW_P_GNSS_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_BAAW_P_MODEM_PCLK, "gout_core_baaw_p_modem_pclk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BAAW_P_MODEM_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_BAAW_P_SHUB_PCLK, "gout_core_baaw_p_shub_pclk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BAAW_P_SHUB_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_BAAW_P_WLBT_PCLK, "gout_core_baaw_p_wlbt_pclk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BAAW_P_WLBT_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_CCI_550_ACLK, "gout_core_cci_550_aclk",
+	     "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_DIT_ICLKL2A, "gout_core_dit_iclkl2a",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_DIT_ICLKL2A,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_GIC400_AIHWACG_CLK, "gout_core_gic400_aihwacg_clk",
+	     "mout_clk_core_gic", CLK_CON_GAT_GOUT_CORE_GIC400_AIHWACG_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACEL_D0_ISP_CLK, "gout_core_lhm_acel_d0_isp_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_ISP_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACEL_D0_MFC_CLK, "gout_core_lhm_acel_d0_mfc_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_MFC_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACEL_D1_ISP_CLK, "gout_core_lhm_acel_d1_isp_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_ISP_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACEL_D1_MFC_CLK, "gout_core_lhm_acel_d1_mfc_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_MFC_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACEL_D_CAM_CLK, "gout_core_lhm_acel_d_cam_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_CAM_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACEL_D_DPU_CLK, "gout_core_lhm_acel_d_dpu_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_DPU_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACEL_D_FSYS_CLK, "gout_core_lhm_acel_d_fsys_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_FSYS_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACEL_D_G2D_CLK, "gout_core_lhm_acel_d_g2d_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_G2D_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACEL_D_USB_CLK, "gout_core_lhm_acel_d_usb_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_USB_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACEL_D_VIPX1_CLK, "gout_core_lhm_acel_d_vipx1_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX1_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACEL_D_VIPX2_CLK, "gout_core_lhm_acel_d_vipx2_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX2_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACE_D_CPUCL0_CLK, "gout_core_lhm_ace_d_cpucl0_clk",
+	     "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL0_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_ACE_D_CPUCL1_CLK, "gout_core_lhm_ace_d_cpucl1_clk",
+	     "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL1_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_AXI_D0_MODEM_CLK, "gout_core_lhm_axi_d0_modem_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D0_MODEM_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_AXI_D1_MODEM_CLK, "gout_core_lhm_axi_d1_modem_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D1_MODEM_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_AXI_D_ABOX_CLK, "gout_core_lhm_axi_d_abox_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_ABOX_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_AXI_D_APM_CLK, "gout_core_lhm_axi_d_apm_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_APM_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_AXI_D_CSSYS_CLK, "gout_core_lhm_axi_d_cssys_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_CSSYS_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_AXI_D_G3D_CLK, "gout_core_lhm_axi_d_g3d_clk",
+	     "mout_pll_core_g3d_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_G3D_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_AXI_D_GNSS_CLK, "gout_core_lhm_axi_d_gnss_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_GNSS_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_AXI_D_SHUB_CLK, "gout_core_lhm_axi_d_shub_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_SHUB_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHM_AXI_D_WLBT_CLK, "gout_core_lhm_axi_d_wlbt_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_WLBT_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_D0_MIF_CPU_CLK, "gout_core_lhs_axi_d0_mif_cpu_clk",
+	     "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CPU_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_D0_MIF_CP_CLK, "gout_core_lhs_axi_d0_mif_cp_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CP_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_D0_MIF_NRT_CLK, "gout_core_lhs_axi_d0_mif_nrt_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_NRT_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_D0_MIF_RT_CLK, "gout_core_lhs_axi_d0_mif_rt_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_RT_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_D1_MIF_CPU_CLK, "gout_core_lhs_axi_d1_mif_cpu_clk",
+	     "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CPU_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_D1_MIF_CP_CLK, "gout_core_lhs_axi_d1_mif_cp_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CP_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_D1_MIF_NRT_CLK, "gout_core_lhs_axi_d1_mif_nrt_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_NRT_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_D1_MIF_RT_CLK, "gout_core_lhs_axi_d1_mif_rt_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_RT_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_APM_CLK, "gout_core_lhs_axi_p_apm_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_APM_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_CAM_CLK, "gout_core_lhs_axi_p_cam_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CAM_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_CPUCL0_CLK, "gout_core_lhs_axi_p_cpucl0_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL0_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_CPUCL1_CLK, "gout_core_lhs_axi_p_cpucl1_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL1_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_DISPAUD_CLK, "gout_core_lhs_axi_p_dispaud_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_DISPAUD_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_FSYS_CLK, "gout_core_lhs_axi_p_fsys_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_FSYS_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_G2D_CLK, "gout_core_lhs_axi_p_g2d_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G2D_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_G3D_CLK, "gout_core_lhs_axi_p_g3d_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G3D_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_GNSS_CLK, "gout_core_lhs_axi_p_gnss_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_GNSS_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_ISP_CLK, "gout_core_lhs_axi_p_isp_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_ISP_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_MFC_CLK, "gout_core_lhs_axi_p_mfc_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MFC_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_MIF0_CLK, "gout_core_lhs_axi_p_mif0_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF0_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_MIF1_CLK, "gout_core_lhs_axi_p_mif1_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF1_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_MODEM_CLK, "gout_core_lhs_axi_p_modem_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MODEM_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_PERI_CLK, "gout_core_lhs_axi_p_peri_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_PERI_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_SHUB_CLK, "gout_core_lhs_axi_p_shub_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_SHUB_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_USB_CLK, "gout_core_lhs_axi_p_usb_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_USB_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_VIPX1_CLK, "gout_core_lhs_axi_p_vipx1_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX1_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_VIPX2_CLK, "gout_core_lhs_axi_p_vipx2_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX2_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_LHS_AXI_P_WLBT_CLK, "gout_core_lhs_wlbt_p_apm_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_WLBT_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PDMA_CORE_ACLK_PDMA0, "gout_core_pdma_core_aclk_pdma0",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_PDMA_CORE_ACLK_PDMA0,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PGEN_LITE_SIREX_CLK, "gout_core_pgen_lite_sirex_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_PGEN_LITE_SIREX_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PGEN_PDMA_CLK, "gout_core_pgen_pdma_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_PGEN_PDMA_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PPCFW_G3D_ACLK, "gout_core_ppcfw_g3d_aclk",
+	     "mout_pll_core_g3d_user", CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PPCFW_G3D_PCLK, "gout_core_ppcfw_g3d_pclk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PPFW_CORE_MEM0_CLK, "gout_core_ppfw_core_mem0_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM0_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PPFW_CORE_MEM1_CLK, "gout_core_ppfw_core_mem1_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM1_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PPFW_CORE_PERI_CLK, "gout_core_ppfw_core_peri_clk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_PPFW_CORE_PERI_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PPMU_ACE_CPUCL0_ACLK, "gout_core_ppmu_ace_cpucl0_aclk",
+	     "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PPMU_ACE_CPUCL0_PCLK, "gout_core_ppmu_ace_cpucl0_pclk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PPMU_ACE_CPUCL1_ACLK, "gout_core_ppmu_ace_cpucl1_aclk",
+	     "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_PPMU_ACE_CPUCL1_PCLK, "gout_core_ppmu_ace_cpucl1_pclk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_BUSD_CLK, "gout_core_busd_clk", "mout_pll_core_bus_user",
+	     CLK_CON_GAT_GOUT_CORE_BUSD_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_BUSP_G3D_OCC_CLK, "gout_core_busp_g3d_occ_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BUSP_G3D_OCC_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_BUSP_CLK, "gout_core_busp_clk", "dout_clk_core_busp",
+	     CLK_CON_GAT_GOUT_CORE_BUSP_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_BUSP_OCC_CLK, "gout_core_busp_occ_clk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BUSP_OCC_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_CCI_CLK, "gout_core_cci_clk", "mout_pll_core_cci_user",
+	     CLK_CON_GAT_GOUT_CORE_CCI_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_CCI_OCC_CLK, "gout_core_cci_occ_clk",
+	     "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_CCI_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_G3D_CLK, "gout_core_g3d_clk", "mout_pll_core_g3d_user",
+	     CLK_CON_GAT_GOUT_CORE_G3D_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_G3D_OCC_CLK, "gout_core_cci_g3d_occ_clk",
+	     "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_G3D_OCC_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_GIC_CLK, "gout_core_gic_clk", "mout_clk_core_gic",
+	     CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, 0, 0),
+	GATE(CLK_GOUT_CORE_OSCCLK_CLK, "gout_core_oscclk_clk", "oscclk",
+	     CLK_CON_GAT_GOUT_CORE_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_SFR_APBIF_CMU_TOPC_PCLK, "gout_core_sfr_apbif_cmu_topc_pclk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_SFR_APBIF_CMU_TOPC_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_SIREX_ACLK, "gout_core_sirex_aclk", "mout_pll_core_bus_user",
+	     CLK_CON_GAT_GOUT_CORE_SIREX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_SIREX_PCLK, "gout_core_sirex_pclk", "dout_clk_core_busp",
+	     CLK_CON_GAT_GOUT_CORE_SIREX_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_SPDMA_CORE_ACLK_PDMA1, "gout_core_spdma_core_aclk_pdma1",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_SPDMA_CORE_ACLK_PDMA1,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_SYSREG_PCLK, "gout_core_sysreg_pclk", "dout_clk_core_busp",
+	     CLK_CON_GAT_GOUT_CORE_SYSREG_PCLK, 21, 0, 0),
+	GATE(CLK_GOUT_CORE_TREX_D_ACLK, "gout_core_trex_d_aclk", "mout_pll_core_bus_user",
+	     CLK_CON_GAT_GOUT_CORE_TREX_D_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_TREX_D_CCLK, "gout_core_trex_d_cclk", "mout_pll_core_cci_user",
+	     CLK_CON_GAT_GOUT_CORE_TREX_D_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_TREX_D_GCLK, "gout_core_trex_d_gclk", "mout_pll_core_g3d_user",
+	     CLK_CON_GAT_GOUT_CORE_TREX_D_GCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_TREX_D_PCLK, "gout_core_trex_d_pclk", "dout_clk_core_busp",
+	     CLK_CON_GAT_GOUT_CORE_TREX_D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_TREX_D_NRT_ACLK, "gout_core_trex_d_nrt_aclk",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_TREX_D_NRT_PCLK, "gout_core_trex_d_nrt_pclk",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+
+	GATE(CLK_GOUT_CORE_TREX_P_ACLK_P_CORE, "gout_core_trex_p_aclk_p_core",
+	     "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_P_ACLK_P_CORE,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_TREX_P_CCLK_P_CORE, "gout_core_trex_p_cclk_p_core",
+	     "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CCLK_P_CORE,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_TREX_P_PCLK, "gout_core_trex_p_pclk", "dout_clk_core_busp",
+	     CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_TREX_P_PCLK_P_CORE, "gout_core_trex_p_pclk_p_core",
+	     "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK_P_CORE,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CORE_XIU_D_ACLK, "gout_core_xiu_d_aclk", "mout_pll_core_bus_user",
+	     CLK_CON_GAT_GOUT_CORE_XIU_D_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info core_cmu_info __initconst = {
+	.mux_clks		= core_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(core_mux_clks),
+	.gate_clks		= core_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(core_gate_clks),
+	.clk_regs		= core_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(core_clk_regs),
+	.nr_clk_ids		= CLKS_NR_CORE,
+};
+
+/* CMU_DISPAUD */
+#define PLL_LOCKTIME_PLL_AUD					0x0000
+#define PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER			0x0100
+#define PLL_CON2_MUX_CLKCMU_DISPAUD_AUD_USER			0x0108
+#define PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER			0x0120
+#define PLL_CON2_MUX_CLKCMU_DISPAUD_CPU_USER			0x0128
+#define PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER			0x0140
+#define PLL_CON2_MUX_CLKCMU_DISPAUD_DISP_USER			0x0148
+#define PLL_CON0_PLL_AUD					0x0160
+#define PLL_CON3_PLL_AUD					0x016c
+#define CLK_CON_MUX_MUX_CLK_AUD_BUS				0x1000
+#define CLK_CON_MUX_MUX_CLK_AUD_CPU				0x1004
+#define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH				0x1008
+#define CLK_CON_MUX_MUX_CLK_AUD_FM				0x100c
+#define CLK_CON_MUX_MUX_CLK_AUD_UAIF0				0x1010
+#define CLK_CON_MUX_MUX_CLK_AUD_UAIF1				0x1014
+#define CLK_CON_MUX_MUX_CLK_AUD_UAIF2				0x1018
+#define CLK_CON_DIV_DIV_CLK_AUD_AUDIF				0x1800
+#define CLK_CON_DIV_DIV_CLK_AUD_BUS				0x1808
+#define CLK_CON_DIV_DIV_CLK_AUD_CPU				0x180c
+#define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK			0x1810
+#define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG			0x1814
+#define CLK_CON_DIV_DIV_CLK_AUD_DSIF				0x1818
+#define CLK_CON_DIV_DIV_CLK_AUD_FM				0x181c
+#define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY				0x1820
+#define CLK_CON_DIV_DIV_CLK_AUD_UAIF0				0x1824
+#define CLK_CON_DIV_DIV_CLK_AUD_UAIF1				0x1828
+#define CLK_CON_DIV_DIV_CLK_AUD_UAIF2				0x182c
+#define CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP			0x1830
+#define CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF0			0x2000
+#define CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF1			0x2004
+#define CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF2			0x2008
+#define CLK_CON_GAT_CLK_DISPAUD_CMU_PCLK			0x200c
+#define CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF0_CLK		0x2010
+#define CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF1_CLK		0x2014
+#define CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF2_CLK		0x2018
+#define CLK_CON_GAT_CLK_DISPAUD_OSCCLK_CLK			0x201c
+#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_ACLK			0x2020
+#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_DSIF			0x2024
+#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_SPDY			0x2028
+#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_ASB			0x202c
+#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_CA7			0x2030
+#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_DBG			0x2034
+#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_OSC_SPDY			0x2038
+#define CLK_CON_GAT_GOUT_DISPAUD_AXI_US_32TO128_ACLK		0x203c
+#define CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_AUD		0x2040
+#define CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_DISP		0x2044
+#define CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_ACLK			0x2048
+#define CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_PCLK			0x204c
+#define CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_ACLK			0x2050
+#define CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_PCLK			0x2054
+#define CLK_CON_GAT_GOUT_DISPAUD_DFTMUX_AUD_CODEC_MCLK		0x2058
+#define CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DECON			0x2060
+#define CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DMA			0x2064
+#define CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DPP			0x2068
+#define CLK_CON_GAT_GOUT_DISPAUD_GPIO_DISPAUD_PCLK		0x206c
+#define CLK_CON_GAT_GOUT_DISPAUD_LHM_AXI_P_DISPAUD_CLK		0x2070
+#define CLK_CON_GAT_GOUT_DISPAUD_LHS_ACEL_D_DPU_CLK		0x2074
+#define CLK_CON_GAT_GOUT_DISPAUD_LHS_AXI_D_ABOX_CLK		0x2078
+#define CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_ACLKM		0x207c
+#define CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_PCLK		0x2080
+#define CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_ACLK			0x2084
+#define CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_PCLK			0x2088
+#define CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_ACLK			0x208c
+#define CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_PCLK			0x2090
+#define CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_ACLK_CLK		0x2094
+#define CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_CLKIN_CLK		0x2098
+#define CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_PCLKDBG_CLK	0x209c
+#define CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_DSIF_CLK		0x20a0
+#define CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CLK			0x20a4
+#define CLK_CON_GAT_GOUT_DISPAUD_CLK_BUSP_CLK			0x20a8
+#define CLK_CON_GAT_GOUT_DISPAUD_CLK_DISP_CLK			0x20ac
+#define CLK_CON_GAT_GOUT_DISPAUD_SMMU_ABOX_CLK			0x20b0
+#define CLK_CON_GAT_GOUT_DISPAUD_SMMU_DPU_CLK			0x20b4
+#define CLK_CON_GAT_GOUT_DISPAUD_SYSREG_PCLK			0x20b8
+#define CLK_CON_GAT_GOUT_DISPAUD_WDT_AUD_PCLK			0x20bc
+
+static const unsigned long dispaud_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_AUD,
+	PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER,
+	PLL_CON2_MUX_CLKCMU_DISPAUD_AUD_USER,
+	PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER,
+	PLL_CON2_MUX_CLKCMU_DISPAUD_CPU_USER,
+	PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER,
+	PLL_CON2_MUX_CLKCMU_DISPAUD_DISP_USER,
+	PLL_CON0_PLL_AUD,
+	PLL_CON3_PLL_AUD,
+	CLK_CON_MUX_MUX_CLK_AUD_BUS,
+	CLK_CON_MUX_MUX_CLK_AUD_CPU,
+	CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH,
+	CLK_CON_MUX_MUX_CLK_AUD_FM,
+	CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
+	CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
+	CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
+	CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
+	CLK_CON_DIV_DIV_CLK_AUD_BUS,
+	CLK_CON_DIV_DIV_CLK_AUD_CPU,
+	CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
+	CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
+	CLK_CON_DIV_DIV_CLK_AUD_DSIF,
+	CLK_CON_DIV_DIV_CLK_AUD_FM,
+	CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY,
+	CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
+	CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
+	CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
+	CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP,
+	CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF0,
+	CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF1,
+	CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF2,
+	CLK_CON_GAT_CLK_DISPAUD_CMU_PCLK,
+	CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF0_CLK,
+	CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF1_CLK,
+	CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF2_CLK,
+	CLK_CON_GAT_CLK_DISPAUD_OSCCLK_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_ABOX_ACLK,
+	CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_DSIF,
+	CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_SPDY,
+	CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_ASB,
+	CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_CA7,
+	CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_DBG,
+	CLK_CON_GAT_GOUT_DISPAUD_ABOX_OSC_SPDY,
+	CLK_CON_GAT_GOUT_DISPAUD_AXI_US_32TO128_ACLK,
+	CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_AUD,
+	CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_DISP,
+	CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_ACLK,
+	CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_PCLK,
+	CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_ACLK,
+	CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_PCLK,
+	CLK_CON_GAT_GOUT_DISPAUD_DFTMUX_AUD_CODEC_MCLK,
+	CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DECON,
+	CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DMA,
+	CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DPP,
+	CLK_CON_GAT_GOUT_DISPAUD_GPIO_DISPAUD_PCLK,
+	CLK_CON_GAT_GOUT_DISPAUD_LHM_AXI_P_DISPAUD_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_LHS_ACEL_D_DPU_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_LHS_AXI_D_ABOX_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_ACLKM,
+	CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_PCLK,
+	CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_ACLK,
+	CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_PCLK,
+	CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_ACLK,
+	CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_PCLK,
+	CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_ACLK_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_CLKIN_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_PCLKDBG_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_DSIF_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_CLK_BUSP_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_CLK_DISP_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_SMMU_ABOX_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_SMMU_DPU_CLK,
+	CLK_CON_GAT_GOUT_DISPAUD_SYSREG_PCLK,
+	CLK_CON_GAT_GOUT_DISPAUD_WDT_AUD_PCLK,
+};
+
+static const struct samsung_pll_rate_table pll_aud_rate_table[] __initconst = {
+	PLL_36XX_RATE(26 * MHZ, 1179648040, 45, 1, 0, 24319),
+	PLL_36XX_RATE(26 * MHZ, 1083801605, 42, 1, 0, -20665),
+};
+
+static const struct samsung_pll_clock dispaud_pll_clks[] __initconst = {
+	PLL(pll_1061x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_AUD, PLL_CON0_PLL_AUD, pll_aud_rate_table),
+};
+
+PNAME(mout_pll_dispaud_aud_user_p)	= { "oscclk",
+					    "dout_cmu_dispaud_aud" };
+PNAME(mout_pll_dispaud_cpu_user_p)	= { "oscclk",
+					    "dout_cmu_dispaud_cpu" };
+PNAME(mout_pll_dispaud_disp_user_p)	= { "oscclk",
+					    "dout_cmu_dispaud_disp" };
+PNAME(mout_clk_aud_bus_p)		= { "dout_clk_aud_bus",
+					    "mout_pll_dispaud_aud_user" };
+PNAME(mout_clk_aud_cpu_p)		= { "dout_clk_aud_cpu",
+					    "mout_pll_dispaud_cpu_user" };
+PNAME(mout_clk_aud_cpu_hch_p)		= { "mout_clk_aud_cpu", "oscclk" };
+PNAME(mout_clk_aud_fm_p)		= { "oscclk",
+					    "dout_clk_aud_fm_spdy" };
+PNAME(mout_clk_aud_uaif0_p)		= { "dout_clk_aud_uaif0",
+					    "ioclk_audiocdclk0" };
+PNAME(mout_clk_aud_uaif1_p)		= { "dout_clk_aud_uaif1",
+					    "ioclk_audiocdclk1" };
+PNAME(mout_clk_aud_uaif2_p)		= { "dout_clk_aud_uaif2",
+					    "ioclk_audiocdclk0" };
+
+static const struct samsung_mux_clock dispaud_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PLL_DISPAUD_AUD_USER, "mout_pll_dispaud_aud_user", mout_pll_dispaud_aud_user_p,
+	    PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_DISPAUD_CPU_USER, "mout_pll_dispaud_cpu_user", mout_pll_dispaud_cpu_user_p,
+	    PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_DISPAUD_DISP_USER, "mout_pll_dispaud_disp_user",
+	    mout_pll_dispaud_disp_user_p, PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER, 4, 1),
+	MUX(CLK_MOUT_CLK_AUD_BUS, "mout_clk_aud_bus", mout_clk_aud_bus_p,
+	    CLK_CON_MUX_MUX_CLK_AUD_BUS, 0, 1),
+	MUX(CLK_MOUT_CLK_AUD_CPU, "mout_clk_aud_cpu", mout_clk_aud_cpu_p,
+	    CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
+	MUX(CLK_MOUT_CLK_AUD_CPU_HCH, "mout_clk_aud_cpu_hch", mout_clk_aud_cpu_hch_p,
+	    CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
+	MUX(CLK_MOUT_CLK_AUD_FM, "mout_clk_aud_fm", mout_clk_aud_fm_p,
+	    CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
+	MUX(CLK_MOUT_CLK_AUD_UAIF0, "mout_clk_aud_uaif0", mout_clk_aud_uaif0_p,
+	    CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
+	MUX(CLK_MOUT_CLK_AUD_UAIF1, "mout_clk_aud_uaif1", mout_clk_aud_uaif1_p,
+	    CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
+	MUX(CLK_MOUT_CLK_AUD_UAIF2, "mout_clk_aud_uaif2", mout_clk_aud_uaif2_p,
+	    CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
+};
+
+static const struct samsung_div_clock dispaud_div_clks[] __initconst = {
+	DIV(CLK_DOUT_CLK_AUD_AUDIF, "dout_clk_aud_audif", "fout_aud_pll",
+	    CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
+	DIV(CLK_DOUT_CLK_AUD_BUS, "dout_clk_aud_bus", "fout_aud_pll",
+	    CLK_CON_DIV_DIV_CLK_AUD_BUS, 0, 3),
+	DIV(CLK_DOUT_CLK_AUD_CPU, "dout_clk_aud_cpu", "fout_aud_pll",
+	    CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
+	DIV(CLK_DOUT_CLK_AUD_CPU_ACLK, "dout_clk_aud_cpu_aclk", "mout_clk_aud_cpu_hch",
+	    CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
+	DIV(CLK_DOUT_CLK_AUD_CPU_PCLKDBG, "dout_clk_aud_cpu_pclkdbg", "mout_clk_aud_cpu_hch",
+	    CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
+	DIV(CLK_DOUT_CLK_AUD_DSIF, "dout_clk_aud_dsif", "dout_clk_aud_audif",
+	    CLK_CON_DIV_DIV_CLK_AUD_DSIF, 0, 9),
+	DIV(CLK_DOUT_CLK_AUD_FM, "dout_clk_aud_fm", "mout_clk_aud_fm",
+	    CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 9),
+	DIV(CLK_DOUT_CLK_AUD_FM_SPDY, "dout_clk_aud_fm_spdy", "tick_usb",
+	    CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 9),
+	DIV(CLK_DOUT_CLK_AUD_UAIF0, "dout_clk_aud_uaif0", "dout_clk_aud_audif",
+	    CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 9),
+	DIV(CLK_DOUT_CLK_AUD_UAIF1, "dout_clk_aud_uaif1", "dout_clk_aud_audif",
+	    CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 9),
+	DIV(CLK_DOUT_CLK_AUD_UAIF2, "dout_clk_aud_uaif2", "dout_clk_aud_audif",
+	    CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 9),
+	DIV(CLK_DOUT_CLK_DISPAUD_BUSP, "dout_clk_dispaud_busp", "mout_pll_dispaud_disp_user",
+	    CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP, 0, 3),
+};
+
+static const struct samsung_gate_clock dispaud_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF0, "gout_clk_dispaud_abox_bclk_uaif0",
+	     "mout_clk_aud_uaif0", CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF0,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF1, "gout_clk_dispaud_abox_bclk_uaif1",
+	     "mout_clk_aud_uaif1", CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF1,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF2, "gout_clk_dispaud_abox_bclk_uaif2",
+	     "mout_clk_aud_uaif2", CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF2,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_DISPAUD_CMU_PCLK, "gout_clk_dispaud_cmu_pclk",
+	     "dout_clk_dispaud_busp", CLK_CON_GAT_CLK_DISPAUD_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF0_CLK, "gout_clk_dispaud_clk_aud_uaif0_clk",
+	     "mout_clk_aud_uaif0", CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF0_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF1_CLK, "gout_clk_dispaud_clk_aud_uaif1_clk",
+	     "mout_clk_aud_uaif1", CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF1_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF2_CLK, "gout_clk_dispaud_clk_aud_uaif2_clk",
+	     "mout_clk_aud_uaif2", CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF2_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_DISPAUD_OSCCLK_CLK, "gout_clk_dispaud_oscclk_clk", "oscclk",
+	     CLK_CON_GAT_CLK_DISPAUD_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_ABOX_ACLK, "gout_clk_dispaud_abox_aclk", "mout_clk_aud_bus",
+	     CLK_CON_GAT_GOUT_DISPAUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_ABOX_BCLK_DSIF, "gout_clk_dispaud_abox_bclk_dsif",
+	     "dout_clk_aud_dsif", CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_DSIF,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_ABOX_BCLK_SPDY, "gout_clk_dispaud_abox_bclk_spdy",
+	     "dout_clk_aud_fm", CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_SPDY,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_ABOX_CCLK_ASB, "gout_clk_dispaud_abox_cclk_asb",
+	     "dout_clk_aud_cpu_aclk", CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_ASB,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_ABOX_CCLK_CA7, "gout_clk_dispaud_abox_cclk_ca7",
+	     "mout_clk_aud_cpu_hch", CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_CA7,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_ABOX_CCLK_DBG, "gout_clk_dispaud_abox_cclk_dbg",
+	     "dout_clk_aud_cpu_pclkdbg", CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_DBG,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_ABOX_OSC_SPDY, "gout_clk_dispaud_abox_osc_spdy",
+	     "mout_clk_aud_fm", CLK_CON_GAT_GOUT_DISPAUD_ABOX_OSC_SPDY, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_AXI_US_32TO128_ACLK, "gout_dispaud_axi_us_32to128_aclk",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_AXI_US_32TO128_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_CLK_DISPAUD_AUD, "gout_dispaud_clk_dispaud_aud",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_AUD,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_CLK_DISPAUD_DISP, "gout_dispaud_clk_dispaud_disp",
+	     "mout_pll_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_DISP,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_BTM_ABOX_ACLK, "gout_dispaud_btm_abox_aclk", "mout_clk_aud_bus",
+	     CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_BTM_ABOX_PCLK, "gout_dispaud_btm_abox_pclk",
+	     "dout_clk_dispaud_busp", CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_BTM_DPU_ACLK, "gout_dispaud_btm_dpu_aclk",
+	     "mout_cmu_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_BTM_DPU_PCLK, "gout_dispaud_btm_dpu_pclk",
+	     "dout_clk_dispaud_busp", CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_DFTMUX_AUD_CODEC_MCLK, "gout_dispaud_dftmux_aud_codec_mclk",
+	     "dout_clk_aud_audif", CLK_CON_GAT_GOUT_DISPAUD_DFTMUX_AUD_CODEC_MCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_DPU_ACLK_DECON, "gout_dispaud_dpu_aclk_decon",
+	     "mout_pll_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DECON,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_DPU_ACLK_DMA, "gout_dispaud_dpu_aclk_dma",
+	     "mout_pll_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DMA,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_DPU_ACLK_DPP, "gout_dispaud_dpu_aclk_dpp",
+	     "mout_pll_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DPP,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_GPIO_DISPAUD_PCLK, "gout_dispaud_gpio_dispaud_pclk",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_GPIO_DISPAUD_PCLK,
+	     21, 0, 0),
+	GATE(CLK_GOUT_DISPAUD_LHM_AXI_P_DISPAUD_CLK, "gout_dispaud_lhm_axi_p_dispaud_clk",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_LHM_AXI_P_DISPAUD_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_LHS_ACEL_D_DPU_CLK, "gout_dispaud_lhs_acel_d_dpu_clk",
+	     "mout_cmu_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_LHS_ACEL_D_DPU_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_LHS_AXI_D_ABOX_CLK, "gout_dispaud_lhs_axi_d_abox_clk",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_LHS_AXI_D_ABOX_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_PERI_AXI_ASB_ACLKM, "gout_dispaud_peri_axi_asb_aclkm",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_ACLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_PERI_AXI_ASB_PCLK, "gout_dispaud_peri_axi_asb_pclk",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_PPMU_ABOX_ACLK, "gout_dispaud_ppmu_abox_aclk",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_PPMU_ABOX_PCLK, "gout_dispaud_ppmu_abox_pclk",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_PPMU_DPU_ACLK, "gout_dispaud_ppmu_dpu_aclk",
+	     "mout_cmu_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_PPMU_DPU_PCLK, "gout_dispaud_ppmu_dpu_pclk",
+	     "dout_clk_dispaud_busp", CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_CLK_AUD_CPU_ACLK_CLK,
+	     "gout_dispaud_clk_aud_cpu_aclk_clk", "dout_clk_aud_cpu_aclk",
+	     CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_ACLK_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_CLK_AUD_CPU_CLKIN_CLK,
+	     "gout_dispaud_clk_aud_cpu_clkin_clk", "mout_clk_aud_cpu_hch",
+	     CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_CLKIN_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_CLK_AUD_CPU_PCLKDBG_CLK,
+	     "gout_dispaud_clk_aud_cpu_pclkdbg_clk", "dout_clk_aud_cpu_pclkdbg",
+	     CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_PCLKDBG_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_CLK_AUD_DSIF_CLK, "gout_dispaud_clk_aud_dsif_clk",
+	     "dout_clk_aud_dsif", CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_DSIF_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_CLK_AUD_CLK, "gout_dispaud_clk_aud_clk",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_CLK_BUSP_CLK, "gout_dispaud_clk_busp_clk",
+	     "dout_clk_dispaud_busp", CLK_CON_GAT_GOUT_DISPAUD_CLK_BUSP_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_CLK_DISP_CLK, "gout_dispaud_clk_disp_clk",
+	     "mout_cmu_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_CLK_DISP_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_SMMU_ABOX_CLK, "gout_dispaud_smmu_abox_clk",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_SMMU_ABOX_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_SMMU_DPU_CLK, "gout_dispaud_smmu_dpu_clk",
+	     "mout_cmu_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_SMMU_DPU_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_DISPAUD_SYSREG_PCLK, "gout_dispaud_sysreg_pclk",
+	     "dout_clk_dispaud_busp", CLK_CON_GAT_GOUT_DISPAUD_SYSREG_PCLK,
+	     21, 0, 0),
+	GATE(CLK_GOUT_DISPAUD_WDT_AUD_PCLK, "gout_dispaud_wdt_aud_pclk",
+	     "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_WDT_AUD_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info dispaud_cmu_info __initconst = {
+	.pll_clks = dispaud_pll_clks,
+	.nr_pll_clks = ARRAY_SIZE(dispaud_pll_clks),
+	.mux_clks = dispaud_mux_clks,
+	.nr_mux_clks = ARRAY_SIZE(dispaud_mux_clks),
+	.div_clks = dispaud_div_clks,
+	.nr_div_clks = ARRAY_SIZE(dispaud_div_clks),
+	.gate_clks = dispaud_gate_clks,
+	.nr_gate_clks = ARRAY_SIZE(dispaud_gate_clks),
+	.nr_clk_ids = CLKS_NR_DISPAUD,
+	.clk_regs = dispaud_clk_regs,
+	.nr_clk_regs = ARRAY_SIZE(dispaud_clk_regs),
+};
+
+/* CMU_FSYS */
+#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER		0x0100
+#define PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER		0x0108
+#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER		0x0120
+#define PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER		0x0128
+#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER		0x0140
+#define PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER		0x0148
+#define PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER		0x0160
+#define PLL_CON2_MUX_CLKCMU_FSYS_UFS_EMBD_USER		0x0168
+#define CLK_CON_GAT_CLK_FSYS_CMU_PCLK			0x2000
+#define CLK_CON_GAT_CLK_FSYS_OSCCLK_CLK			0x2004
+#define CLK_CON_GAT_GOUT_FSYS_ADM_AHB_SSS_HCLKM		0x2008
+#define CLK_CON_GAT_GOUT_FSYS_BTM_ACLK			0x200c
+#define CLK_CON_GAT_GOUT_FSYS_BTM_PCLK			0x2010
+#define CLK_CON_GAT_GOUT_FSYS_GPIO_PCLK			0x2014
+#define CLK_CON_GAT_GOUT_FSYS_LHM_AXI_P_CLK		0x2018
+#define CLK_CON_GAT_GOUT_FSYS_LHS_ACEL_D_CLK		0x201c
+#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_ACLK		0x2020
+#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN		0x2024
+#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_ACLK		0x2028
+#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN		0x202c
+#define CLK_CON_GAT_GOUT_FSYS_PGEN_LITE_CLK		0x2030
+#define CLK_CON_GAT_GOUT_FSYS_PPMU_ACLK			0x2034
+#define CLK_CON_GAT_GOUT_FSYS_PPMU_PCLK			0x2038
+#define CLK_CON_GAT_GOUT_FSYS_BUS_CLK			0x203c
+#define CLK_CON_GAT_GOUT_FSYS_RTIC_ACLK			0x2040
+#define CLK_CON_GAT_GOUT_FSYS_RTIC_PCLK			0x2044
+#define CLK_CON_GAT_GOUT_FSYS_SSS_ACLK			0x2048
+#define CLK_CON_GAT_GOUT_FSYS_SSS_PCLK			0x204c
+#define CLK_CON_GAT_GOUT_FSYS_SYSREG_PCLK		0x2050
+#define CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_ACLK		0x2054
+#define CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_CLK_UNIPRO	0x2058
+#define CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_FMP_CLK		0x205c
+#define CLK_CON_GAT_GOUT_FSYS_XIU_D_ACLK		0x2060
+
+static const unsigned long fsys_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,
+	PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER,
+	PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
+	PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER,
+	PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
+	PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
+	PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER,
+	PLL_CON2_MUX_CLKCMU_FSYS_UFS_EMBD_USER,
+	CLK_CON_GAT_CLK_FSYS_CMU_PCLK,
+	CLK_CON_GAT_CLK_FSYS_OSCCLK_CLK,
+	CLK_CON_GAT_GOUT_FSYS_ADM_AHB_SSS_HCLKM,
+	CLK_CON_GAT_GOUT_FSYS_BTM_ACLK,
+	CLK_CON_GAT_GOUT_FSYS_BTM_PCLK,
+	CLK_CON_GAT_GOUT_FSYS_GPIO_PCLK,
+	CLK_CON_GAT_GOUT_FSYS_LHM_AXI_P_CLK,
+	CLK_CON_GAT_GOUT_FSYS_LHS_ACEL_D_CLK,
+	CLK_CON_GAT_GOUT_FSYS_MMC_CARD_ACLK,
+	CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_ACLK,
+	CLK_CON_GAT_GOUT_FSYS_PGEN_LITE_CLK,
+	CLK_CON_GAT_GOUT_FSYS_PPMU_ACLK,
+	CLK_CON_GAT_GOUT_FSYS_PPMU_PCLK,
+	CLK_CON_GAT_GOUT_FSYS_BUS_CLK,
+	CLK_CON_GAT_GOUT_FSYS_SYSREG_PCLK,
+	CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_ACLK,
+	CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_FMP_CLK,
+	CLK_CON_GAT_GOUT_FSYS_XIU_D_ACLK,
+};
+
+PNAME(mout_pll_fsys_bus_user_p)		= { "oscclk",
+					    "dout_cmu_fsys_bus" };
+PNAME(mout_pll_fsys_mmc_card_user_p)	= { "oscclk",
+					    "dout_cmu_fsys_mmc_card" };
+PNAME(mout_pll_fsys_mmc_embd_user_p)	= { "oscclk",
+					    "dout_cmu_fsys_mmc_embd" };
+PNAME(mout_pll_fsys_ufs_embd_user_p)	= { "oscclk",
+					    "dout_cmu_fsys_ufs_embd" };
+
+static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PLL_FSYS_BUS_USER, "mout_pll_fsys_bus_user", mout_pll_fsys_bus_user_p,
+	    PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_FSYS_MMC_CARD_USER, "mout_pll_fsys_mmc_card_user",
+	    mout_pll_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_FSYS_MMC_EMBD_USER, "mout_pll_fsys_mmc_embd_user",
+	    mout_pll_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_FSYS_UFS_EMBD_USER, "mout_pll_fsys_ufs_embd_user",
+	    mout_pll_fsys_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER, 4, 1),
+};
+
+static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_FSYS_CMU_PCLK, "gout_fsys_cmu_pclk", "mout_pll_fsys_bus_user",
+	     CLK_CON_GAT_CLK_FSYS_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_OSCCLK_CLK, "gout_fsys_oscclk_clk", "oscclk",
+	     CLK_CON_GAT_CLK_FSYS_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_ADM_AHB_SSS_HCLKM, "gout_fsys_adm_ahb_sss_hclkm",
+	     "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_ADM_AHB_SSS_HCLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_BTM_ACLK, "gout_fsys_btm_aclk", "mout_pll_fsys_bus_user",
+	     CLK_CON_GAT_GOUT_FSYS_BTM_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_BTM_PCLK, "gout_fsys_btm_pclk", "mout_pll_fsys_bus_user",
+	     CLK_CON_GAT_GOUT_FSYS_BTM_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_GPIO_PCLK, "gout_fsys_gpio_pclk", "mout_pll_fsys_bus_user",
+	     CLK_CON_GAT_GOUT_FSYS_GPIO_PCLK, 21, 0, 0),
+	GATE(CLK_GOUT_FSYS_LHM_AXI_P_CLK, "gout_fsys_lhm_axi_p_clk",
+	     "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_LHM_AXI_P_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_LHS_ACEL_D_CLK, "gout_fsys_lhs_acel_d_clk",
+	     "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_LHS_ACEL_D_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_MMC_CARD_ACLK, "gout_fsys_mmc_card_aclk",
+	     "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_MMC_CARD_SDCLKIN, "gout_fsys_mmc_card_sdclkin",
+	     "mout_pll_fsys_mmc_card_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_MMC_EMBD_ACLK, "gout_fsys_mmc_embd_aclk",
+	     "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_MMC_EMBD_SDCLKIN, "gout_fsys_mmc_embd_sdclkin",
+	     "mout_pll_fsys_mmc_embd_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_PGEN_LITE_CLK, "gout_fsys_pgen_lite_clk",
+	     "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_PGEN_LITE_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_PPMU_ACLK, "gout_fsys_ppmu_aclk", "mout_pll_fsys_bus_user",
+	     CLK_CON_GAT_GOUT_FSYS_PPMU_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_PPMU_PCLK, "gout_fsys_ppmu_pclk", "mout_pll_fsys_bus_user",
+	     CLK_CON_GAT_GOUT_FSYS_PPMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_BUS_CLK, "gout_fsys_bus_clk", "mout_pll_fsys_bus_user",
+	     CLK_CON_GAT_GOUT_FSYS_BUS_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_SYSREG_PCLK, "gout_fsys_sysreg_pclk", "mout_pll_fsys_bus_user",
+	     CLK_CON_GAT_GOUT_FSYS_SYSREG_PCLK, 21, 0, 0),
+	GATE(CLK_GOUT_FSYS_UFS_EMBD_ACLK, "gout_fsys_ufs_embd_aclk",
+	     "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_ACLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_UFS_EMBD_CLK_UNIPRO, "gout_fsys_ufs_embd_clk_unipro",
+	     "mout_pll_fsys_ufs_embd_user", CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_CLK_UNIPRO,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_UFS_EMBD_FMP_CLK, "gout_fsys_ufs_embd_fmp_clk",
+	     "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_FMP_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_FSYS_XIU_D_ACLK, "gout_fsys_xiu_d_aclk", "mout_pll_fsys_bus_user",
+	     CLK_CON_GAT_GOUT_FSYS_XIU_D_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info fsys_cmu_info __initconst = {
+	.mux_clks		= fsys_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(fsys_mux_clks),
+	.gate_clks		= fsys_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(fsys_gate_clks),
+	.clk_regs		= fsys_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(fsys_clk_regs),
+	.nr_clk_ids		= CLKS_NR_FSYS,
+};
+
+/* CMU_G2D */
+#define PLL_CON0_MUX_CLKCMU_G2D_G2D_USER	0x0100
+#define PLL_CON2_MUX_CLKCMU_G2D_G2D_USER	0x0108
+#define PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER	0x0120
+#define PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER	0x0128
+#define CLK_CON_DIV_DIV_CLK_G2D_BUSP		0x1800
+#define CLK_CON_GAT_CLK_G2D_CMU_PCLK		0x2000
+#define CLK_CON_GAT_CLK_G2D_OSCCLK_CLK		0x2004
+#define CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKM	0x2008
+#define CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKS	0x200c
+#define CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKM	0x2010
+#define CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKS	0x2014
+#define CLK_CON_GAT_GOUT_G2D_CLK_G2D_G2D	0x2018
+#define CLK_CON_GAT_GOUT_G2D_CLK_G2D_MSCL	0x201c
+#define CLK_CON_GAT_GOUT_G2D_BTM_G2D_ACLK	0x2020
+#define CLK_CON_GAT_GOUT_G2D_BTM_G2D_PCLK	0x2024
+#define CLK_CON_GAT_GOUT_G2D_G2D_ACLK		0x2028
+#define CLK_CON_GAT_GOUT_G2D_JPEG_FIMP_CLK	0x202c
+#define CLK_CON_GAT_GOUT_G2D_LHM_AXI_P_CLK	0x2030
+#define CLK_CON_GAT_GOUT_G2D_LHS_ACEL_D_CLK	0x2034
+#define CLK_CON_GAT_GOUT_G2D_MSCL_ACLK		0x2038
+#define CLK_CON_GAT_GOUT_G2D_PGEN100_LITE_CLK	0x203c
+#define CLK_CON_GAT_GOUT_G2D_PPMU_ACLK		0x2040
+#define CLK_CON_GAT_GOUT_G2D_PPMU_PCLK		0x2044
+#define CLK_CON_GAT_GOUT_G2D_BUSP_CLK		0x2048
+#define CLK_CON_GAT_GOUT_G2D_G2D_CLK		0x204c
+#define CLK_CON_GAT_GOUT_G2D_MSCL_CLK		0x2050
+#define CLK_CON_GAT_GOUT_G2D_SYSMMU_CLK		0x2054
+#define CLK_CON_GAT_GOUT_G2D_SYSREG_PCLK	0x2058
+#define CLK_CON_GAT_GOUT_G2D_XIU_D_MSCL_ACLK	0x205c
+
+static const unsigned long g2d_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLKCMU_G2D_G2D_USER,
+	PLL_CON2_MUX_CLKCMU_G2D_G2D_USER,
+	PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER,
+	PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER,
+	CLK_CON_DIV_DIV_CLK_G2D_BUSP,
+	CLK_CON_GAT_CLK_G2D_CMU_PCLK,
+	CLK_CON_GAT_CLK_G2D_OSCCLK_CLK,
+	CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKM,
+	CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKS,
+	CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKM,
+	CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKS,
+	CLK_CON_GAT_GOUT_G2D_CLK_G2D_G2D,
+	CLK_CON_GAT_GOUT_G2D_CLK_G2D_MSCL,
+	CLK_CON_GAT_GOUT_G2D_BTM_G2D_ACLK,
+	CLK_CON_GAT_GOUT_G2D_BTM_G2D_PCLK,
+	CLK_CON_GAT_GOUT_G2D_G2D_ACLK,
+	CLK_CON_GAT_GOUT_G2D_JPEG_FIMP_CLK,
+	CLK_CON_GAT_GOUT_G2D_LHM_AXI_P_CLK,
+	CLK_CON_GAT_GOUT_G2D_LHS_ACEL_D_CLK,
+	CLK_CON_GAT_GOUT_G2D_MSCL_ACLK,
+	CLK_CON_GAT_GOUT_G2D_PGEN100_LITE_CLK,
+	CLK_CON_GAT_GOUT_G2D_PPMU_ACLK,
+	CLK_CON_GAT_GOUT_G2D_PPMU_PCLK,
+	CLK_CON_GAT_GOUT_G2D_BUSP_CLK,
+	CLK_CON_GAT_GOUT_G2D_G2D_CLK,
+	CLK_CON_GAT_GOUT_G2D_MSCL_CLK,
+	// CLK_CON_GAT_GOUT_G2D_SYSMMU_CLK, // wronly
+	CLK_CON_GAT_GOUT_G2D_SYSREG_PCLK,
+	CLK_CON_GAT_GOUT_G2D_XIU_D_MSCL_ACLK,
+};
+
+PNAME(mout_pll_g2d_g2d_user_p) = { "oscclk", "dout_cmu_g2d_g2d" };
+PNAME(mout_pll_g2d_mscl_user_p) = { "oscclk", "dout_cmu_g2d_mscl" };
+
+static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_PLL_G2D_G2D_USER, "mout_pll_g2d_g2d_user", mout_pll_g2d_g2d_user_p,
+	    PLL_CON0_MUX_CLKCMU_G2D_G2D_USER, 4, 1),
+	MUX(CLK_MOUT_PLL_G2D_MSCL_USER, "mout_pll_g2d_mscl_user", mout_pll_g2d_mscl_user_p,
+	    PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER, 4, 1),
+};
+
+static const struct samsung_div_clock g2d_div_clks[] __initconst = {
+	DIV(CLK_DOUT_CLK_G2D_BUSP, "dout_clk_g2d_busp", "mout_pll_g2d_mscl_user",
+	    CLK_CON_DIV_DIV_CLK_G2D_BUSP, 0, 3),
+};
+
+static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_CLK_G2D_CMU_PCLK, "gout_clk_g2d_cmu_pclk", "dout_clk_g2d_busp",
+	     CLK_CON_GAT_CLK_G2D_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_G2D_OSCCLK_CLK, "gout_clk_g2d_oscclk_clk", "oscclk",
+	     CLK_CON_GAT_CLK_G2D_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_AS_AXI_JPEG_ACLKM, "gout_g2d_as_axi_jpeg_aclkm",
+	     "mout_pll_g2d_g2d_user", CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_AS_AXI_JPEG_ACLKS, "gout_g2d_as_axi_jpeg_aclks",
+	     "mout_pll_g2d_mscl_user", CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKS,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_AS_AXI_MSCL_ACLKM, "gout_g2d_as_axi_mscl_aclkm",
+	     "mout_pll_g2d_g2d_user", CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKM,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_AS_AXI_MSCL_ACLKS, "gout_g2d_as_axi_mscl_aclks",
+	     "mout_pll_g2d_mscl_user", CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKS,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_CLK_G2D_G2D, "gout_g2d_clk_g2d_g2d", "mout_pll_g2d_g2d_user",
+	     CLK_CON_GAT_GOUT_G2D_CLK_G2D_G2D, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_CLK_G2D_MSCL, "gout_g2d_clk_g2d_mscl", "mout_pll_g2d_mscl_user",
+	     CLK_CON_GAT_GOUT_G2D_CLK_G2D_MSCL, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_BTM_G2D_ACLK, "gout_g2d_btm_g2d_aclk", "mout_pll_g2d_g2d_user",
+	     CLK_CON_GAT_GOUT_G2D_BTM_G2D_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_BTM_G2D_PCLK, "gout_g2d_btm_g2d_pclk", "dout_clk_g2d_busp",
+	     CLK_CON_GAT_GOUT_G2D_BTM_G2D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_G2D_ACLK, "gout_g2d_g2d_aclk", "mout_pll_g2d_g2d_user",
+	     CLK_CON_GAT_GOUT_G2D_G2D_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_JPEG_FIMP_CLK, "gout_g2d_jpeg_fimp_clk", "mout_pll_g2d_mscl_user",
+	     CLK_CON_GAT_GOUT_G2D_JPEG_FIMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_LHM_AXI_P_CLK, "gout_g2d_lhm_axi_p_clk", "dout_clk_g2d_busp",
+	     CLK_CON_GAT_GOUT_G2D_LHM_AXI_P_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_LHS_ACEL_D_CLK, "gout_g2d_lhs_acel_d_clk", "mout_pll_g2d_mscl_user",
+	     CLK_CON_GAT_GOUT_G2D_LHS_ACEL_D_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_MSCL_ACLK, "gout_g2d_mscl_aclk", "mout_pll_g2d_mscl_user",
+	     CLK_CON_GAT_GOUT_G2D_MSCL_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_PGEN100_LITE_CLK, "gout_g2d_pgen100_lite_clk", "dout_clk_g2d_busp",
+	     CLK_CON_GAT_GOUT_G2D_PGEN100_LITE_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_PPMU_ACLK, "gout_g2d_ppmu_aclk", "mout_pll_g2d_g2d_user",
+	     CLK_CON_GAT_GOUT_G2D_PPMU_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_PPMU_PCLK, "gout_g2d_ppmu_pclk", "dout_clk_g2d_busp",
+	     CLK_CON_GAT_GOUT_G2D_PPMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_BUSP_CLK, "gout_g2d_busp_clk", "dout_clk_g2d_busp",
+	     CLK_CON_GAT_GOUT_G2D_BUSP_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_SYSMMU_CLK, "gout_g2d_sysmmu_clk", "mout_pll_g2d_g2d_user",
+	     CLK_CON_GAT_GOUT_G2D_SYSMMU_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G2D_SYSREG_PCLK, "gout_g2d_sysreg_pclk", "dout_clk_g2d_busp",
+	     CLK_CON_GAT_GOUT_G2D_SYSREG_PCLK, 21, 0, 0),
+	GATE(CLK_GOUT_G2D_XIU_D_MSCL_ACLK, "gout_g2d_xiu_d_mscl_aclk", "mout_pll_g2d_g2d_user",
+	     CLK_CON_GAT_GOUT_G2D_XIU_D_MSCL_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info g2d_cmu_info __initconst = {
+	.mux_clks		= g2d_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(g2d_mux_clks),
+	.div_clks		= g2d_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(g2d_div_clks),
+	.gate_clks		= g2d_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(g2d_gate_clks),
+	.clk_regs		= g2d_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(g2d_clk_regs),
+	.nr_clk_ids		= CLKS_NR_G2D,
+};
+
+/* CMU_G3D */
+#define PLL_LOCKTIME_PLL_G3D			0x0000
+#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER	0x0100
+#define PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER	0x0108
+#define PLL_CON0_PLL_G3D			0x0120
+#define CLK_CON_MUX_MUX_CLK_G3D_BUSD		0x1004
+#define CLK_CON_DIV_DIV_CLK_G3D_BUSD		0x1800
+#define CLK_CON_DIV_DIV_CLK_G3D_BUSP		0x1804
+#define CLK_CON_GAT_CLK_G3D_CMU_PCLK		0x2000
+#define CLK_CON_GAT_CLK_G3D_G3D_CLK		0x2004
+#define CLK_CON_GAT_CLK_G3D_HPM_TARGETCLK_C	0x2008
+#define CLK_CON_GAT_CLK_G3D_OSCCLK_CLK		0x200c
+#define CLK_CON_GAT_GOUT_G3D_BTM_G3D_ACLK	0x2014
+#define CLK_CON_GAT_GOUT_G3D_BTM_G3D_PCLK	0x2018
+#define CLK_CON_GAT_GOUT_G3D_BUSIF_HPMG3D_PCLK	0x201c
+#define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_G3D_CLK	0x2020
+#define CLK_CON_GAT_GOUT_G3D_LHM_AXI_G3DSFR_CLK	0x2024
+#define CLK_CON_GAT_GOUT_G3D_LHM_AXI_P_G3D_CLK	0x2028
+#define CLK_CON_GAT_GOUT_G3D_LHS_AXI_D_G3D_CLK	0x202c
+#define CLK_CON_GAT_GOUT_G3D_LHS_AXI_G3DSFR_CLK	0x2030
+#define CLK_CON_GAT_GOUT_G3D_PGEN_LITE_G3D_CLK	0x2034
+#define CLK_CON_GAT_GOUT_G3D_BUSD_CLK		0x2038
+#define CLK_CON_GAT_GOUT_G3D_BUSP_CLK		0x203c
+#define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK	0x2040
+
+static const unsigned long g3d_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_G3D,
+	PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER,
+	PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER,
+	PLL_CON0_PLL_G3D,
+	CLK_CON_MUX_MUX_CLK_G3D_BUSD,
+	CLK_CON_DIV_DIV_CLK_G3D_BUSD,
+	CLK_CON_DIV_DIV_CLK_G3D_BUSP,
+	CLK_CON_GAT_CLK_G3D_CMU_PCLK,
+	CLK_CON_GAT_CLK_G3D_G3D_CLK,
+	CLK_CON_GAT_CLK_G3D_HPM_TARGETCLK_C,
+	CLK_CON_GAT_CLK_G3D_OSCCLK_CLK,
+	CLK_CON_GAT_GOUT_G3D_BTM_G3D_ACLK,
+	CLK_CON_GAT_GOUT_G3D_BTM_G3D_PCLK,
+	CLK_CON_GAT_GOUT_G3D_BUSIF_HPMG3D_PCLK,
+	CLK_CON_GAT_GOUT_G3D_GRAY2BIN_G3D_CLK,
+	CLK_CON_GAT_GOUT_G3D_LHM_AXI_G3DSFR_CLK,
+	CLK_CON_GAT_GOUT_G3D_LHM_AXI_P_G3D_CLK,
+	CLK_CON_GAT_GOUT_G3D_LHS_AXI_D_G3D_CLK,
+	CLK_CON_GAT_GOUT_G3D_LHS_AXI_G3DSFR_CLK,
+	CLK_CON_GAT_GOUT_G3D_PGEN_LITE_G3D_CLK,
+	CLK_CON_GAT_GOUT_G3D_BUSD_CLK,
+	CLK_CON_GAT_GOUT_G3D_BUSP_CLK,
+	CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK,
+};
+
+static const struct samsung_pll_rate_table pll_g3d_rate_table[] __initconst = {
+	PLL_35XX_RATE(26 * MHZ, 750000000, 375, 13, 0),
+	PLL_35XX_RATE(26 * MHZ, 1000000000, 500, 13, 0),
+	PLL_35XX_RATE(26 * MHZ, 1200000000, 600, 13, 0),
+	PLL_35XX_RATE(26 * MHZ, 330000000, 660, 13, 2),
+	PLL_35XX_RATE(26 * MHZ, 550000000, 550, 13, 1),
+};
+
+static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
+	PLL(pll_1052x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
+	    PLL_LOCKTIME_PLL_G3D, PLL_CON0_PLL_G3D,
+	    pll_g3d_rate_table),
+};
+
+PNAME(mout_g3d_switch_user_p)	= { "oscclk", "dout_cmu_g3d_switch" };
+PNAME(mout_clk_g3d_busd_p)	= { "fout_g3d_pll",
+				    "mout_g3d_switch_user" };
+
+static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user", mout_g3d_switch_user_p,
+	    PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1),
+	MUX(CLK_MOUT_CLK_G3D_BUSD, "mout_clk_g3d_busd", mout_clk_g3d_busd_p,
+	    CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1),
+};
+
+static const struct samsung_div_clock g3d_div_clks[] __initconst = {
+	DIV(CLK_DOUT_CLK_G3D_BUSD, "dout_clk_g3d_busd", "mout_clk_g3d_busd",
+	    CLK_CON_DIV_DIV_CLK_G3D_BUSD, 0, 1),
+	DIV(CLK_DOUT_CLK_G3D_BUSP, "dout_clk_g3d_busp", "mout_clk_g3d_busd",
+	    CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3),
+};
+
+static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_CLK_G3D_CMU_PCLK, "gout_clk_g3d_cmu_pclk", "dout_clk_g3d_busp",
+	     CLK_CON_GAT_CLK_G3D_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_G3D_G3D_CLK, "gout_clk_g3d_g3d_clk", "dout_clk_g3d_busd",
+	     CLK_CON_GAT_CLK_G3D_G3D_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_G3D_HPM_TARGETCLK_C, "gout_clk_g3d_hpm_targetclk_c",
+	     "dout_cmu_hpm", CLK_CON_GAT_CLK_G3D_HPM_TARGETCLK_C, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_CLK_G3D_OSCCLK_CLK, "gout_clk_g3d_oscclk_clk", "oscclk",
+	     CLK_CON_GAT_CLK_G3D_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_BTM_G3D_ACLK, "gout_g3d_btm_g3d_aclk", "dout_clk_g3d_busd",
+	     CLK_CON_GAT_GOUT_G3D_BTM_G3D_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_BTM_G3D_PCLK, "gout_g3d_btm_g3d_pclk", "dout_clk_g3d_busp",
+	     CLK_CON_GAT_GOUT_G3D_BTM_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_BUSIF_HPMG3D_PCLK, "gout_g3d_busif_hpmg3d_pclk",
+	     "dout_clk_g3d_busp", CLK_CON_GAT_GOUT_G3D_BUSIF_HPMG3D_PCLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_GRAY2BIN_G3D_CLK, "gout_g3d_gray2bin_g3d_clk",
+	     "dout_clk_g3d_busd", CLK_CON_GAT_GOUT_G3D_GRAY2BIN_G3D_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_LHM_AXI_G3DSFR_CLK, "gout_g3d_lhm_axi_g3dsfr_clk",
+	     "dout_clk_g3d_busd", CLK_CON_GAT_GOUT_G3D_LHM_AXI_G3DSFR_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_LHM_AXI_P_G3D_CLK, "gout_g3d_lhm_axi_p_g3d_clk",
+	     "dout_clk_g3d_busp", CLK_CON_GAT_GOUT_G3D_LHM_AXI_P_G3D_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_LHS_AXI_D_G3D_CLK, "gout_g3d_lhs_axi_d_g3d_clk",
+	     "dout_clk_g3d_busd", CLK_CON_GAT_GOUT_G3D_LHS_AXI_D_G3D_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_LHS_AXI_G3DSFR_CLK, "gout_g3d_lhs_axi_g3dsfr_clk",
+	     "dout_clk_g3d_busp", CLK_CON_GAT_GOUT_G3D_LHS_AXI_G3DSFR_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_PGEN_LITE_G3D_CLK, "gout_g3d_pgen_lite_g3d_clk",
+	     "dout_clk_g3d_busp", CLK_CON_GAT_GOUT_G3D_PGEN_LITE_G3D_CLK,
+	     21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "dout_clk_g3d_busd",
+	     CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_clk_g3d_busp",
+	     CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, CLK_IGNORE_UNUSED, 0),
+	GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_clk_g3d_busp",
+	     CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0),
+};
+
+static const struct samsung_cmu_info g3d_cmu_info __initconst = {
+	.pll_clks		= g3d_pll_clks,
+	.nr_pll_clks		= ARRAY_SIZE(g3d_pll_clks),
+	.mux_clks		= g3d_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(g3d_mux_clks),
+	.div_clks		= g3d_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(g3d_div_clks),
+	.gate_clks		= g3d_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(g3d_gate_clks),
+	.clk_regs		= g3d_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(g3d_clk_regs),
+	.nr_clk_ids		= CLKS_NR_G3D,
+};
+
+static int __init exynos9610_cmu_probe(struct platform_device *pdev)
+{
+	const struct samsung_cmu_info *info;
+	struct device *dev = &pdev->dev;
+
+	info = of_device_get_match_data(dev);
+	exynos_arm64_register_cmu(dev, dev->of_node, info);
+
+	return 0;
+}
+
+static const struct of_device_id exynos9610_cmu_of_match[] = {
+	{
+		.compatible = "samsung,exynos9610-cmu-cam",
+		.data = &cam_cmu_info,
+	},
+	{
+		.compatible = "samsung,exynos9610-cmu-cmgp",
+		.data = &cmgp_cmu_info,
+	},
+	{
+		.compatible = "samsung,exynos9610-cmu-core",
+		.data = &core_cmu_info,
+	},
+	{
+		.compatible = "samsung,exynos9610-cmu-dispaud",
+		.data = &dispaud_cmu_info,
+	},
+	{
+		.compatible = "samsung,exynos9610-cmu-fsys",
+		.data = &fsys_cmu_info,
+	},
+	{
+		.compatible = "samsung,exynos9610-cmu-g2d",
+		.data = &g2d_cmu_info,
+	},
+	{
+		.compatible = "samsung,exynos9610-cmu-g3d",
+		.data = &g3d_cmu_info,
+	},
+	{ }
+};
+
+static struct platform_driver exynos9610_cmu_driver __refdata = {
+	.driver = {
+		.name = "exynos9610-cmu",
+		.of_match_table = exynos9610_cmu_of_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = exynos9610_cmu_probe,
+};
+
+static int __init exynos9610_cmu_init(void)
+{
+	return platform_driver_register(&exynos9610_cmu_driver);
+}
+core_initcall(exynos9610_cmu_init);

-- 
2.47.3

[PATCH 4/8] arm64: dts: exynos9610: Enable clock support

[Alexandru Chimac]

Add CMU (Clock Management Unit) nodes and required
fixed clocks.

Signed-off-by: Alexandru Chimac <alex@chimac.ro>
---
 arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts |   1 +
 arch/arm64/boot/dts/exynos/exynos9610.dtsi       | 205 +++++++++++++++++++++++
 2 files changed, 206 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts b/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts
index f455af22ff872c6f07b9bcfc68b1ae1f45d0def3..1a09d5e8ebaa130e9cd0b7f3266ee2c9dac4cf9a 100644
--- a/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts
+++ b/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts
@@ -10,6 +10,7 @@
 #include "exynos9610.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/samsung,exynos9610.h>
 
 / {
 	compatible = "samsung,gta4xl", "samsung,exynos9610";
diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
index 852f7111e5cdfd82b5afc350792e8b539fe87d39..2a15986c459d6af9f83362c27cdcc3a2646c256b 100644
--- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/samsung,exynos9610.h>
 
 / {
 	compatible = "samsung,exynos9610";
@@ -161,6 +162,41 @@ oscclk: clock-osc {
 		clock-frequency = <26000000>;
 	};
 
+	dll_dco: clock-dll-dco {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-output-names = "dll_dco";
+		clock-frequency = <360000000>;
+	};
+
+	oscclk_rco_cmgp: clock-osc-rco {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-output-names = "oscclk_rco";
+		clock-frequency = <30000000>;
+	};
+
+	ioclk_audiocdclk0: clock-audiocdclk0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-output-names = "ioclk_audiocdclk0";
+		clock-frequency = <10000000>;
+	};
+
+	ioclk_audiocdclk1: clock-audiocdclk1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-output-names = "ioclk_audiocdclk1";
+		clock-frequency = <100000000>;
+	};
+
+	tick_usb: clock-tick-usb {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-output-names = "tick_usb";
+		clock-frequency = <60000000>;
+	};
+
 	soc: soc@0 {
 		compatible = "simple-bus";
 		ranges = <0x0 0x0 0x0 0x20000000>;
@@ -174,12 +210,81 @@ chipid@10000000 {
 			reg = <0x10000000 0x100>;
 		};
 
+		cmu_peri: clock-controller@10030000 {
+			compatible = "samsung,exynos9610-cmu-peri";
+			reg = <0x10030000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_CMU_PERI_BUS>,
+				 <&cmu_top CLK_DOUT_CMU_PERI_IP>,
+				 <&cmu_top CLK_DOUT_CMU_PERI_UART>;
+			clock-names = "oscclk",
+				      "dout_cmu_peri_bus",
+				      "dout_cmu_peri_ip",
+				      "dout_cmu_peri_uart";
+		};
+
+		cmu_cpucl1: clock-controller@0x10800000 {
+			compatible = "samsung,exynos9610-cmu-cpucl1";
+			reg = <0x10800000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_CMU_CPUCL1_SWITCH>,
+				 <&cmu_top CLK_DOUT_CMU_HPM>;
+			clock-names = "oscclk",
+				      "dout_cmu_cpucl1_switch",
+				      "dout_cmu_hpm";
+		};
+
+		cmu_cpucl0: clock-controller@0x10900000 {
+			compatible = "samsung,exynos9610-cmu-cpucl0";
+			reg = <0x10900000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_CMU_CPUCL0_DBG>,
+				 <&cmu_top CLK_DOUT_CMU_CPUCL0_SWITCH>,
+				 <&cmu_top CLK_DOUT_CMU_HPM>;
+			clock-names = "oscclk",
+				      "dout_cmu_cpucl0_dbg",
+				      "dout_cmu_cpucl0_switch",
+				      "dout_cmu_hpm";
+		};
+
 		pinctrl_shub: pinctrl@11080000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x11080000 0x1000>;
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		cmu_g3d: clock-controller@11430000 {
+			compatible = "samsung,exynos9610-cmu-g3d";
+			reg = <0x11430000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_CMU_G3D_SWITCH>,
+				 <&cmu_top CLK_DOUT_CMU_HPM>;
+			clock-names = "oscclk",
+				      "dout_cmu_g3d_switch",
+				      "dout_cmu_hpm";
+		};
+
+		cmu_apm: clock-controller@11800000 {
+			compatible = "samsung,exynos9610-cmu-apm";
+			reg = <0x11800000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&dll_dco>,
+				 <&cmu_top CLK_DOUT_CMU_APM_BUS>;
+			clock-names = "oscclk",
+				      "dll_dco",
+				      "dout_cmu_apm_bus";
+		};
+
 		pinctrl_alive: pinctrl@11850000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x11850000 0x1000>;
@@ -191,11 +296,48 @@ wakeup-interrupt-controller {
 			};
 		};
 
+		cmu_cmgp: clock-controller@11c00000 {
+			compatible = "samsung,exynos9610-cmu-cmgp";
+			reg = <0x11c00000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&oscclk_rco_cmgp>,
+				 <&cmu_apm CLK_GOUT_CMU_CMGP_BUS>;
+			clock-names = "oscclk",
+				      "oscclk_rco",
+				      "gout_cmu_cmgp_bus";
+		};
+
 		pinctrl_cmgp: pinctrl@11c20000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x11c20000 0x1000>;
 		};
 
+		cmu_core: clock-controller@120f0000 {
+			compatible = "samsung,exynos9610-cmu-core";
+			reg = <0x120f0000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_CMU_CORE_BUS>,
+				 <&cmu_top CLK_DOUT_CMU_CORE_CCI>,
+				 <&cmu_top CLK_DOUT_CMU_CORE_G3D>;
+			clock-names = "oscclk",
+				      "dout_cmu_core_bus",
+				      "dout_cmu_core_cci",
+				      "dout_cmu_core_g3d";
+		};
+
+		cmu_top: clock-controller@12100000 {
+			compatible = "samsung,exynos9610-cmu-top";
+			reg = <0x12100000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>;
+			clock-names = "oscclk";
+		};
+
 		gic: interrupt-controller@12300000 {
 			compatible = "arm,gic-400";
 			#interrupt-cells = <3>;
@@ -209,6 +351,37 @@ gic: interrupt-controller@12300000 {
 						 IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
+		cmu_g2d: clock-controller@12e00000 {
+			compatible = "samsung,exynos9610-cmu-g2d";
+			reg = <0x12e00000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_CMU_G2D_G2D>,
+				 <&cmu_top CLK_DOUT_CMU_G2D_MSCL>;
+
+			clock-names = "oscclk",
+				      "dout_cmu_g2d_g2d",
+				      "dout_cmu_g2d_mscl";
+		};
+
+		cmu_fsys: clock-controller@13400000 {
+			compatible = "samsung,exynos9610-cmu-fsys";
+			reg = <0x13400000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_CMU_FSYS_BUS>,
+				 <&cmu_top CLK_DOUT_CMU_FSYS_MMC_CARD>,
+				 <&cmu_top CLK_DOUT_CMU_FSYS_MMC_EMBD>,
+				 <&cmu_top CLK_DOUT_CMU_FSYS_UFS_EMBD>;
+			clock-names = "oscclk",
+				      "dout_cmu_fsys_bus",
+				      "dout_cmu_fsys_mmc_card",
+				      "dout_cmu_fsys_mmc_embd",
+				      "dout_cmu_fsys_ufs_embd";
+		};
+
 		pinctrl_fsys: pinctrl@13490000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x13490000 0x1000>;
@@ -221,6 +394,38 @@ pinctrl_top: pinctrl@139b0000 {
 			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		cmu_cam: clock-controller@14500000 {
+			compatible = "samsung,exynos9610-cmu-cam";
+			reg = <0x14500000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_CMU_CAM_BUS>;
+			clock-names = "oscclk",
+				      "dout_cmu_cam_bus";
+		};
+
+		cmu_dispaud: clock-controller@14980000 {
+			compatible = "samsung,exynos9610-cmu-dispaud";
+			reg = <0x14980000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&ioclk_audiocdclk0>,
+				 <&ioclk_audiocdclk1>,
+				 <&tick_usb>,
+				 <&cmu_top CLK_DOUT_CMU_DISPAUD_AUD>,
+				 <&cmu_top CLK_DOUT_CMU_DISPAUD_CPU>,
+				 <&cmu_top CLK_DOUT_CMU_DISPAUD_DISP>;
+			clock-names = "oscclk",
+				      "ioclk_audiocdclk0",
+				      "ioclk_audiocdclk1",
+				      "tick_usb",
+				      "dout_cmu_dispaud_aud",
+				      "dout_cmu_dispaud_cpu",
+				      "dout_cmu_dispaud_disp";
+		};
+
 		pinctrl_dispaud: pinctrl@14a60000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x14a60000 0x1000>;

-- 
2.47.3

Re: [PATCH 4/8] arm64: dts: exynos9610: Enable clock support

[Krzysztof Kozlowski]

On 14/09/2025 23:19, Alexandru Chimac wrote:
> Add CMU (Clock Management Unit) nodes and required
> fixed clocks.
> 
> Signed-off-by: Alexandru Chimac <alex@chimac.ro>
> ---
>  arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts |   1 +
>  arch/arm64/boot/dts/exynos/exynos9610.dtsi       | 205 +++++++++++++++++++++++


There is no such file, which means you did not explain the dependencies
and this should not be separate patch at all. You must squash it.


Best regards,
Krzysztof

[PATCH 5/8] dt-bindings: soc: exynos-sysreg: Add Exynos9610 SYSREG bindings

[Alexandru Chimac]

Add bindings for SYSREG nodes, compatible with the standard syscon
driver.

Signed-off-by: Alexandru Chimac <alex@chimac.ro>
---
 .../bindings/soc/samsung/samsung,exynos-sysreg.yaml  | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
index d8b302f975474a87e4886006cf0b21cf758e4479..9f759e457a0acc2870adfd077d33870593cf7b83 100644
--- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -30,6 +30,16 @@ properties:
               - samsung,exynos8895-fsys1-sysreg
               - samsung,exynos8895-peric0-sysreg
               - samsung,exynos8895-peric1-sysreg
+              - samsung,exynos9610-apm-sysreg
+              - samsung,exynos9610-cam-sysreg
+              - samsung,exynos9610-core-sysreg
+              - samsung,exynos9610-cpucl0-sysreg
+              - samsung,exynos9610-cpucl1-sysreg
+              - samsung,exynos9610-dispaud-sysreg
+              - samsung,exynos9610-fsys-sysreg
+              - samsung,exynos9610-g2d-sysreg
+              - samsung,exynos9610-g3d-sysreg
+              - samsung,exynos9610-peri-sysreg
               - samsung,exynosautov920-hsi2-sysreg
               - samsung,exynosautov920-peric0-sysreg
               - samsung,exynosautov920-peric1-sysreg
@@ -93,6 +103,16 @@ allOf:
               - samsung,exynos8895-fsys1-sysreg
               - samsung,exynos8895-peric0-sysreg
               - samsung,exynos8895-peric1-sysreg
+              - samsung,exynos9610-apm-sysreg
+              - samsung,exynos9610-cam-sysreg
+              - samsung,exynos9610-core-sysreg
+              - samsung,exynos9610-cpucl0-sysreg
+              - samsung,exynos9610-cpucl1-sysreg
+              - samsung,exynos9610-dispaud-sysreg
+              - samsung,exynos9610-fsys-sysreg
+              - samsung,exynos9610-g2d-sysreg
+              - samsung,exynos9610-g3d-sysreg
+              - samsung,exynos9610-peri-sysreg
     then:
       required:
         - clocks

-- 
2.47.3

Re: [PATCH 5/8] dt-bindings: soc: exynos-sysreg: Add Exynos9610 SYSREG bindings

[Rob Herring (Arm)]

On Sun, 14 Sep 2025 21:20:09 +0000, Alexandru Chimac wrote:
> Add bindings for SYSREG nodes, compatible with the standard syscon
> driver.
> 
> Signed-off-by: Alexandru Chimac <alex@chimac.ro>
> ---
>  .../bindings/soc/samsung/samsung,exynos-sysreg.yaml  | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH 6/8] arm64: dts: exynos9610: Add SYSREG nodes

[Alexandru Chimac]

Add nodes for:
- apm-sysreg
- cam-sysreg
- core-sysreg
- cpucl0/1-sysreg
- dispaud-sysreg
- fsys-sysreg
- g2d/g3d-sysreg
- peri-sysreg

Signed-off-by: Alexandru Chimac <alex@chimac.ro>
---
 arch/arm64/boot/dts/exynos/exynos9610.dtsi | 60 ++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
index 2a15986c459d6af9f83362c27cdcc3a2646c256b..8ac113ceddacc30b52fa35954c85e1b8c320057d 100644
--- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
@@ -210,6 +210,12 @@ chipid@10000000 {
 			reg = <0x10000000 0x100>;
 		};
 
+		sysreg_peri: system-controller@10010000 {
+			compatible = "samsung,exynos9610-peri-sysreg", "syscon";
+			reg = <0x10010000 0x10000>;
+			clocks = <&cmu_peri CLK_GOUT_PERI_SYSREG_PCLK>;
+		};
+
 		cmu_peri: clock-controller@10030000 {
 			compatible = "samsung,exynos9610-cmu-peri";
 			reg = <0x10030000 0x8000>;
@@ -238,6 +244,12 @@ cmu_cpucl1: clock-controller@0x10800000 {
 				      "dout_cmu_hpm";
 		};
 
+		sysreg_cpucl1: system-controller@10810000 {
+			compatible = "samsung,exynos9610-cpucl1-sysreg", "syscon";
+			reg = <0x10810000 0x10000>;
+			clocks = <&cmu_cpucl1 CLK_GOUT_CPUCL1_SYSREG_PCLK>;
+		};
+
 		cmu_cpucl0: clock-controller@0x10900000 {
 			compatible = "samsung,exynos9610-cmu-cpucl0";
 			reg = <0x10900000 0x8000>;
@@ -253,12 +265,24 @@ cmu_cpucl0: clock-controller@0x10900000 {
 				      "dout_cmu_hpm";
 		};
 
+		sysreg_cpucl0: system-controller@10910000 {
+			compatible = "samsung,exynos9610-cpucl0-sysreg", "syscon";
+			reg = <0x10910000 0x10000>;
+			clocks = <&cmu_cpucl0 CLK_GOUT_CPUCL0_SYSREG_PCLK>;
+		};
+
 		pinctrl_shub: pinctrl@11080000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x11080000 0x1000>;
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		sysreg_g3d: system-controller@11410000 {
+			compatible = "samsung,exynos9610-g3d-sysreg", "syscon";
+			reg = <0x11410000 0x10000>;
+			clocks = <&cmu_g3d CLK_GOUT_G3D_SYSREG_PCLK>;
+		};
+
 		cmu_g3d: clock-controller@11430000 {
 			compatible = "samsung,exynos9610-cmu-g3d";
 			reg = <0x11430000 0x8000>;
@@ -285,6 +309,12 @@ cmu_apm: clock-controller@11800000 {
 				      "dout_cmu_apm_bus";
 		};
 
+		sysreg_apm: system-controller@11810000 {
+			compatible = "samsung,exynos9610-apm-sysreg", "syscon";
+			reg = <0x11810000 0x10000>;
+			clocks = <&cmu_apm CLK_GOUT_APM_SYSREG_PCLK>;
+		};
+
 		pinctrl_alive: pinctrl@11850000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x11850000 0x1000>;
@@ -314,6 +344,12 @@ pinctrl_cmgp: pinctrl@11c20000 {
 			reg = <0x11c20000 0x1000>;
 		};
 
+		sysreg_core: system-controller@12010000 {
+			compatible = "samsung,exynos9610-core-sysreg", "syscon";
+			reg = <0x12010000 0x10000>;
+			clocks = <&cmu_core CLK_GOUT_CORE_SYSREG_PCLK>;
+		};
+
 		cmu_core: clock-controller@120f0000 {
 			compatible = "samsung,exynos9610-cmu-core";
 			reg = <0x120f0000 0x8000>;
@@ -365,6 +401,12 @@ cmu_g2d: clock-controller@12e00000 {
 				      "dout_cmu_g2d_mscl";
 		};
 
+		sysreg_g2d: system-controller@12e10000 {
+			compatible = "samsung,exynos9610-g2d-sysreg", "syscon";
+			reg = <0x12e10000 0x10000>;
+			clocks = <&cmu_g2d CLK_GOUT_G2D_SYSREG_PCLK>;
+		};
+
 		cmu_fsys: clock-controller@13400000 {
 			compatible = "samsung,exynos9610-cmu-fsys";
 			reg = <0x13400000 0x8000>;
@@ -382,6 +424,12 @@ cmu_fsys: clock-controller@13400000 {
 				      "dout_cmu_fsys_ufs_embd";
 		};
 
+		sysreg_fsys: system-controller@13410000 {
+			compatible = "samsung,exynos9610-fsys-sysreg", "syscon";
+			reg = <0x13410000 0x10000>;
+			clocks = <&cmu_fsys CLK_GOUT_FSYS_SYSREG_PCLK>;
+		};
+
 		pinctrl_fsys: pinctrl@13490000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x13490000 0x1000>;
@@ -405,6 +453,18 @@ cmu_cam: clock-controller@14500000 {
 				      "dout_cmu_cam_bus";
 		};
 
+		sysreg_cam: system-controller@14510000 {
+			compatible = "samsung,exynos9610-cam-sysreg", "syscon";
+			reg = <0x14510000 0x10000>;
+			clocks = <&cmu_cam CLK_GOUT_CAM_SYSREG_PCLK>;
+		};
+
+		sysreg_dispaud: system-controller@14810000 {
+			compatible = "samsung,exynos9610-dispaud-sysreg", "syscon";
+			reg = <0x14810000 0x10000>;
+			clocks = <&cmu_dispaud CLK_GOUT_DISPAUD_SYSREG_PCLK>;
+		};
+
 		cmu_dispaud: clock-controller@14980000 {
 			compatible = "samsung,exynos9610-cmu-dispaud";
 			reg = <0x14980000 0x8000>;

-- 
2.47.3

[PATCH 7/8] arm64: dts: exynos9610: Assign clocks to existing nodes

[Alexandru Chimac]

Required in order to have these parts work while the
clock driver is enabled (without clk_ignore_unused).

Signed-off-by: Alexandru Chimac <alex@chimac.ro>
---
 arch/arm64/boot/dts/exynos/exynos9610.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
index 8ac113ceddacc30b52fa35954c85e1b8c320057d..2dc7cdda83d9357cb2a44d58d666a75674c83ec4 100644
--- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
@@ -319,6 +319,9 @@ pinctrl_alive: pinctrl@11850000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x11850000 0x1000>;
 
+			clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>;
+			clock-names = "pclk";
+
 			wakeup-interrupt-controller {
 				compatible = "samsung,exynos9610-wakeup-eint",
 					     "samsung,exynos850-wakeup-eint",
@@ -342,6 +345,9 @@ cmu_cmgp: clock-controller@11c00000 {
 		pinctrl_cmgp: pinctrl@11c20000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x11c20000 0x1000>;
+
+			clocks = <&cmu_cmgp CLK_GOUT_CMGP_GPIO_PCLK>;
+			clock-names = "pclk";
 		};
 
 		sysreg_core: system-controller@12010000 {
@@ -385,6 +391,8 @@ gic: interrupt-controller@12300000 {
 			      <0x12306000 0x2000>;
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
 						 IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&cmu_core CLK_GOUT_CORE_GIC_CLK>;
+			clock-names = "clk";
 		};
 
 		cmu_g2d: clock-controller@12e00000 {
@@ -434,6 +442,8 @@ pinctrl_fsys: pinctrl@13490000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x13490000 0x1000>;
 			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_fsys CLK_GOUT_FSYS_GPIO_PCLK>;
+			clock-names = "pclk";
 		};
 
 		pinctrl_top: pinctrl@139b0000 {
@@ -489,6 +499,8 @@ cmu_dispaud: clock-controller@14980000 {
 		pinctrl_dispaud: pinctrl@14a60000 {
 			compatible = "samsung,exynos9610-pinctrl";
 			reg = <0x14a60000 0x1000>;
+			clocks = <&cmu_dispaud CLK_GOUT_DISPAUD_GPIO_DISPAUD_PCLK>;
+			clock-names = "pclk";
 		};
 	};
 

-- 
2.47.3

[PATCH 8/8] arm64: dts: exynos9610-gta4xl: Assign clocks to existing nodes

[Alexandru Chimac]

Temporarily assign DISPAUD_DISP gate to simplefb node,
until the Exynos DRM driver will support this SoC.

Signed-off-by: Alexandru Chimac <alex@chimac.ro>
---
 arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts b/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts
index 1a09d5e8ebaa130e9cd0b7f3266ee2c9dac4cf9a..e08a3603c27396c96dc2e9d5186be504ff7ce3aa 100644
--- a/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts
+++ b/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts
@@ -29,6 +29,7 @@ framebuffer0: framebuffer@ca000000 {
 			height = <2000>;
 			stride = <(1200 * 4)>;
 			format = "a8r8g8b8";
+			clocks = <&cmu_dispaud CLK_GOUT_DISPAUD_CLK_DISPAUD_DISP>;
 		};
 	};
 

-- 
2.47.3