From: Qiang Yu <quic_qianyu@quicinc.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: <vkoul@kernel.org>, <kishon@kernel.org>, <robh@kernel.org>,
<andersson@kernel.org>, <konradybcio@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<mturquette@baylibre.com>, <sboyd@kernel.org>,
<abel.vesa@linaro.org>, <quic_msarkar@quicinc.com>,
<quic_devipriy@quicinc.com>, <dmitry.baryshkov@linaro.org>,
<kw@linux.com>, <lpieralisi@kernel.org>,
<neil.armstrong@linaro.org>, <linux-arm-msm@vger.kernel.org>,
<linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-clk@vger.kernel.org>
Subject: Re: [PATCH v6 3/8] dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt
Date: Mon, 14 Oct 2024 15:50:53 +0800 [thread overview]
Message-ID: <96816abb-4e0d-4c60-8ae6-b5a5cd796e99@quicinc.com> (raw)
In-Reply-To: <df6379c6-662a-4b35-a919-13c695a869c7@kernel.org>
On 10/12/2024 12:06 AM, Krzysztof Kozlowski wrote:
> On 11/10/2024 17:51, Manivannan Sadhasivam wrote:
>>
>> On October 11, 2024 9:14:31 PM GMT+05:30, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>> On 11/10/2024 17:42, Manivannan Sadhasivam wrote:
>>>>
>>>> On October 11, 2024 8:03:58 PM GMT+05:30, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>>> On Fri, Oct 11, 2024 at 03:41:37AM -0700, Qiang Yu wrote:
>>>>>> Document 'global' SPI interrupt along with the existing MSI interrupts so
>>>>>> that QCOM PCIe RC driver can make use of it to get events such as PCIe
>>>>>> link specific events, safety events, etc.
>>>>> Describe the hardware, not what the driver will do.
>>>>>
>>>>>> Though adding a new interrupt will break the ABI, it is required to
>>>>>> accurately describe the hardware.
>>>>> That's poor reason. Hardware was described and missing optional piece
>>>>> (because according to your description above everything was working
>>>>> fine) is not needed to break ABI.
>>>>>
>>>> Hardware was described but not completely. 'global' IRQ let's the controller driver to handle PCIe link specific events like Link up, Link down etc... They improve user experience like the driver can use those interrupts to start bus enumeration on its own. So breaking the ABI for good in this case.
>>>>
>>>>> Sorry, if your driver changes the ABI for this poor reason.
>>>>>
>>>> Is the above reasoning sufficient?
>>> I tried to look for corresponding driver change, but could not, so maybe
>>> there is no ABI break in the first place.
>> Here it is:
>>
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4581403f67929d02c197cb187c4e1e811c9e762a
>>
>> Above explanation is good, but
>>> still feels like improvement and device could work without global clock.
> So there is no ABI break in the first place... Commit is misleading.
OK, will remove the description about ABI break in commit message. But may
I know in which case ABI will be broken by adding an interrupt in bingdings
and what ABI will be broken?
>
>> It is certainly an improvement but provides a nice user experience as the devices will be enumerated when they get plugged into the slot (like hotplug). Otherwise, users have to rescan the bus every time they plug a device. Also when the device gets removed, driver could retrain the link if link went to a bad state. Otherwise, link will remain in the broken state requiring users to unload/load the driver again.
> OK
Thanks Mani for your detailed explaination. Can I reword commit message
like this:
Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt
to the host CPU. This interrupt can be used by the device driver to handle
PCIe link specific events such as Link up and Link down, which give the
driver a chance to start bus enumeration on its own when link is up and
initiate link training if link went to a bad state. This provides a nice
user experience.
Hence, document it in the binding along with the existing MSI interrupts.
Thanks,
Qiang
>
> Best regards,
> Krzysztof
>
next prev parent reply other threads:[~2024-10-14 7:51 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-11 10:41 [PATCH v6 0/8] Add support for PCIe3 on x1e80100 Qiang Yu
2024-10-11 10:41 ` [PATCH v6 1/8] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 Qiang Yu
2024-10-12 4:14 ` Manivannan Sadhasivam
2024-10-11 10:41 ` [PATCH v6 2/8] dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml Qiang Yu
2024-10-11 10:41 ` [PATCH v6 3/8] dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt Qiang Yu
2024-10-11 14:33 ` Krzysztof Kozlowski
2024-10-11 14:36 ` Krzysztof Kozlowski
2024-10-11 15:42 ` Manivannan Sadhasivam
2024-10-11 15:44 ` Krzysztof Kozlowski
2024-10-11 15:51 ` Manivannan Sadhasivam
2024-10-11 16:06 ` Krzysztof Kozlowski
2024-10-14 7:50 ` Qiang Yu [this message]
2024-10-14 8:25 ` Krzysztof Kozlowski
2024-10-14 13:09 ` Qiang Yu
2024-10-14 9:02 ` Manivannan Sadhasivam
2024-10-14 9:26 ` Krzysztof Kozlowski
2024-10-14 9:41 ` Manivannan Sadhasivam
2024-10-14 13:09 ` Qiang Yu
2024-10-11 10:41 ` [PATCH v6 4/8] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 Qiang Yu
2024-10-11 10:41 ` [PATCH v6 5/8] clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks Qiang Yu
2024-10-11 10:41 ` [PATCH v6 6/8] PCI: qcom: Fix the ops for SC8280X family SoC Qiang Yu
2024-10-11 13:36 ` Dmitry Baryshkov
2024-10-12 4:23 ` Manivannan Sadhasivam
2024-10-14 17:18 ` Bjorn Helgaas
2024-10-15 2:46 ` Qiang Yu
2024-10-11 10:41 ` [PATCH v6 7/8] PCI: qcom: Fix the cfg for X1E80100 SoC Qiang Yu
2024-10-11 13:37 ` Dmitry Baryshkov
2024-10-12 5:36 ` Manivannan Sadhasivam
2024-10-14 17:20 ` Bjorn Helgaas
2024-10-11 10:41 ` [PATCH v6 8/8] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Qiang Yu
2024-10-16 20:42 ` (subset) [PATCH v6 0/8] " Bjorn Andersson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=96816abb-4e0d-4c60-8ae6-b5a5cd796e99@quicinc.com \
--to=quic_qianyu@quicinc.com \
--cc=abel.vesa@linaro.org \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=kishon@kernel.org \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=krzk@kernel.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=mturquette@baylibre.com \
--cc=neil.armstrong@linaro.org \
--cc=quic_devipriy@quicinc.com \
--cc=quic_msarkar@quicinc.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox