* Re: [PATCH] clk: imx: imx8mq: fix sys2/3_pll_out_sels
From: Shawn Guo @ 2019-10-28 8:53 UTC (permalink / raw)
To: Peng Fan
Cc: mturquette@baylibre.com, sboyd@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, Abel Vesa, kernel@pengutronix.de,
dl-linux-imx, Anson Huang, Jacky Bai, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Leonard Crestez
In-Reply-To: <1571900044-22079-1-git-send-email-peng.fan@nxp.com>
@Abel, comments?
Shawn
On Thu, Oct 24, 2019 at 06:57:21AM +0000, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> The current clk tree shows:
> osc_25m 9 11 0 25000000 0 0 50000
> sys2_pll1_ref_sel 1 1 0 25000000 0 0 50000
> sys3_pll_out 1 1 0 25000000 0 0 50000
> sys1_pll1_ref_sel 2 2 0 25000000 0 0 50000
> sys2_pll_out 6 6 0 1000000000 0 0 50000
>
> It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent,
> sys2_pll_out use sys1_pll1_ref_sel as parent.
>
> According to the current imx_clk_sccg_pll design, it uses both
> bypass1/2, however set bypass2 as 1 is not correct, because it will
> make sys[x]_pll_out use wrong parent and might access wrong registers.
>
> So correct bypass2 to 0 and fix sys2/3_pll_out_sels.
>
> After fix, the tree shows:
> osc_25m 10 12 0 25000000 0 0 50000
> sys3_pll1_ref_sel 1 1 0 25000000 0 0 50000
> sys3_pll_out 1 1 0 25000000 0 0 50000
> sys2_pll1_ref_sel 1 1 0 25000000 0 0 50000
> sys2_pll_out 6 6 0 1000000000 0 0 50000
> sys1_pll1_ref_sel 1 1 0 25000000 0 0 50000
> sys1_pll_out 5 5 0 800000000 0 0 50000
>
> Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk")
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/clk/imx/clk-imx8mq.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index 05ece7b5da54..e17f0ebfacb0 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -35,8 +35,8 @@ static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_
> static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
>
> static const char * const sys1_pll_out_sels[] = {"sys1_pll1_ref_sel", };
> -static const char * const sys2_pll_out_sels[] = {"sys1_pll1_ref_sel", "sys2_pll1_ref_sel", };
> -static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", "sys2_pll1_ref_sel", };
> +static const char * const sys2_pll_out_sels[] = {"sys2_pll1_ref_sel", };
> +static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", };
> static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", };
> static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", };
>
> @@ -345,8 +345,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
> clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21);
>
> clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, CLK_IS_CRITICAL);
> - clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, CLK_IS_CRITICAL);
> - clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL);
> + clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 0, base + 0x3c, CLK_IS_CRITICAL);
> + clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + 0x48, CLK_IS_CRITICAL);
> clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL);
> clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_sccg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);
>
> --
> 2.16.4
>
^ permalink raw reply
* Re: [PATCH V2 0/3] clk: imx: imx6x: use imx_obtain_fixed_clk_hw
From: Shawn Guo @ 2019-10-28 8:47 UTC (permalink / raw)
To: Peng Fan
Cc: mturquette@baylibre.com, sboyd@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, kernel@pengutronix.de, dl-linux-imx,
Anson Huang, Jacky Bai, Abel Vesa, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Leonard Crestez
In-Reply-To: <1571885777-21662-1-git-send-email-peng.fan@nxp.com>
On Thu, Oct 24, 2019 at 02:59:27AM +0000, Peng Fan wrote:
> Peng Fan (3):
> clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify code
> clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify code
> clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify code
Applied all, thanks.
^ permalink raw reply
* Re: [PATCH] clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify code
From: Shawn Guo @ 2019-10-28 8:47 UTC (permalink / raw)
To: Peng Fan
Cc: mturquette@baylibre.com, sboyd@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, kernel@pengutronix.de, dl-linux-imx,
Anson Huang, Jacky Bai, Abel Vesa, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Leonard Crestez
In-Reply-To: <1571884513-19892-1-git-send-email-peng.fan@nxp.com>
On Thu, Oct 24, 2019 at 02:38:22AM +0000, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> imx_obtain_fixed_clk_hw could be used to simplify code to replace
> __clk_get_hw(of_clk_get_by_name(node, "name"))
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH] clk: imx8m: Use SYS_PLL1_800M as intermediate parent of CLK_ARM
From: Shawn Guo @ 2019-10-28 8:35 UTC (permalink / raw)
To: Leonard Crestez, Stephen Boyd
Cc: Michael Turquette, Dong Aisheng, Fabio Estevam, Jacky Bai,
Anson Huang, Abel Vesa, linux-clk, kernel, linux-imx,
linux-arm-kernel
In-Reply-To: <f5d2b9c53f1ed5ccb1dd3c6624f56759d92e1689.1571771777.git.leonard.crestez@nxp.com>
On Tue, Oct 22, 2019 at 10:21:28PM +0300, Leonard Crestez wrote:
> During cpu frequency switching the main "CLK_ARM" is reparented to an
> intermediate "step" clock. On imx8mm and imx8mn the 24M oscillator is
> used for this purpose but it is extremely slow, increasing wakeup
> latencies to the point that i2c transactions can timeout and system
> becomes unresponsive.
>
> Fix by switching the "step" clk to SYS_PLL1_800M, matching the behavior
> of imx8m cpufreq drivers in imx vendor tree.
>
> This bug was not immediately apparent because upstream arm64 defconfig
> uses the "performance" governor by default so no cpufreq transitions
> happen.
>
> Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
> Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Stephen,
I assume that you will pick up this one as a fix.
Shawn
^ permalink raw reply
* [PATCH v4] clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock
From: Fancy Fang @ 2019-10-28 8:07 UTC (permalink / raw)
To: shawnguo@kernel.org
Cc: sboyd@kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, mturquette@baylibre.com,
s.hauer@pengutronix.de, kernel@pengutronix.de, dl-linux-imx
The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.
MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transferring the pixel data out and its
output clock is configured according to the display mode.
So it should be used only for MIPI DSI and not be exported
out for other usages.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
---
ChangeLog v3->v4:
* Add some comments to 'IMX7ULP_CLK_MIPI_PLL'
clock.
Documentation/devicetree/bindings/clock/imx7ulp-clock.txt | 1 -
drivers/clk/imx/clk-imx7ulp.c | 3 +--
include/dt-bindings/clock/imx7ulp-clock.h | 6 ++++++
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
index a4f8cd478f92..93d89adb7afe 100644
--- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
@@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 {
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
- <&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 2022d9bead91..459b120b71d5 100644
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -28,7 +28,7 @@ static const char * const scs_sels[] = { "dummy", "sosc", "sirc", "firc", "dumm
static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
static const char * const nic_sels[] = { "firc", "ddr_clk", };
static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
-static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
+static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
static const char * const arm_sels[] = { "divcore", "dummy", "dummy", "hsrun_divcore", };
/* used by sosc/sirc/firc/ddr/spll/apll dividers */
@@ -75,7 +75,6 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
- clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
/* SCG1 */
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
index 6f66f9005c81..e9ef62f211fe 100644
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -49,7 +49,13 @@
#define IMX7ULP_CLK_NIC1_DIV 36
#define IMX7ULP_CLK_NIC1_BUS_DIV 37
#define IMX7ULP_CLK_NIC1_EXT_DIV 38
+
+/* mpll clock is a special clock comes from
+ * mipi DPHY PLL and should be used only for
+ * mipi dsi instead of any other peripheral.
+ */
#define IMX7ULP_CLK_MIPI_PLL 39
+
#define IMX7ULP_CLK_SIRC 40
#define IMX7ULP_CLK_SOSC_BUS_CLK 41
#define IMX7ULP_CLK_FIRC_BUS_CLK 42
--
2.17.1
^ permalink raw reply related
* Re: [PATCH] clk: qcom: gcc: Add missing clocks in SM8150
From: Vinod Koul @ 2019-10-28 7:23 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-arm-msm, Taniya Das, Bjorn Andersson, Andy Gross,
Michael Turquette, linux-clk, linux-kernel
In-Reply-To: <20191027212527.AE3D021783@mail.kernel.org>
On 27-10-19, 14:25, Stephen Boyd wrote:
> Quoting Vinod Koul (2019-10-21 03:54:35)
> > On 17-10-19, 10:48, Stephen Boyd wrote:
> > > > > > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> > > > > > index 12ca2d14797f..13d4d14a5744 100644
> > > > > > --- a/drivers/clk/qcom/gcc-sm8150.c
> > > > > > +++ b/drivers/clk/qcom/gcc-sm8150.c
> > > > > > @@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
> > > > > > },
> > > > > > };
> > > > > >
> > > > > > +static struct clk_branch gcc_gpu_gpll0_clk_src = {
> > > > > > + .halt_check = BRANCH_HALT_SKIP,
> > > > >
> > > > > Why skip?
> > > >
> > > > I will explore and add comments for that
> > > >
> > > > > > + .clkr = {
> > > > > > + .enable_reg = 0x52004,
> > > > > > + .enable_mask = BIT(15),
> > > > > > + .hw.init = &(struct clk_init_data){
> > > > > > + .name = "gcc_gpu_gpll0_clk_src",
> > > > > > + .parent_hws = (const struct clk_hw *[]){
> > > > > > + &gpll0.clkr.hw },
> > > > > > + .num_parents = 1,
> > > > > > + .flags = CLK_SET_RATE_PARENT,
> > > > > > + .ops = &clk_branch2_ops,
> > > > > > + },
> > > > > > + },
> > > > > > +};
> > > > > > +
> > > > > > +static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
> > > > > > + .halt_check = BRANCH_HALT_SKIP,
> > > > >
> > > > > Why skip?
> > > > >
> > >
> > > Any answer from the explorations?
> >
> > Yeah so asking around the answer I got is that these are external
> > clocks and we need cannot rely on CLK_OFF bit for these clocks
> >
>
> The parents are from some other clk controller? Not external to the
> chip, right? If so, I still don't get it. Please add some sort of
> comment here in the code.
Yeah I have added a comment and posted v2 few days back.
Thanks
--
~Vinod
^ permalink raw reply
* [PATCH v2 3/4] clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management
From: Yoshihiro Shimoda @ 2019-10-28 6:07 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, geert+renesas
Cc: linux-clk, devicetree, linux-renesas-soc, Yoshihiro Shimoda
In-Reply-To: <1572242850-9073-1-git-send-email-yoshihiro.shimoda.uh@renesas.com>
This hardware needs to enable clocks of both host and peripheral.
So, this patch adds multiple clocks management.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/clk/renesas/rcar-usb2-clock-sel.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/rcar-usb2-clock-sel.c b/drivers/clk/renesas/rcar-usb2-clock-sel.c
index b97f5f9..4096506 100644
--- a/drivers/clk/renesas/rcar-usb2-clock-sel.c
+++ b/drivers/clk/renesas/rcar-usb2-clock-sel.c
@@ -26,9 +26,16 @@
#define CLKSET0_PRIVATE BIT(0)
#define CLKSET0_EXTAL_ONLY (CLKSET0_INTCLK_EN | CLKSET0_PRIVATE)
+enum {
+ CLK_INDEX_EHCI_OHCI,
+ CLK_INDEX_HS_USB,
+ CLK_NUM
+};
+
struct usb2_clock_sel_priv {
void __iomem *base;
struct clk_hw hw;
+ struct clk_bulk_data clks[CLK_NUM];
bool extal;
bool xtal;
};
@@ -53,14 +60,25 @@ static void usb2_clock_sel_disable_extal_only(struct usb2_clock_sel_priv *priv)
static int usb2_clock_sel_enable(struct clk_hw *hw)
{
- usb2_clock_sel_enable_extal_only(to_priv(hw));
+ struct usb2_clock_sel_priv *priv = to_priv(hw);
+ int ret;
+
+ ret = clk_bulk_prepare_enable(CLK_NUM, priv->clks);
+ if (ret)
+ return ret;
+
+ usb2_clock_sel_enable_extal_only(priv);
return 0;
}
static void usb2_clock_sel_disable(struct clk_hw *hw)
{
- usb2_clock_sel_disable_extal_only(to_priv(hw));
+ struct usb2_clock_sel_priv *priv = to_priv(hw);
+
+ usb2_clock_sel_disable_extal_only(priv);
+
+ clk_bulk_disable_unprepare(CLK_NUM, priv->clks);
}
/*
@@ -128,6 +146,14 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
+ priv->clks[CLK_INDEX_EHCI_OHCI].clk = devm_clk_get(dev, "ehci_ohci");
+ if (IS_ERR(priv->clks[CLK_INDEX_EHCI_OHCI].clk))
+ return PTR_ERR(priv->clks[CLK_INDEX_EHCI_OHCI].clk);
+
+ priv->clks[CLK_INDEX_HS_USB].clk = devm_clk_get(dev, "hs-usb-if");
+ if (IS_ERR(priv->clks[CLK_INDEX_HS_USB].clk))
+ return PTR_ERR(priv->clks[CLK_INDEX_HS_USB].clk);
+
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
--
2.7.4
^ permalink raw reply related
* [PATCH v2 0/4] clk: renesas: rcar-usb2-clock-sel: Fix clks/resets handling
From: Yoshihiro Shimoda @ 2019-10-28 6:07 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, geert+renesas
Cc: linux-clk, devicetree, linux-renesas-soc, Yoshihiro Shimoda
This patch series is based on the latest renesas-drivers.git /
clk-renesas-for-v5.5 branch.
The hardware also needs multiple clocks/resets management like
renesas_usbhs driver [1], so this patch series fixes it.
[1]
3df0e24 usb: renesas_usbhs: Add multiple clocks management
f181dbb usb: renesas_usbhs: Add reset_control
Changes from v1:
- Add Reviewed-by into this series' patch 1/4.
- (new) Add resets and power-domains properties into the patch 2/4.
- Use clk_bulk_* APIs (except clk_bulk_get() because this driver has
4 clocks and used only 2 clocks).
- Add "select RESET_CONTROLLER" into Kconfig
- Use devm_reset_control_array_get() instead of optional API.
https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=192869
Yoshihiro Shimoda (4):
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s
properties
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains
and resets properties
clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management
clk: renesas: rcar-usb2-clock-sel: Add reset_control
.../bindings/clock/renesas,rcar-usb2-clock-sel.txt | 13 +++++--
drivers/clk/renesas/Kconfig | 1 +
drivers/clk/renesas/rcar-usb2-clock-sel.c | 43 +++++++++++++++++++++-
3 files changed, 52 insertions(+), 5 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v2 4/4] clk: renesas: rcar-usb2-clock-sel: Add reset_control
From: Yoshihiro Shimoda @ 2019-10-28 6:07 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, geert+renesas
Cc: linux-clk, devicetree, linux-renesas-soc, Yoshihiro Shimoda
In-Reply-To: <1572242850-9073-1-git-send-email-yoshihiro.shimoda.uh@renesas.com>
This hardware needs to deassert resets of both host and peripheral.
So, this patch adds reset control.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/clk/renesas/Kconfig | 1 +
drivers/clk/renesas/rcar-usb2-clock-sel.c | 15 ++++++++++++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index be03bb7..a76d05af 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -156,6 +156,7 @@ config CLK_RCAR_GEN3_CPG
config CLK_RCAR_USB2_CLOCK_SEL
bool "Renesas R-Car USB2 clock selector support"
depends on ARCH_RENESAS || COMPILE_TEST
+ select RESET_CONTROLLER
help
This is a driver for R-Car USB2 clock selector
diff --git a/drivers/clk/renesas/rcar-usb2-clock-sel.c b/drivers/clk/renesas/rcar-usb2-clock-sel.c
index 4096506..1cdcc8f 100644
--- a/drivers/clk/renesas/rcar-usb2-clock-sel.c
+++ b/drivers/clk/renesas/rcar-usb2-clock-sel.c
@@ -19,6 +19,7 @@
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#define USB20_CLKSET0 0x00
@@ -36,6 +37,7 @@ struct usb2_clock_sel_priv {
void __iomem *base;
struct clk_hw hw;
struct clk_bulk_data clks[CLK_NUM];
+ struct reset_control *rsts;
bool extal;
bool xtal;
};
@@ -63,10 +65,16 @@ static int usb2_clock_sel_enable(struct clk_hw *hw)
struct usb2_clock_sel_priv *priv = to_priv(hw);
int ret;
- ret = clk_bulk_prepare_enable(CLK_NUM, priv->clks);
+ ret = reset_control_deassert(priv->rsts);
if (ret)
return ret;
+ ret = clk_bulk_prepare_enable(CLK_NUM, priv->clks);
+ if (ret) {
+ reset_control_assert(priv->rsts);
+ return ret;
+ }
+
usb2_clock_sel_enable_extal_only(priv);
return 0;
@@ -79,6 +87,7 @@ static void usb2_clock_sel_disable(struct clk_hw *hw)
usb2_clock_sel_disable_extal_only(priv);
clk_bulk_disable_unprepare(CLK_NUM, priv->clks);
+ reset_control_assert(priv->rsts);
}
/*
@@ -154,6 +163,10 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
if (IS_ERR(priv->clks[CLK_INDEX_HS_USB].clk))
return PTR_ERR(priv->clks[CLK_INDEX_HS_USB].clk);
+ priv->rsts = devm_reset_control_array_get(dev, true, false);
+ if (IS_ERR(priv->rsts))
+ return PTR_ERR(priv->rsts);
+
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
--
2.7.4
^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties
From: Yoshihiro Shimoda @ 2019-10-28 6:07 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, geert+renesas
Cc: linux-clk, devicetree, linux-renesas-soc, Yoshihiro Shimoda
In-Reply-To: <1572242850-9073-1-git-send-email-yoshihiro.shimoda.uh@renesas.com>
Since the hardware requires to enable both USB 2.0 host and peripheral
functional clock, this patch fixes the documentation.
Fortunately, no one has this device node for now, so that we don't
need to think of backward compatibility.
Fixes: 311accb64570 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
index 83f6c6a..5c1903f 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
@@ -38,7 +38,8 @@ Required properties:
- reg: offset and length of the USB 2.0 clock selector register block.
- clocks: A list of phandles and specifier pairs.
- clock-names: Name of the clocks.
- - The functional clock must be "ehci_ohci"
+ - The functional clock of USB 2.0 host side must be "ehci_ohci"
+ - The functional clock of HS-USB side must be "hs-usb-if"
- The USB_EXTAL clock pin must be "usb_extal"
- The USB_XTAL clock pin must be "usb_xtal"
- #clock-cells: Must be 0
@@ -49,7 +50,8 @@ Example (R-Car H3):
compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
"renesas,rcar-gen3-usb2-clock-sel";
reg = <0 0xe6590630 0 0x02>;
- clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
- clock-names = "ehci_ohci", "usb_extal", "usb_xtal";
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
+ <&usb_extal>, <&usb_xtal>;
+ clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";
#clock-cells = <0>;
};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/4] dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties
From: Yoshihiro Shimoda @ 2019-10-28 6:07 UTC (permalink / raw)
To: mturquette, sboyd, robh+dt, mark.rutland, geert+renesas
Cc: linux-clk, devicetree, linux-renesas-soc, Yoshihiro Shimoda
In-Reply-To: <1572242850-9073-1-git-send-email-yoshihiro.shimoda.uh@renesas.com>
This patch adds missing required properties of power-domains and resets.
Fortunately, no one has this device node for now, so that we don't
need to think of backward compatibility.
Fixes: 311accb64570 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
.../devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
index 5c1903f..bad876f 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt
@@ -43,6 +43,9 @@ Required properties:
- The USB_EXTAL clock pin must be "usb_extal"
- The USB_XTAL clock pin must be "usb_xtal"
- #clock-cells: Must be 0
+- power-domains: A phandle and symbolic PM domain specifier.
+ See power/renesas,rcar-sysc.txt.
+- resets: A list of phandles and specifier pairs.
Example (R-Car H3):
@@ -54,4 +57,6 @@ Example (R-Car H3):
<&usb_extal>, <&usb_xtal>;
clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";
#clock-cells = <0>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>>;
+ resets = <&cpg 703>, <&cpg 704>;
};
--
2.7.4
^ permalink raw reply related
* [PATCH V2] clk: imx: imx8mq: fix sys3_pll_out_sels
From: Peng Fan @ 2019-10-28 3:08 UTC (permalink / raw)
To: mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com, Abel Vesa
Cc: kernel@pengutronix.de, dl-linux-imx, Anson Huang, Jacky Bai,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Leonard Crestez, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent.
According to the current imx_clk_sccg_pll design, it uses both
bypass1/2, however set bypass2 as 1 is not correct, because it will
make sys[x]_pll_out use wrong parent and might access wrong registers.
So correct bypass2 to 0 and fix sys3_pll_out_sels.
Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
V2:
Rebased on Shawn's clk/imx tree to avoid conflicts
drivers/clk/imx/clk-imx8mq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 4a5dbc4366a5..5f10a606d836 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -34,7 +34,7 @@ static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
-static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", "sys2_pll1_ref_sel", };
+static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", };
static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", };
static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", };
@@ -342,7 +342,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_fixed("sys1_pll_out", 800000000);
clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_fixed("sys2_pll_out", 1000000000);
- clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL);
+ clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + 0x48, CLK_IS_CRITICAL);
clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL);
clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_sccg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);
--
2.16.4
^ permalink raw reply related
* Re: [PATCH v4 1/2] clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver
From: Stephen Boyd @ 2019-10-27 21:36 UTC (permalink / raw)
To: Jeffrey Hugo
Cc: Michael Turquette, Andy Gross, Bjorn Andersson, Marc Gonzalez,
MSM, linux-clk, lkml
In-Reply-To: <CAOCk7Np_Wn9JZ8JQCiDg1w+xcTVW9fhvtCA-k5ysc2juHZuvUw@mail.gmail.com>
Quoting Jeffrey Hugo (2019-10-18 14:11:09)
> On Thu, Oct 17, 2019 at 5:16 PM Jeffrey Hugo <jeffrey.l.hugo@gmail.com> wrote:
> >
> > On Thu, Oct 17, 2019 at 3:50 PM Stephen Boyd <sboyd@kernel.org> wrote:
> > >
> > > Quoting Jeffrey Hugo (2019-10-01 18:16:40)
> > > > +static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
> > > > + F(180000000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > > + F(257000000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > > + F(342000000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > > + F(414000000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > > + F(515000000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > > + F(596000000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > > + F(670000000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > > + F(710000000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > > + { }
> > >
> > > I guess this one doesn't do PLL ping pong? Instead we just reprogram the
> > > PLL all the time? Can we have rcg2 clk ops that set the rate on the
> > > parent to be exactly twice as much as the incoming frequency? I thought
> > > we already had this support in the code. Indeed, it is part of
> > > _freq_tbl_determine_rate() in clk-rcg.c, but not yet implemented in the
> > > same function name in clk-rcg2.c! Can you implement it? That way we
> > > don't need this long frequency table, just this weird one where it looks
> > > like:
> > >
> > > { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 }
> > > { }
> > >
> > > And then some more logic in the rcg2 ops to allow this possibility for a
> > > frequency table when CLK_SET_RATE_PARENT is set.
> >
> > Does not do PLL ping pong. I'll look at extending the rcg2 ops like
> > you describe.
>
> Am I missing something? From what I can tell, what you describe is
> not implemented.
>
> The only in-tree example of a freq_tbl with only a src and a pre_div
> defined for rcg ops is for the tv_src clk in mmcc-msm8960 [1]
> However, that uses a variant of rcg ops, clk_rcg_bypass_ops, not clk_rcg_ops.
>
> clk_rcg_bypass_ops has its own determine_rate implementation which
> does not utilize _freq_tbl_determine_rate(), and can only do a 1:1
> input rate to output ratio (we want a 1:2).
>
> _freq_tbl_determine_rate() in either rcg_ops or rcg2_ops won't work,
> because they both use qcom_find_freq() which doesn't work when your
> table doesn't specify any frequencies (f->freq is 0).
Yes. You have to have some sort of frequency table to tell us what the
source and predivider to use.
> qcom_find_freq() won't iterate through the table, therefore f in
> qcom_find_freq() won't be pointing at the end of the table (the null
> entry), so when qcom_find_freq decrements f in the return, it actually
> goes off the beginning of the array in an array out of bounds
> violation.
Ouch!
>
> Please advise how you would like to proceed.
Please have a frequency table like
{ .src = SOME_PLL, .div = 4 }
>
> I can still extend rcg2_ops to do what you want, but it won't be based
> on what rcg_ops is doing.
Why isn't rcg_ops doing it? The idea is to copy whatever is happening
with this snippet in the _freq_tbl_determine_rate() in rcg.c to rcg2.c
clk_flags = clk_hw_get_flags(hw);
p = clk_hw_get_parent_by_index(hw, index);
if (clk_flags & CLK_SET_RATE_PARENT) {
rate = rate * f->pre_div;
We have checked for CLK_SET_RATE_PARENT from the beginning. Maybe it was
always broken! If the frequency table pointer can return us the pre div
and source then we can do math to ask the parent PLL for something.
>
> I can spin a rcg2_ops variant to do what you want, with a custom
> determine_rate, but it doesn't seem like I'll really be saving any
> lines of code. Whatever I eliminate by minimizing the gfx3d
> freq_table I will surely be putting into clk-rcg2.c
>
> Or, I can just drop this idea and keep the freq_tbl as it is. Seems
> like just a one off scenario.
Please make rcg2 clk ops "do the right thing" when the flag
CLK_SET_RATE_PARENT is set and the frequency table is just a
source/divider sort of thing. That way we don't have to have different
clk ops or even put anything in the frequency table besides the source
PLL we want to use and the predivider we want to configure.
^ permalink raw reply
* Re: [PATCH] clk: qcom: gcc: Add missing clocks in SM8150
From: Stephen Boyd @ 2019-10-27 21:25 UTC (permalink / raw)
To: Vinod Koul
Cc: linux-arm-msm, Taniya Das, Bjorn Andersson, Andy Gross,
Michael Turquette, linux-clk, linux-kernel
In-Reply-To: <20191021105435.GE2654@vkoul-mobl>
Quoting Vinod Koul (2019-10-21 03:54:35)
> On 17-10-19, 10:48, Stephen Boyd wrote:
> > > > > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> > > > > index 12ca2d14797f..13d4d14a5744 100644
> > > > > --- a/drivers/clk/qcom/gcc-sm8150.c
> > > > > +++ b/drivers/clk/qcom/gcc-sm8150.c
> > > > > @@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
> > > > > },
> > > > > };
> > > > >
> > > > > +static struct clk_branch gcc_gpu_gpll0_clk_src = {
> > > > > + .halt_check = BRANCH_HALT_SKIP,
> > > >
> > > > Why skip?
> > >
> > > I will explore and add comments for that
> > >
> > > > > + .clkr = {
> > > > > + .enable_reg = 0x52004,
> > > > > + .enable_mask = BIT(15),
> > > > > + .hw.init = &(struct clk_init_data){
> > > > > + .name = "gcc_gpu_gpll0_clk_src",
> > > > > + .parent_hws = (const struct clk_hw *[]){
> > > > > + &gpll0.clkr.hw },
> > > > > + .num_parents = 1,
> > > > > + .flags = CLK_SET_RATE_PARENT,
> > > > > + .ops = &clk_branch2_ops,
> > > > > + },
> > > > > + },
> > > > > +};
> > > > > +
> > > > > +static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
> > > > > + .halt_check = BRANCH_HALT_SKIP,
> > > >
> > > > Why skip?
> > > >
> >
> > Any answer from the explorations?
>
> Yeah so asking around the answer I got is that these are external
> clocks and we need cannot rely on CLK_OFF bit for these clocks
>
The parents are from some other clk controller? Not external to the
chip, right? If so, I still don't get it. Please add some sort of
comment here in the code.
^ permalink raw reply
* [PATCH 5.3 003/197] clk: ti: dra7: Fix mcasp8 clock bits
From: Greg Kroah-Hartman @ 2019-10-27 20:58 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, stable, linux-clk, Michael Turquette,
Stephen Boyd, Suman Anna, Tero Kristo, Tony Lindgren, Sasha Levin
In-Reply-To: <20191027203351.684916567@linuxfoundation.org>
From: Tony Lindgren <tony@atomide.com>
[ Upstream commit dd8882a255388ba66175098b1560d4f81c100d30 ]
There's a typo for dra7 mcasp clkctrl bit, it should be 22 like the other
macasp instances, and not 24. And in dra7xx_clks[] we have the bits wrong
way around.
Fixes: dffa9051d546 ("clk: ti: dra7: add new clkctrl data")
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/clk/ti/clk-7xx.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index b57fe09b428be..9dd6185a4b4e2 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -683,7 +683,7 @@ static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst
{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
- { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" },
+ { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
{ DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
{ DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
@@ -828,8 +828,8 @@ static struct ti_dt_clk dra7xx_clks[] = {
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
- DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"),
- DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"),
+ DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
+ DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
--
2.20.1
^ permalink raw reply related
* [PATCH v2 1/5] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
From: Martin Blumenstingl @ 2019-10-27 16:23 UTC (permalink / raw)
To: narmstrong, jbrunet, linux-amlogic, khilman
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, Martin Blumenstingl, Rob Herring
In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com>
Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in
the MMCBUS registers. There is no public documentation on this, but the
GPL u-boot sources from the Amlogic BSP show that:
- it uses the same XTAL input as the main clock controller
- it contains a PLL which seems to be implemented just like the other
PLLs in this SoC
- there is a power-of-two PLL post-divider
Add the documentation and header file for this DDR clock controller.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../clock/amlogic,meson8-ddr-clkc.yaml | 50 +++++++++++++++++++
include/dt-bindings/clock/meson8-ddr-clkc.h | 4 ++
2 files changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml
create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml
new file mode 100644
index 000000000000..4b8669f870ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic DDR Clock Controller Device Tree Bindings
+
+maintainers:
+ - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson8-ddr-clkc
+ - amlogic,meson8b-ddr-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: xtal
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ ddr_clkc: clock-controller@400 {
+ compatible = "amlogic,meson8-ddr-clkc";
+ reg = <0x400 0x20>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
+...
diff --git a/include/dt-bindings/clock/meson8-ddr-clkc.h b/include/dt-bindings/clock/meson8-ddr-clkc.h
new file mode 100644
index 000000000000..a8e0fa2987ab
--- /dev/null
+++ b/include/dt-bindings/clock/meson8-ddr-clkc.h
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#define DDR_CLKID_DDR_PLL_DCO 0
+#define DDR_CLKID_DDR_PLL 1
--
2.23.0
^ permalink raw reply related
* [PATCH v2 2/5] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
From: Martin Blumenstingl @ 2019-10-27 16:23 UTC (permalink / raw)
To: narmstrong, jbrunet, linux-amlogic, khilman
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, Martin Blumenstingl
In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com>
The Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in the
MMCBUS registers. There is no public documentation, but the u-boot GPL
sources from the Amlogic BSP show that the DDR clock controller is
identical on all three SoCs:
#define CFG_DDR_CLK 792
#define CFG_PLL_M (((CFG_DDR_CLK/12)*12)/24)
#define CFG_PLL_N 1
#define CFG_PLL_OD 1
// from set_ddr_clock:
t_ddr_pll_cntl= (CFG_PLL_OD << 16)|(CFG_PLL_N<<9)|(CFG_PLL_M<<0)
writel(timing_reg->t_ddr_pll_cntl|(1<<29),AM_DDR_PLL_CNTL);
writel(readl(AM_DDR_PLL_CNTL) & (~(1<<29)),AM_DDR_PLL_CNTL);
// from hx_ddr_power_down_enter: shut down DDR PLL
writel(readl(AM_DDR_PLL_CNTL)|(1<<30),AM_DDR_PLL_CNTL);
do { ... } while((readl(AM_DDR_PLL_CNTL)&(1<<31))==0)
This translates to:
- AM_DDR_PLL_CNTL[29] is the reset bit
- AM_DDR_PLL_CNTL[30] is the enable bit
- AM_DDR_PLL_CNTL[31] is the lock bit
- AM_DDR_PLL_CNTL[8:0] is the m value (assuming the width is 9 bits
based on the start of the n value)
- AM_DDR_PLL_CNTL[13:9] is the n value (assuming the width is 5 bits
based on the start of the od)
- AM_DDR_PLL_CNTL[17:16] is the od (assuming the width is 2 bits based
on other PLLs on this SoC)
Add a driver for this PLL setup because it's used as one of the inputs
of the audio clocks. There may be more clocks inside that clock
controller - those can be added in subsequent patches.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/meson8-ddr.c | 152 +++++++++++++++++++++++++++++++++
2 files changed, 153 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/meson/meson8-ddr.c
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 3939f218587a..6eca2a406ee3 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -18,4 +18,4 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
-obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
+obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c
new file mode 100644
index 000000000000..4aefcc5bdaae
--- /dev/null
+++ b/drivers/clk/meson/meson8-ddr.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson8 DDR clock controller
+ *
+ * Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ */
+
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
+
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+
+#include "clk-regmap.h"
+#include "clk-pll.h"
+
+#define AM_DDR_PLL_CNTL 0x00
+#define AM_DDR_PLL_CNTL1 0x04
+#define AM_DDR_PLL_CNTL2 0x08
+#define AM_DDR_PLL_CNTL3 0x0c
+#define AM_DDR_PLL_CNTL4 0x10
+#define AM_DDR_PLL_STS 0x14
+#define DDR_CLK_CNTL 0x18
+#define DDR_CLK_STS 0x1c
+
+static struct clk_regmap meson8_ddr_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = AM_DDR_PLL_CNTL,
+ .shift = 30,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = AM_DDR_PLL_CNTL,
+ .shift = 0,
+ .width = 9,
+ },
+ .n = {
+ .reg_off = AM_DDR_PLL_CNTL,
+ .shift = 9,
+ .width = 5,
+ },
+ .l = {
+ .reg_off = AM_DDR_PLL_CNTL,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = AM_DDR_PLL_CNTL,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ddr_pll_dco",
+ .ops = &meson_clk_pll_ro_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xtal",
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap meson8_ddr_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = AM_DDR_PLL_CNTL,
+ .shift = 16,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "ddr_pll",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &meson8_ddr_pll_dco.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = {
+ .hws = {
+ [DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw,
+ [DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw,
+ },
+ .num = 2,
+};
+
+static struct clk_regmap *const meson8_ddr_clk_regmaps[] = {
+ &meson8_ddr_pll_dco,
+ &meson8_ddr_pll,
+};
+
+static const struct regmap_config meson8_ddr_clkc_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = DDR_CLK_STS,
+};
+
+static int meson8_ddr_clkc_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ struct resource *res;
+ void __iomem *base;
+ struct clk_hw *hw;
+ int ret, i;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ &meson8_ddr_clkc_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /* Populate regmap */
+ for (i = 0; i < ARRAY_SIZE(meson8_ddr_clk_regmaps); i++)
+ meson8_ddr_clk_regmaps[i]->map = regmap;
+
+ /* Register all clks */
+ for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) {
+ hw = meson8_ddr_clk_hw_onecell_data.hws[i];
+
+ ret = devm_clk_hw_register(&pdev->dev, hw);
+ if (ret) {
+ dev_err(&pdev->dev, "Clock registration failed\n");
+ return ret;
+ }
+ }
+
+ return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
+ &meson8_ddr_clk_hw_onecell_data);
+}
+
+static const struct of_device_id meson8_ddr_clkc_match_table[] = {
+ { .compatible = "amlogic,meson8-ddr-clkc" },
+ { .compatible = "amlogic,meson8b-ddr-clkc" },
+ { /* sentinel */ },
+};
+
+static struct platform_driver meson8_ddr_clkc_driver = {
+ .probe = meson8_ddr_clkc_probe,
+ .driver = {
+ .name = "meson8-ddr-clkc",
+ .of_match_table = meson8_ddr_clkc_match_table,
+ },
+};
+
+builtin_platform_driver(meson8_ddr_clkc_driver);
--
2.23.0
^ permalink raw reply related
* [PATCH v2 4/5] ARM: dts: meson8: add the DDR clock controller
From: Martin Blumenstingl @ 2019-10-27 16:23 UTC (permalink / raw)
To: narmstrong, jbrunet, linux-amlogic, khilman
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, Martin Blumenstingl
In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com>
Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 4f59a4c8f036..257c1364864c 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -3,6 +3,7 @@
* Copyright 2014 Carlo Caione <carlo@caione.org>
*/
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
@@ -195,6 +196,14 @@
#size-cells = <1>;
ranges = <0x0 0xc8000000 0x8000>;
+ ddr_clkc: clock-controller@400 {
+ compatible = "amlogic,meson8-ddr-clkc";
+ reg = <0x400 0x20>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
dmcbus: bus@6000 {
compatible = "simple-bus";
reg = <0x6000 0x400>;
@@ -455,8 +464,8 @@
&hhi {
clkc: clock-controller {
compatible = "amlogic,meson8-clkc";
- clocks = <&xtal>;
- clock-names = "xtal";
+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ clock-names = "xtal", "ddr_pll";
#clock-cells = <1>;
#reset-cells = <1>;
};
--
2.23.0
^ permalink raw reply related
* [PATCH v2 5/5] ARM: dts: meson8b: add the DDR clock controller
From: Martin Blumenstingl @ 2019-10-27 16:23 UTC (permalink / raw)
To: narmstrong, jbrunet, linux-amlogic, khilman
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, Martin Blumenstingl
In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com>
Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8b.dtsi | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 1934666ff60f..8ac8bdfaf58f 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -4,6 +4,7 @@
* Author: Carlo Caione <carlo@endlessm.com>
*/
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8b-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h>
@@ -172,6 +173,14 @@
#size-cells = <1>;
ranges = <0x0 0xc8000000 0x8000>;
+ ddr_clkc: clock-controller@400 {
+ compatible = "amlogic,meson8b-ddr-clkc";
+ reg = <0x400 0x20>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
dmcbus: bus@6000 {
compatible = "simple-bus";
reg = <0x6000 0x400>;
@@ -434,8 +443,8 @@
&hhi {
clkc: clock-controller {
compatible = "amlogic,meson8-clkc";
- clocks = <&xtal>;
- clock-names = "xtal";
+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ clock-names = "xtal", "ddr_pll";
#clock-cells = <1>;
#reset-cells = <1>;
};
--
2.23.0
^ permalink raw reply related
* [PATCH v2 3/5] clk: meson: meson8b: use of_clk_hw_register to register the clocks
From: Martin Blumenstingl @ 2019-10-27 16:23 UTC (permalink / raw)
To: narmstrong, jbrunet, linux-amlogic, khilman
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, Martin Blumenstingl
In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com>
Switch from clk_hw_register to of_clk_hw_register so we can use
clk_parent_data.fw_name. This will be used to get the "xtal", "ddr_pll"
and possibly others from the .dtb.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/meson8b.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 70ac6755607e..306b809deb49 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -3696,7 +3696,7 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
if (!clk_hw_onecell_data->hws[i])
continue;
- ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]);
+ ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]);
if (ret)
return;
}
--
2.23.0
^ permalink raw reply related
* [PATCH v2 0/5] add the DDR clock controller on Meson8 and Meson8b
From: Martin Blumenstingl @ 2019-10-27 16:23 UTC (permalink / raw)
To: narmstrong, jbrunet, linux-amlogic, khilman
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, Martin Blumenstingl
Meson8 and Meson8b SoCs embed a DDR clock controller in their MMCBUS
registers. This series:
- adds support for this DDR clock controller (patches 0 and 1)
- wires up the DDR PLL as input for two audio clocks (patches 2 and 3)
- adds the DDR clock controller to meson8.dtsi and meson8b.dtsi
Special thanks go out to Alexandre Mergnat for switching the Amlogic
clock drivers over to parent_hws and parent_data. That made this series
a lot easier for me!
This series depends on v2 my other series from [0]:
"provide the XTAL clock via OF on Meson8/8b/8m2"
Changes since v1 at [1]:
- fixed the license of the .yaml binding and added Rob's Reviewed-by
- drop unused syscon.h include (spotted by Jerome - thanks)
- drop fast_io from regmap_config and add max_register as suggested
by Jerome
- dropped original patch #4 "clk: meson: meson8b: add the ddr_pll
input for the audio clocks" because I could not test that yet (that
patch was a forward-port from Amlogic's 3.10 BSP kernel)
[0] https://patchwork.kernel.org/cover/11214189/
[1] https://patchwork.kernel.org/cover/11155553/
Martin Blumenstingl (5):
dt-bindings: clock: add the Amlogic Meson8 DDR clock controller
binding
clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
clk: meson: meson8b: use of_clk_hw_register to register the clocks
ARM: dts: meson8: add the DDR clock controller
ARM: dts: meson8b: add the DDR clock controller
.../clock/amlogic,meson8-ddr-clkc.yaml | 50 ++++++
arch/arm/boot/dts/meson8.dtsi | 13 +-
arch/arm/boot/dts/meson8b.dtsi | 13 +-
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/meson8-ddr.c | 152 ++++++++++++++++++
drivers/clk/meson/meson8b.c | 2 +-
include/dt-bindings/clock/meson8-ddr-clkc.h | 4 +
7 files changed, 230 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml
create mode 100644 drivers/clk/meson/meson8-ddr.c
create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h
--
2.23.0
^ permalink raw reply
* [PATCH v2 0/5] provide the XTAL clock via OF on Meson8/8b/8m2
From: Martin Blumenstingl @ 2019-10-27 16:18 UTC (permalink / raw)
To: narmstrong, jbrunet, linux-amlogic, khilman
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, Martin Blumenstingl
So far the HHI clock controller has been providing the XTAL clock on
Amlogic Meson8/Meson8b/Meson8m2 SoCs.
This is not correct because the XTAL is actually a crystal on the
boards and the SoC has a dedicated input for it.
This updates the dt-bindings of the HHI clock controller and defines
a fixed-clock in meson.dtsi (along with switching everything over to
use this clock).
The clock driver needs three updates to use this:
- patch #2 uses clk_hw_set_parent in the CPU clock notifier. This drops
the explicit reference to CLKID_XTAL while at the same time making
the code much easier (thanks to Neil for providing this new method
as part of the G12A CPU clock bringup!)
- patch #3 ensures that the clock driver doesn't rely on it's internal
XTAL clock while not losing support for older .dtbs that don't have
the XTAL clock input yet
- with patch #4 the clock controller's own XTAL clock is not registered
anymore when a clock input is provided via OF
This series is a functional no-op. It's main goal is to better represent
how the actual hardware looks like.
Changes since v1 at [0]:
- add Rob's Reviewed-by to the dt-bindings patch
- check that "xtal" clock is actually passed via OF instead of checking
that there's any parent at all (which in the worst case may not be the
xtal clock) as suggested by Jerome
[0] https://patchwork.kernel.org/cover/11155515/
Martin Blumenstingl (5):
dt-bindings: clock: meson8b: add the clock inputs
clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
clk: meson: meson8b: change references to the XTAL clock to use the
name
clk: meson: meson8b: don't register the XTAL clock when provided via
OF
ARM: dts: meson: provide the XTAL clock using a fixed-clock
.../bindings/clock/amlogic,meson8b-clkc.txt | 5 +
arch/arm/boot/dts/meson.dtsi | 7 ++
arch/arm/boot/dts/meson6.dtsi | 7 --
arch/arm/boot/dts/meson8.dtsi | 15 +--
arch/arm/boot/dts/meson8b-ec100.dts | 2 +-
arch/arm/boot/dts/meson8b-mxq.dts | 2 +-
arch/arm/boot/dts/meson8b-odroidc1.dts | 2 +-
arch/arm/boot/dts/meson8b.dtsi | 15 +--
drivers/clk/meson/meson8b.c | 106 +++++++++---------
9 files changed, 87 insertions(+), 74 deletions(-)
--
2.23.0
^ permalink raw reply
* [PATCH v2 2/5] clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
From: Martin Blumenstingl @ 2019-10-27 16:18 UTC (permalink / raw)
To: narmstrong, jbrunet, linux-amlogic, khilman
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, Martin Blumenstingl
In-Reply-To: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com>
Switch from clk_set_parent() to clk_hw_set_parent() now that we have a
way to configure a mux clock based on clk_hw pointers. This simplifies
the meson8b_cpu_clk_notifier_cb logic. No functional changes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/meson8b.c | 21 ++++++++-------------
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 67e6691e080c..d376f80e806d 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -3585,7 +3585,7 @@ static const struct reset_control_ops meson8b_clk_reset_ops = {
struct meson8b_nb_data {
struct notifier_block nb;
- struct clk_hw_onecell_data *onecell_data;
+ struct clk_hw *cpu_clk;
};
static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
@@ -3593,30 +3593,25 @@ static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
{
struct meson8b_nb_data *nb_data =
container_of(nb, struct meson8b_nb_data, nb);
- struct clk_hw **hws = nb_data->onecell_data->hws;
- struct clk_hw *cpu_clk_hw, *parent_clk_hw;
- struct clk *cpu_clk, *parent_clk;
+ struct clk_hw *parent_clk;
int ret;
switch (event) {
case PRE_RATE_CHANGE:
- parent_clk_hw = hws[CLKID_XTAL];
+ /* xtal */
+ parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0);
break;
case POST_RATE_CHANGE:
- parent_clk_hw = hws[CLKID_CPU_SCALE_OUT_SEL];
+ /* cpu_scale_out_sel */
+ parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1);
break;
default:
return NOTIFY_DONE;
}
- cpu_clk_hw = hws[CLKID_CPUCLK];
- cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw));
-
- parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw));
-
- ret = clk_set_parent(cpu_clk, parent_clk);
+ ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk);
if (ret)
return notifier_from_errno(ret);
@@ -3695,7 +3690,7 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
return;
}
- meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data;
+ meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK];
/*
* FIXME we shouldn't program the muxes in notifier handlers. The
--
2.23.0
^ permalink raw reply related
* [PATCH v2 3/5] clk: meson: meson8b: change references to the XTAL clock to use the name
From: Martin Blumenstingl @ 2019-10-27 16:18 UTC (permalink / raw)
To: narmstrong, jbrunet, linux-amlogic, khilman
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, Martin Blumenstingl
In-Reply-To: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com>
The XTAL clock is an actual crystal which is mounted on the PCB. Thus
the meson8b clock controller driver should not provide the XTAL clock.
The meson8b clock controller driver must not use references to
the meson8b_xtal clock anymore before we can provide the XTAL clock
via OF. Replace the references to the meson8b_xtal.hw by using
clk_parent_data.name = "xtal" (along with index = -1) because this works
regardless how the XTAL clock is registered (either as fixed-clock in
the .dtb or - if missing - when registered in the meson8b clock
controller driver).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/meson8b.c | 73 ++++++++++++++++++++-----------------
1 file changed, 39 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index d376f80e806d..b785b67baf2b 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -97,8 +97,9 @@ static struct clk_regmap meson8b_fixed_pll_dco = {
.hw.init = &(struct clk_init_data){
.name = "fixed_pll_dco",
.ops = &meson_clk_pll_ro_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &meson8b_xtal.hw
+ .parent_data = &(const struct clk_parent_data) {
+ .name = "xtal",
+ .index = -1,
},
.num_parents = 1,
},
@@ -162,8 +163,9 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
/* sometimes also called "HPLL" or "HPLL PLL" */
.name = "hdmi_pll_dco",
.ops = &meson_clk_pll_ro_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &meson8b_xtal.hw
+ .parent_data = &(const struct clk_parent_data) {
+ .name = "xtal",
+ .index = -1,
},
.num_parents = 1,
},
@@ -237,8 +239,9 @@ static struct clk_regmap meson8b_sys_pll_dco = {
.hw.init = &(struct clk_init_data){
.name = "sys_pll_dco",
.ops = &meson_clk_pll_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &meson8b_xtal.hw
+ .parent_data = &(const struct clk_parent_data) {
+ .name = "xtal",
+ .index = -1,
},
.num_parents = 1,
},
@@ -631,9 +634,9 @@ static struct clk_regmap meson8b_cpu_in_sel = {
.hw.init = &(struct clk_init_data){
.name = "cpu_in_sel",
.ops = &clk_regmap_mux_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &meson8b_xtal.hw,
- &meson8b_sys_pll.hw,
+ .parent_data = (const struct clk_parent_data[]) {
+ { .name = "xtal", .index = -1, },
+ { .hw = &meson8b_sys_pll.hw, },
},
.num_parents = 2,
.flags = (CLK_SET_RATE_PARENT |
@@ -736,9 +739,9 @@ static struct clk_regmap meson8b_cpu_clk = {
.hw.init = &(struct clk_init_data){
.name = "cpu_clk",
.ops = &clk_regmap_mux_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &meson8b_xtal.hw,
- &meson8b_cpu_scale_out_sel.hw,
+ .parent_data = (const struct clk_parent_data[]) {
+ { .name = "xtal", .index = -1, },
+ { .hw = &meson8b_cpu_scale_out_sel.hw, },
},
.num_parents = 2,
.flags = (CLK_SET_RATE_PARENT |
@@ -758,12 +761,12 @@ static struct clk_regmap meson8b_nand_clk_sel = {
.name = "nand_clk_sel",
.ops = &clk_regmap_mux_ops,
/* FIXME all other parents are unknown: */
- .parent_hws = (const struct clk_hw *[]) {
- &meson8b_fclk_div4.hw,
- &meson8b_fclk_div3.hw,
- &meson8b_fclk_div5.hw,
- &meson8b_fclk_div7.hw,
- &meson8b_xtal.hw,
+ .parent_data = (const struct clk_parent_data[]) {
+ { .hw = &meson8b_fclk_div4.hw, },
+ { .hw = &meson8b_fclk_div3.hw, },
+ { .hw = &meson8b_fclk_div5.hw, },
+ { .hw = &meson8b_fclk_div7.hw, },
+ { .name = "xtal", .index = -1, },
},
.num_parents = 5,
.flags = CLK_SET_RATE_PARENT,
@@ -1721,8 +1724,9 @@ static struct clk_regmap meson8b_hdmi_sys_sel = {
.name = "hdmi_sys_sel",
.ops = &clk_regmap_mux_ro_ops,
/* FIXME: all other parents are unknown */
- .parent_hws = (const struct clk_hw *[]) {
- &meson8b_xtal.hw
+ .parent_data = &(const struct clk_parent_data) {
+ .name = "xtal",
+ .index = -1,
},
.num_parents = 1,
.flags = CLK_SET_RATE_NO_REPARENT,
@@ -1767,14 +1771,14 @@ static struct clk_regmap meson8b_hdmi_sys = {
* muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
* has mali_0 and no glitch-free mux.
*/
-static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = {
- &meson8b_xtal.hw,
- &meson8b_mpll2.hw,
- &meson8b_mpll1.hw,
- &meson8b_fclk_div7.hw,
- &meson8b_fclk_div4.hw,
- &meson8b_fclk_div3.hw,
- &meson8b_fclk_div5.hw,
+static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = {
+ { .name = "xtal", .index = -1, },
+ { .hw = &meson8b_mpll2.hw, },
+ { .hw = &meson8b_mpll1.hw, },
+ { .hw = &meson8b_fclk_div7.hw, },
+ { .hw = &meson8b_fclk_div4.hw, },
+ { .hw = &meson8b_fclk_div3.hw, },
+ { .hw = &meson8b_fclk_div5.hw, },
};
static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
@@ -1789,8 +1793,8 @@ static struct clk_regmap meson8b_mali_0_sel = {
.hw.init = &(struct clk_init_data){
.name = "mali_0_sel",
.ops = &clk_regmap_mux_ops,
- .parent_hws = meson8b_mali_0_1_parent_hws,
- .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
+ .parent_data = meson8b_mali_0_1_parent_data,
+ .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
/*
* Don't propagate rate changes up because the only changeable
* parents are mpll1 and mpll2 but we need those for audio and
@@ -1844,8 +1848,8 @@ static struct clk_regmap meson8b_mali_1_sel = {
.hw.init = &(struct clk_init_data){
.name = "mali_1_sel",
.ops = &clk_regmap_mux_ops,
- .parent_hws = meson8b_mali_0_1_parent_hws,
- .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
+ .parent_data = meson8b_mali_0_1_parent_data,
+ .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
/*
* Don't propagate rate changes up because the only changeable
* parents are mpll1 and mpll2 but we need those for audio and
@@ -1944,8 +1948,9 @@ static struct clk_regmap meson8m2_gp_pll_dco = {
.hw.init = &(struct clk_init_data){
.name = "gp_pll_dco",
.ops = &meson_clk_pll_ops,
- .parent_hws = (const struct clk_hw *[]) {
- &meson8b_xtal.hw
+ .parent_data = &(const struct clk_parent_data) {
+ .name = "xtal",
+ .index = -1,
},
.num_parents = 1,
},
--
2.23.0
^ permalink raw reply related
* [PATCH v2 4/5] clk: meson: meson8b: don't register the XTAL clock when provided via OF
From: Martin Blumenstingl @ 2019-10-27 16:18 UTC (permalink / raw)
To: narmstrong, jbrunet, linux-amlogic, khilman
Cc: robh+dt, mark.rutland, devicetree, linux-kernel, linux-arm-kernel,
linux-clk, Martin Blumenstingl
In-Reply-To: <20191027161805.1176321-1-martin.blumenstingl@googlemail.com>
The XTAL clock is an actual crystal on the PCB. Thus the meson8b clock
driver should not register the XTAL clock - instead it should be
provided via .dts and then passed to the clock controller.
Skip the registration of the XTAL clock if a parent clock is provided
via OF. Fall back to registering the XTAL clock if this is not the case
to keep support for old .dtbs.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/clk/meson/meson8b.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index b785b67baf2b..70ac6755607e 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -3682,10 +3682,16 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
meson8b_clk_regmaps[i]->map = map;
/*
- * register all clks
- * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
+ * always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the
+ * XTAL clock as input.
*/
- for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
+ if (!IS_ERR(of_clk_get_by_name(np, "xtal")))
+ i = CLKID_PLL_FIXED;
+ else
+ i = CLKID_XTAL;
+
+ /* register all clks */
+ for (; i < CLK_NR_CLKS; i++) {
/* array might be sparse */
if (!clk_hw_onecell_data->hws[i])
continue;
--
2.23.0
^ permalink raw reply related
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