[PATCH] clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks

[PATCH] clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks

[Abel Vesa]

Allow the USB3 second and third GCC PHY pipe clocks to propagate the
rate to the pipe clocks provided by the QMP combo PHYs. The first
instance is already doing that.

Fixes: ("161b7c401f4b clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
 drivers/clk/qcom/gcc-x1e80100.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index 1404017be918..8c72fdc99fd9 100644
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -5269,6 +5269,7 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
 				&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -5339,6 +5340,7 @@ static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
 				&gcc_usb3_tert_phy_pipe_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},

---
base-commit: 9d99040b1bc8dbf385a8aa535e9efcdf94466e19
change-id: 20240530-x1e80100-clk-gcc-usb3-sec-tert-set-parent-rate-420a9e2113d1

Best regards,
-- 
Abel Vesa <abel.vesa@linaro.org>

Re: [PATCH] clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks

[Dmitry Baryshkov]

On Thu, May 30, 2024 at 05:05:24PM +0300, Abel Vesa wrote:
> Allow the USB3 second and third GCC PHY pipe clocks to propagate the
> rate to the pipe clocks provided by the QMP combo PHYs. The first
> instance is already doing that.

Which driver changes the rate of those clocks?

> 
> Fixes: ("161b7c401f4b clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>  drivers/clk/qcom/gcc-x1e80100.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
> index 1404017be918..8c72fdc99fd9 100644
> --- a/drivers/clk/qcom/gcc-x1e80100.c
> +++ b/drivers/clk/qcom/gcc-x1e80100.c
> @@ -5269,6 +5269,7 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
>  				&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
>  		},
>  	},
> @@ -5339,6 +5340,7 @@ static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
>  				&gcc_usb3_tert_phy_pipe_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
>  		},
>  	},
> 
> ---
> base-commit: 9d99040b1bc8dbf385a8aa535e9efcdf94466e19
> change-id: 20240530-x1e80100-clk-gcc-usb3-sec-tert-set-parent-rate-420a9e2113d1
> 
> Best regards,
> -- 
> Abel Vesa <abel.vesa@linaro.org>
> 

-- 
With best wishes
Dmitry

Re: [PATCH] clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks

[Abel Vesa]

On 24-05-31 02:56:12, Dmitry Baryshkov wrote:
> On Thu, May 30, 2024 at 05:05:24PM +0300, Abel Vesa wrote:
> > Allow the USB3 second and third GCC PHY pipe clocks to propagate the
> > rate to the pipe clocks provided by the QMP combo PHYs. The first
> > instance is already doing that.
> 
> Which driver changes the rate of those clocks?

Sorry for the late reply.

These clocks are consumed by the combo PHYs, so driver is
phy-qcom-qmp-combo. This driver doesn't change the rates of the pipe
clocks as of yet.

The fix is still good, even if it's just to align all three clocks.

> 
> > 
> > Fixes: ("161b7c401f4b clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
> >  drivers/clk/qcom/gcc-x1e80100.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
> > index 1404017be918..8c72fdc99fd9 100644
> > --- a/drivers/clk/qcom/gcc-x1e80100.c
> > +++ b/drivers/clk/qcom/gcc-x1e80100.c
> > @@ -5269,6 +5269,7 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
> >  				&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> > +			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> >  		},
> >  	},
> > @@ -5339,6 +5340,7 @@ static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
> >  				&gcc_usb3_tert_phy_pipe_clk_src.clkr.hw,
> >  			},
> >  			.num_parents = 1,
> > +			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> >  		},
> >  	},
> > 
> > ---
> > base-commit: 9d99040b1bc8dbf385a8aa535e9efcdf94466e19
> > change-id: 20240530-x1e80100-clk-gcc-usb3-sec-tert-set-parent-rate-420a9e2113d1
> > 
> > Best regards,
> > -- 
> > Abel Vesa <abel.vesa@linaro.org>
> > 
> 
> -- 
> With best wishes
> Dmitry

Re: [PATCH] clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks

[Dmitry Baryshkov]

On Fri, Jun 28, 2024 at 11:14:47AM GMT, Abel Vesa wrote:
> On 24-05-31 02:56:12, Dmitry Baryshkov wrote:
> > On Thu, May 30, 2024 at 05:05:24PM +0300, Abel Vesa wrote:
> > > Allow the USB3 second and third GCC PHY pipe clocks to propagate the
> > > rate to the pipe clocks provided by the QMP combo PHYs. The first
> > > instance is already doing that.
> > 
> > Which driver changes the rate of those clocks?
> 
> Sorry for the late reply.
> 
> These clocks are consumed by the combo PHYs, so driver is
> phy-qcom-qmp-combo. This driver doesn't change the rates of the pipe
> clocks as of yet.
> 
> The fix is still good, even if it's just to align all three clocks.
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>


-- 
With best wishes
Dmitry

Re: [PATCH] clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks

[Bjorn Andersson]

On Thu, 30 May 2024 17:05:24 +0300, Abel Vesa wrote:
> Allow the USB3 second and third GCC PHY pipe clocks to propagate the
> rate to the pipe clocks provided by the QMP combo PHYs. The first
> instance is already doing that.
> 
> 

Applied, thanks!

[1/1] clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks
      commit: 2bb98a88edd5ddf15ca4cfc65595b7f7588351b5

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>