* [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC
@ 2026-08-24 15:01 Sreeshankar K
2026-08-24 15:01 ` [PATCH v6 01/13] dt-bindings: arm: qcom,ids: Add SoC ID for SM7250 Sreeshankar K
` (14 more replies)
0 siblings, 15 replies; 24+ messages in thread
From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael,
viresh.kumar, konradybcio, tglx, ulfh
Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila,
davidwronek, mani, robimarko, linux, devicetree, linux-kernel,
linux-arm-msm, linux-clk, linux-pm, Sreeshankar K
This patchset introduces foundational upstream support for the Qualcomm SM7250
SoC (internally codenamed Lito).
SM7250 is an ARMv8.2-A platform manufactured on a 7nm process, featuring an
octa-core Kryo 475 CPU configuration (1x Prime Cortex-A76, 1x Gold Cortex-A76,
and 6x Silver Cortex-A55) and Adreno 620 GPU.
This patchset is organized as follows:
> Document relevant device tree bindings (SoC ID, Kryo 475 CPUs, SCM, PDC,
RPMh clocks/power domains, GCC and cpufreq hardware).
> Add driver support for SM7250 in socinfo, rpmh-clk, rpmhpd, and GCC.
> Add the base SoC DTSI (sm7250.dtsi) defining the cpus, PSCI,
interrupt controllers, clock providers, power domains, and reserved memory.
Dependencies:
This patchset depends on the following patch:
> [PATCH] dt-bindings: clock: qcom,sm6375-gcc: Merge SM7150 into SM6375
Link: https://lore.kernel.org/linux-arm-msm/20260817082457.64797-2-krzysztof.kozlowski@oss.qualcomm.com/T/#t
[PATCH v5] Link: https://lore.kernel.org/linux-arm-msm/20260824130437.2771-1-sreeshankar0910@gmail.com/T/#t
Changes in [PATCH v6]:
[PATCH v6 04/13]: clk: qcom: Add Global Clock Controller (GCC) driver for SM7250
> Make all clk_init_data instances const across the driver.
Sreeshankar K (13):
dt-bindings: arm: qcom,ids: Add SoC ID for SM7250
soc: qcom: socinfo: Add SM7250 SoC ID
dt-bindings: clock: Add SM7250 global clock controller
clk: qcom: Add Global Clock Controller (GCC) driver for SM7250
dt-bindings: clock: qcom,rpmhcc: Document RPMHCC compatible for SM7250
clk: qcom: rpmh: Add SM7250 rpmh clocks
dt-bindings: power: qcom,rpmhpd: Document RPMh power domain for SM7250
pmdomain: qcom: rpmhpd: Add RPMh power domains for SM7250
dt-bindings: arm: cpus: Document Kryo 475 CPUs
dt-bindings: firmware: qcom,scm: Document SM7250 SCM
dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC
dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware
arm64: dts: qcom: Add SM7250 devicetree file
.../devicetree/bindings/arm/cpus.yaml | 1 +
.../bindings/clock/qcom,rpmhcc.yaml | 1 +
.../bindings/clock/qcom,sm6375-gcc.yaml | 4 +-
.../bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 +
.../bindings/firmware/qcom,scm.yaml | 1 +
.../interrupt-controller/qcom,pdc.yaml | 1 +
.../devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
arch/arm64/boot/dts/qcom/sm7250.dtsi | 771 ++++++
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c | 24 +
drivers/clk/qcom/gcc-sm7250.c | 2275 +++++++++++++++++
drivers/pmdomain/qcom/rpmhpd.c | 19 +
drivers/soc/qcom/socinfo.c | 1 +
include/dt-bindings/arm/qcom,ids.h | 1 +
include/dt-bindings/clock/qcom,sm7250-gcc.h | 163 ++
16 files changed, 3273 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/qcom/sm7250.dtsi
create mode 100644 drivers/clk/qcom/gcc-sm7250.c
create mode 100644 include/dt-bindings/clock/qcom,sm7250-gcc.h
--
2.43.0
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH v6 01/13] dt-bindings: arm: qcom,ids: Add SoC ID for SM7250 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 02/13] soc: qcom: socinfo: Add SM7250 SoC ID Sreeshankar K ` (13 subsequent siblings) 14 siblings, 0 replies; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K, Krzysztof Kozlowski, Konrad Dybcio, Dmitry Baryshkov Add the ID for the Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 2cf433f61..b63e4a0b8 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -209,6 +209,7 @@ #define QCOM_ID_IPQ8172 397 #define QCOM_ID_IPQ8173 398 #define QCOM_ID_IPQ8174 399 +#define QCOM_ID_SM7250 400 #define QCOM_ID_IPQ6018 402 #define QCOM_ID_IPQ6028 403 #define QCOM_ID_SDM429W 416 -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v6 02/13] soc: qcom: socinfo: Add SM7250 SoC ID 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 01/13] dt-bindings: arm: qcom,ids: Add SoC ID for SM7250 Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 03/13] dt-bindings: clock: Add SM7250 global clock controller Sreeshankar K ` (12 subsequent siblings) 14 siblings, 0 replies; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K, Dmitry Baryshkov Add SoC ID for Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 1836e226a..63ee5cd56 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -450,6 +450,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(IPQ8172) }, { qcom_board_id(IPQ8173) }, { qcom_board_id(IPQ8174) }, + { qcom_board_id(SM7250) }, { qcom_board_id(IPQ6018) }, { qcom_board_id(IPQ6028) }, { qcom_board_id(SDM429W) }, -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v6 03/13] dt-bindings: clock: Add SM7250 global clock controller 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 01/13] dt-bindings: arm: qcom,ids: Add SoC ID for SM7250 Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 02/13] soc: qcom: socinfo: Add SM7250 SoC ID Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 Sreeshankar K ` (11 subsequent siblings) 14 siblings, 0 replies; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K, Krzysztof Kozlowski Add device tree bindings for global clock controller on SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> --- Dependencies: This patch depends on the following patch: > [PATCH] dt-bindings: clock: qcom,sm6375-gcc: Merge SM7150 into SM6375 Link: https://lore.kernel.org/linux-arm-msm/20260817082457.64797-2-krzysztof.kozlowski@oss.qualcomm.com/T/#t .../bindings/clock/qcom,sm6375-gcc.yaml | 4 +- include/dt-bindings/clock/qcom,sm7250-gcc.h | 163 ++++++++++++++++++ 2 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,sm7250-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml index b4ad2ad14..39a2d2839 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml @@ -4,13 +4,14 @@ $id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Global Clock & Reset Controller on SM6375 and SM7150 +title: Qualcomm Global Clock & Reset Controller on SM6375, SM7150 and SM7250 maintainers: - Konrad Dybcio <konradybcio@kernel.org> - Bjorn Andersson <andersson@kernel.org> - Danila Tikhonov <danila@jiaxyga.com> - David Wronek <davidwronek@gmail.com> + - Sreeshankar K <sreeshankar0910@gmail.com> description: | Qualcomm global clock control module provides the clocks, resets and power @@ -26,6 +27,7 @@ properties: enum: - qcom,sm6375-gcc - qcom,sm7150-gcc + - qcom,sm7250-gcc clocks: items: diff --git a/include/dt-bindings/clock/qcom,sm7250-gcc.h b/include/dt-bindings/clock/qcom,sm7250-gcc.h new file mode 100644 index 000000000..765fdc38f --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm7250-gcc.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2026, Sreeshankar K <sreeshankar0910@gmail.com> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7250_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SM7250_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL6 2 +#define GPLL9 3 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 4 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5 +#define GCC_BOOT_ROM_AHB_CLK 6 +#define GCC_CAMERA_AHB_CLK 7 +#define GCC_CAMERA_HF_AXI_CLK 8 +#define GCC_CAMERA_SF_AXI_CLK 9 +#define GCC_CAMERA_XO_CLK 10 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 11 +#define GCC_CPUSS_AHB_CLK 12 +#define GCC_CPUSS_AHB_CLK_SRC 13 +#define GCC_CPUSS_GNOC_CLK 14 +#define GCC_CPUSS_RBCPR_CLK 15 +#define GCC_DDRSS_GPU_AXI_CLK 16 +#define GCC_DISP_GPLL0_CLK_SRC 17 +#define GCC_DISP_AHB_CLK 18 +#define GCC_DISP_HF_AXI_CLK 19 +#define GCC_DISP_SF_AXI_CLK 20 +#define GCC_DISP_XO_CLK 21 +#define GCC_GP1_CLK 22 +#define GCC_GP1_CLK_SRC 23 +#define GCC_GP2_CLK 24 +#define GCC_GP2_CLK_SRC 25 +#define GCC_GP3_CLK 26 +#define GCC_GP3_CLK_SRC 27 +#define GCC_GPU_CFG_AHB_CLK 28 +#define GCC_GPU_GPLL0_CLK_SRC 29 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 30 +#define GCC_GPU_IREF_CLK 31 +#define GCC_GPU_MEMNOC_GFX_CLK 32 +#define GCC_GPU_SNOC_DVM_GFX_CLK 33 +#define GCC_NPU_AXI_CLK 34 +#define GCC_NPU_BWMON2_AXI_CLK 35 +#define GCC_NPU_BWMON_AXI_CLK 36 +#define GCC_NPU_BWMON_CFG_AHB_CLK 37 +#define GCC_NPU_CFG_AHB_CLK 38 +#define GCC_NPU_DMA_CLK 39 +#define GCC_NPU_GPLL0_CLK_SRC 40 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 41 +#define GCC_PDM2_CLK 42 +#define GCC_PDM2_CLK_SRC 43 +#define GCC_PDM_AHB_CLK 44 +#define GCC_PDM_XO4_CLK 45 +#define GCC_PRNG_AHB_CLK 46 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 47 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 48 +#define GCC_QMIP_DISP_AHB_CLK 49 +#define GCC_QMIP_RT_DISP_AHB_CLK 50 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 51 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 52 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 53 +#define GCC_QUPV3_WRAP0_CORE_CLK 54 +#define GCC_QUPV3_WRAP0_S0_CLK 55 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 56 +#define GCC_QUPV3_WRAP0_S1_CLK 57 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 58 +#define GCC_QUPV3_WRAP0_S2_CLK 59 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 60 +#define GCC_QUPV3_WRAP0_S3_CLK 61 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 62 +#define GCC_QUPV3_WRAP0_S4_CLK 63 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 64 +#define GCC_QUPV3_WRAP0_S5_CLK 65 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 66 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 67 +#define GCC_QUPV3_WRAP1_CORE_CLK 68 +#define GCC_QUPV3_WRAP1_S0_CLK 69 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 70 +#define GCC_QUPV3_WRAP1_S1_CLK 71 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 72 +#define GCC_QUPV3_WRAP1_S2_CLK 73 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 74 +#define GCC_QUPV3_WRAP1_S3_CLK 75 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 76 +#define GCC_QUPV3_WRAP1_S4_CLK 77 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 78 +#define GCC_QUPV3_WRAP1_S5_CLK 79 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 80 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 81 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 82 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 83 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 84 +#define GCC_SDCC1_AHB_CLK 85 +#define GCC_SDCC1_APPS_CLK 86 +#define GCC_SDCC1_APPS_CLK_SRC 87 +#define GCC_SDCC1_ICE_CORE_CLK 88 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 89 +#define GCC_SDCC2_AHB_CLK 90 +#define GCC_SDCC2_APPS_CLK 91 +#define GCC_SDCC2_APPS_CLK_SRC 92 +#define GCC_SDCC4_AHB_CLK 93 +#define GCC_SDCC4_APPS_CLK 94 +#define GCC_SDCC4_APPS_CLK_SRC 95 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96 +#define GCC_UFS_1X_CLKREF_CLK 97 +#define GCC_UFS_PHY_AHB_CLK 98 +#define GCC_UFS_PHY_AXI_CLK 99 +#define GCC_UFS_PHY_AXI_CLK_SRC 100 +#define GCC_UFS_PHY_ICE_CORE_CLK 101 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 +#define GCC_UFS_PHY_PHY_AUX_CLK 103 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 106 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 107 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 108 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 109 +#define GCC_USB30_PRIM_MASTER_CLK 110 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 112 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 113 +#define GCC_USB30_PRIM_SLEEP_CLK 114 +#define GCC_USB3_PRIM_CLKREF_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK 116 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 117 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 118 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 119 +#define GCC_VIDEO_AHB_CLK 120 +#define GCC_VIDEO_AXI_CLK 121 +#define GCC_VIDEO_XO_CLK 122 + +/* GCC resets */ +#define GCC_DPM_BCR 0 +#define GCC_GPU_BCR 1 +#define GCC_MMSS_BCR 2 +#define GCC_NPU_BWMON_BCR 3 +#define GCC_NPU_BCR 4 +#define GCC_PDM_BCR 5 +#define GCC_PRNG_BCR 6 +#define GCC_QUPV3_WRAPPER_0_BCR 7 +#define GCC_QUPV3_WRAPPER_1_BCR 8 +#define GCC_QUSB2PHY_PRIM_BCR 9 +#define GCC_SDCC1_BCR 10 +#define GCC_SDCC2_BCR 11 +#define GCC_SDCC4_BCR 12 +#define GCC_UFS_PHY_BCR 13 +#define GCC_USB30_PRIM_BCR 14 +#define GCC_USB3_DP_PHY_PRIM_BCR 15 +#define GCC_USB3_PHY_PRIM_BCR 16 +#define GCC_USB3PHY_PHY_PRIM_BCR 17 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 18 + +/* GCC power domains */ +#define UFS_PHY_GDSC 0 +#define USB30_PRIM_GDSC 1 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 3 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 4 + +#endif -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v6 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (2 preceding siblings ...) 2026-08-24 15:01 ` [PATCH v6 03/13] dt-bindings: clock: Add SM7250 global clock controller Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-31 23:26 ` Bjorn Andersson 2026-08-24 15:01 ` [PATCH v6 05/13] dt-bindings: clock: qcom,rpmhcc: Document RPMHCC compatible " Sreeshankar K ` (10 subsequent siblings) 14 siblings, 1 reply; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K Add support for the global clock controller found on SM7250 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sm7250.c | 2275 +++++++++++++++++++++++++++++++++ 3 files changed, 2285 insertions(+) create mode 100644 drivers/clk/qcom/gcc-sm7250.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 7d84c2f1d..532d8f002 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1416,6 +1416,15 @@ config SM_GCC_7150 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. +config SM_GCC_7250 + tristate "SM7250 Global Clock Controller" + depends on ARM64 || COMPILE_TEST + select QCOM_GDSC + help + Support for the global clock controller on SM7250 devices. + Say Y if you want to use peripheral devices such as UART, + SPI, I2C, USB, SD/UFS etc. + config SM_GCC_MILOS tristate "Milos Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 58f9a5eb6..18414089c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -174,6 +174,7 @@ obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o obj-$(CONFIG_SM_GCC_6375) += gcc-sm6375.o obj-$(CONFIG_SM_GCC_7150) += gcc-sm7150.o +obj-$(CONFIG_SM_GCC_7250) += gcc-sm7250.o obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o diff --git a/drivers/clk/qcom/gcc-sm7250.c b/drivers/clk/qcom/gcc-sm7250.c new file mode 100644 index 000000000..899a2ed75 --- /dev/null +++ b/drivers/clk/qcom/gcc-sm7250.c @@ -0,0 +1,2275 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2026, Sreeshankar K <sreeshankar0910@gmail.com> + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,sm7250-gcc.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_EVEN, + P_GPLL0_OUT_MAIN, + P_GPLL6_OUT_MAIN, + P_GPLL9_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct clk_alpha_pll gpll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .enable_reg = 0x52010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpll0", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_even = { + .offset = 0x0, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpll0_out_even", + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static struct clk_alpha_pll gpll6 = { + .offset = 0x13000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .enable_reg = 0x52010, + .enable_mask = BIT(6), + .hw.init = &(const struct clk_init_data){ + .name = "gpll6", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll9 = { + .offset = 0x1c000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .enable_reg = 0x52010, + .enable_mask = BIT(9), + .hw.init = &(const struct clk_init_data){ + .name = "gpll9", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct clk_parent_data gcc_parent_data_0_ao[] = { + { .index = DT_BI_TCXO_AO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .index = DT_SLEEP_CLK }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL6_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll6.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL9_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll9.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] = { + { .index = DT_BI_TCXO }, + { .index = DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { + .cmd_rcgr = 0x48010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_cpuss_ahb_clk_src", + .parent_data = gcc_parent_data_0_ao, + .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src = { + .cmd_rcgr = 0x64004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_gp1_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src = { + .cmd_rcgr = 0x65004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_gp2_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src = { + .cmd_rcgr = 0x66004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_gp3_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src = { + .cmd_rcgr = 0x33010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pdm2_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_pdm2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), + F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), + F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), + F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), + F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { + .name = "gcc_qupv3_wrap0_s0_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { + .cmd_rcgr = 0x17010, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { + .name = "gcc_qupv3_wrap0_s1_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { + .cmd_rcgr = 0x17140, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { + .name = "gcc_qupv3_wrap0_s2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { + .cmd_rcgr = 0x17270, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { + .name = "gcc_qupv3_wrap0_s3_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { + .cmd_rcgr = 0x173a0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { + .name = "gcc_qupv3_wrap0_s4_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { + .cmd_rcgr = 0x174d0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { + .name = "gcc_qupv3_wrap0_s5_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { + .cmd_rcgr = 0x17600, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { + .name = "gcc_qupv3_wrap1_s0_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { + .cmd_rcgr = 0x18010, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { + .name = "gcc_qupv3_wrap1_s1_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { + .cmd_rcgr = 0x18140, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { + .name = "gcc_qupv3_wrap1_s2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { + .cmd_rcgr = 0x18270, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { + .name = "gcc_qupv3_wrap1_s3_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { + .cmd_rcgr = 0x183a0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { + .name = "gcc_qupv3_wrap1_s4_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { + .cmd_rcgr = 0x184d0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { + .name = "gcc_qupv3_wrap1_s5_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { + .cmd_rcgr = 0x18600, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { + .cmd_rcgr = 0x26024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_floor_ops, + }, +}; + + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { + .cmd_rcgr = 0x2600c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { + .cmd_rcgr = 0x1400c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk_src", + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { + .cmd_rcgr = 0x1600c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_sdcc4_apps_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { + .cmd_rcgr = 0x77024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_axi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { + .cmd_rcgr = 0x7706c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_ice_core_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { + .cmd_rcgr = 0x770a0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { + .cmd_rcgr = 0x77084, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_unipro_core_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { + .cmd_rcgr = 0xf020, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_usb30_prim_master_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { + .cmd_rcgr = 0xf038, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { + .cmd_rcgr = 0xf064, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gcc_usb3_prim_phy_aux_clk_src", + .parent_data = gcc_parent_data_5, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { + .halt_reg = 0x770cc, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x770cc, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x770cc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_aggre_ufs_phy_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { + .halt_reg = 0xf080, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0xf080, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_aggre_usb3_prim_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x38004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x38004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(10), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_hf_axi_clk = { + .halt_reg = 0xb028, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0xb028, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_camera_hf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_sf_axi_clk = { + .halt_reg = 0xb02c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0xb02c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_camera_sf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { + .halt_reg = 0xf07c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0xf07c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_gnoc_clk = { + .halt_reg = 0x48064, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(29), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_cpuss_gnoc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_rbcpr_clk = { + .halt_reg = 0x48004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_cpuss_rbcpr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_gpu_axi_clk = { + .halt_reg = 0x71154, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x71154, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_ddrss_gpu_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_gpll0_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(20), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_disp_gpll0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk = { + .halt_reg = 0xb030, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0xb030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_disp_hf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_sf_axi_clk = { + .halt_reg = 0xb034, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0xb034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_disp_sf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x64000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x64000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_gp1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x65000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x65000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_gp2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x66000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x66000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_gp3_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(15), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(16), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_gpu_gpll0_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpll0_out_even.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_iref_clk = { + .halt_reg = 0x8c014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_gpu_iref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_memnoc_gfx_clk = { + .halt_reg = 0x7100c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7100c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_gpu_memnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { + .halt_reg = 0x71018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x71018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_gpu_snoc_dvm_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_axi_clk = { + .halt_reg = 0x4d008, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x4d008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_npu_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_bwmon2_axi_clk = { + .halt_reg = 0x7000c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7000c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_npu_bwmon2_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_bwmon_axi_clk = { + .halt_reg = 0x70008, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x70008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_npu_bwmon_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_dma_clk = { + .halt_reg = 0x4d00c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x4d00c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_npu_dma_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(18), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_npu_gpll0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(19), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_npu_gpll0_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpll0_out_even.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x3300c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3300c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_pdm2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x33004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x33004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x33004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x33008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x33008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_pdm_xo4_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x34004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(13), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { + .halt_reg = 0xb018, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xb018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qmip_camera_nrt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { + .halt_reg = 0xb01c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xb01c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb01c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qmip_camera_rt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_ahb_clk = { + .halt_reg = 0xb020, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xb020, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qmip_disp_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_rt_disp_ahb_clk = { + .halt_reg = 0xb07c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xb07c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb07c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qmip_rt_disp_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { + .halt_reg = 0xb010, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xb010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qmip_video_cvp_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { + .halt_reg = 0xb014, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xb014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb014, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qmip_video_vcodec_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { + .halt_reg = 0x23008, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(9), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap0_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk = { + .halt_reg = 0x23000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(8), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap0_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk = { + .halt_reg = 0x1700c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(10), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s0_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk = { + .halt_reg = 0x1713c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(11), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk = { + .halt_reg = 0x1726c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(12), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk = { + .halt_reg = 0x1739c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(13), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s3_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk = { + .halt_reg = 0x174cc, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(14), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s4_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk = { + .halt_reg = 0x175fc, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(15), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s5_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { + .halt_reg = 0x23140, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(18), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap1_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_clk = { + .halt_reg = 0x23138, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(19), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap1_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s0_clk = { + .halt_reg = 0x1800c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(22), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s0_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s1_clk = { + .halt_reg = 0x1813c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(23), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s1_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s2_clk = { + .halt_reg = 0x1826c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(24), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s2_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s3_clk = { + .halt_reg = 0x1839c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(25), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s3_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s4_clk = { + .halt_reg = 0x184cc, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(26), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s4_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s5_clk = { + .halt_reg = 0x185fc, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(27), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s5_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { + .halt_reg = 0x17004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(6), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap_0_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { + .halt_reg = 0x17008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(7), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap_0_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { + .halt_reg = 0x18004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(20), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap_1_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { + .halt_reg = 0x18008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x18008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = BIT(21), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_qupv3_wrap_1_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x26004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x26004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x26004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x26008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x26008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk = { + .halt_reg = 0x2603c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2603c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc1_ice_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x14008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x14008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_sdcc2_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk = { + .halt_reg = 0x14004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x14004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_ahb_clk = { + .halt_reg = 0x16008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x16008, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_sdcc4_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_apps_clk = { + .halt_reg = 0x16004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x16004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_sdcc4_apps_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_sdcc4_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_1x_clkref_clk = { + .halt_reg = 0x8c000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_1x_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ahb_clk = { + .halt_reg = 0x77018, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x77018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x77018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_clk = { + .halt_reg = 0x77010, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x77010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x77010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_clk = { + .halt_reg = 0x77064, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x77064, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x77064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_ice_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_clk = { + .halt_reg = 0x7709c, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x7709c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7709c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { + .halt_reg = 0x77020, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x77020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_rx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { + .halt_reg = 0x770b8, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x770b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_rx_symbol_1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { + .halt_reg = 0x7701c, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x7701c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_tx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_clk = { + .halt_reg = 0x7705c, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x7705c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7705c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_ufs_phy_unipro_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk = { + .halt_reg = 0xf010, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0xf010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_usb30_prim_master_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { + .halt_reg = 0xf01c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf01c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk = { + .halt_reg = 0xf018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_usb30_prim_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_clk = { + .halt_reg = 0x8c010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c010, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_usb3_prim_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_aux_clk = { + .halt_reg = 0xf054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_usb3_prim_phy_aux_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { + .halt_reg = 0xf058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf058, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_usb3_prim_phy_com_aux_clk", + .parent_hws = (const struct clk_hw*[]){ + &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { + .halt_reg = 0xf05c, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0xf05c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_usb3_prim_phy_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi_clk = { + .halt_reg = 0xb080, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0xb080, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gcc_video_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc ufs_phy_gdsc = { + .gdscr = 0x77004, + .pd = { + .name = "ufs_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb30_prim_gdsc = { + .gdscr = 0xf004, + .pd = { + .name = "usb30_prim_gdsc", + }, + .pwrsts = PWRSTS_RET_ON, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { + .gdscr = 0x7d050, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { + .gdscr = 0x7d058, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = { + .gdscr = 0x7d054, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct clk_regmap *gcc_sm7250_clocks[] = { + [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, + [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, + [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, + [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, + [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, + [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, + [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, + [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, + [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, + [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, + [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, + [GCC_NPU_BWMON2_AXI_CLK] = &gcc_npu_bwmon2_axi_clk.clkr, + [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr, + [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr, + [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, + [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, + [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, + [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, + [GCC_QMIP_RT_DISP_AHB_CLK] = &gcc_qmip_rt_disp_ahb_clk.clkr, + [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, + [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, + [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, + [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, + [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, + [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, + [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, + [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, + [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, + [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, + [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, + [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, + [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, + [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, + [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, + [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, + [GCC_UFS_1X_CLKREF_CLK] = &gcc_ufs_1x_clkref_clk.clkr, + [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, + [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, + [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = + &gcc_ufs_phy_unipro_core_clk_src.clkr, + [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = + &gcc_usb30_prim_mock_utmi_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, + [GPLL0] = &gpll0.clkr, + [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, + [GPLL6] = &gpll6.clkr, + [GPLL9] = &gpll9.clkr, +}; + +static struct gdsc *gcc_sm7250_gdscs[] = { + [UFS_PHY_GDSC] = &ufs_phy_gdsc, + [USB30_PRIM_GDSC] = &usb30_prim_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = + &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = + &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, + [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = + &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, +}; + +static const struct qcom_reset_map gcc_sm7250_resets[] = { + [GCC_DPM_BCR] = { 0x46000 }, + [GCC_GPU_BCR] = { 0x71000 }, + [GCC_MMSS_BCR] = { 0xb000 }, + [GCC_NPU_BWMON_BCR] = { 0x70000 }, + [GCC_NPU_BCR] = { 0x4d000 }, + [GCC_PDM_BCR] = { 0x33000 }, + [GCC_PRNG_BCR] = { 0x34000 }, + [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, + [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_SDCC1_BCR] = { 0x26000 }, + [GCC_SDCC2_BCR] = { 0x14000 }, + [GCC_SDCC4_BCR] = { 0x16000 }, + [GCC_UFS_PHY_BCR] = { 0x77000 }, + [GCC_USB30_PRIM_BCR] = { 0xf000 }, + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, + [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, + [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, +}; + +static const u32 gcc_sm7250_critical_cbcrs[] = { + 0x0b004, /* GCC_VIDEO_AHB_CLK */ + 0x0b008, /* GCC_CAMERA_AHB_CLK */ + 0x0b00c, /* GCC_DISP_AHB_CLK */ + 0x0b038, /* GCC_VIDEO_XO_CLK */ + 0x0b03c, /* GCC_CAMERA_XO_CLK */ + 0x0b040, /* GCC_DISP_XO_CLK */ + 0x4d004, /* GCC_NPU_CFG_AHB_CLK */ + 0x52000, /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + 0x70004, /* GCC_NPU_BWMON_CFG_AHB_CLK */ + 0x71004, /* GCC_GPU_CFG_AHB_CLK */ +}; + +static const struct clk_rcg_dfs_data gcc_sm7250_dfs_clocks[] = { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), +}; + +static const struct regmap_config gcc_sm7250_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9c100, + .fast_io = true, +}; + +static void gcc_sm7250_clk_regs_configure(struct regmap *regmap) +{ + /* + * Disable the GPLL0 active input to NPU and GPU + * via MISC registers. + */ + regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); + regmap_update_bits(regmap, 0x71028, 0x3, 0x3); + + /* + * Critical clocks that has same register with + * different mask + */ + regmap_update_bits(regmap, 0x52000, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ +} + +static const struct qcom_cc_driver_data gcc_sm7250_driver_data = { + .clk_cbcrs = gcc_sm7250_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(gcc_sm7250_critical_cbcrs), + .dfs_rcgs = gcc_sm7250_dfs_clocks, + .num_dfs_rcgs = ARRAY_SIZE(gcc_sm7250_dfs_clocks), + .clk_regs_configure = gcc_sm7250_clk_regs_configure, +}; + +static const struct qcom_cc_desc gcc_sm7250_desc = { + .config = &gcc_sm7250_regmap_config, + .clks = gcc_sm7250_clocks, + .num_clks = ARRAY_SIZE(gcc_sm7250_clocks), + .resets = gcc_sm7250_resets, + .num_resets = ARRAY_SIZE(gcc_sm7250_resets), + .gdscs = gcc_sm7250_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_sm7250_gdscs), + .use_rpm = true, + .driver_data = &gcc_sm7250_driver_data, +}; + +static const struct of_device_id gcc_sm7250_match_table[] = { + { .compatible = "qcom,sm7250-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_sm7250_match_table); + +static int gcc_sm7250_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_sm7250_desc); +} + +static struct platform_driver gcc_sm7250_driver = { + .probe = gcc_sm7250_probe, + .driver = { + .name = "gcc-sm7250", + .of_match_table = gcc_sm7250_match_table, + }, +}; + +static int __init gcc_sm7250_init(void) +{ + return platform_driver_register(&gcc_sm7250_driver); +} +subsys_initcall(gcc_sm7250_init); + +static void __exit gcc_sm7250_exit(void) +{ + platform_driver_unregister(&gcc_sm7250_driver); +} +module_exit(gcc_sm7250_exit); + +MODULE_DESCRIPTION("QTI GCC SM7250 Driver"); +MODULE_LICENSE("GPL"); -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 2026-08-24 15:01 ` [PATCH v6 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 Sreeshankar K @ 2026-08-31 23:26 ` Bjorn Andersson 2026-09-01 6:35 ` Sreeshankar K 0 siblings, 1 reply; 24+ messages in thread From: Bjorn Andersson @ 2026-08-31 23:26 UTC (permalink / raw) To: Sreeshankar K Cc: robh, krzk+dt, conor+dt, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh, bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm On Mon, Aug 24, 2026 at 03:01:47PM +0000, Sreeshankar K wrote: > Add support for the global clock controller found on SM7250 > based devices. This should allow most non-multimedia device > drivers to probe and control their clocks. "This should"? > > Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> [..] > diff --git a/drivers/clk/qcom/gcc-sm7250.c b/drivers/clk/qcom/gcc-sm7250.c [..] > + .clk_regs_configure = gcc_sm7250_clk_regs_configure, /home/bjorn/sandbox/kernel/workspace/drivers/clk/qcom/gcc-sm7250.c:2228:24: error: incompatible function pointer types initializing 'void (*)(struct device *, struct regmap *)' with an expression of type 'void (struct regmap *)' [-Wincompatible-function-pointer-types] 2228 | .clk_regs_configure = gcc_sm7250_clk_regs_configure, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Thank you, Bjorn > +}; ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 2026-08-31 23:26 ` Bjorn Andersson @ 2026-09-01 6:35 ` Sreeshankar K 0 siblings, 0 replies; 24+ messages in thread From: Sreeshankar K @ 2026-09-01 6:35 UTC (permalink / raw) To: Bjorn Andersson Cc: robh, krzk+dt, conor+dt, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh, bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm On Tue, 1 Sept 2026 at 04:56, Bjorn Andersson <andersson@kernel.org> wrote: > > On Mon, Aug 24, 2026 at 03:01:47PM +0000, Sreeshankar K wrote: > > Add support for the global clock controller found on SM7250 > > based devices. This should allow most non-multimedia device > > drivers to probe and control their clocks. > > "This should"? > > > > > Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> > [..] > > diff --git a/drivers/clk/qcom/gcc-sm7250.c b/drivers/clk/qcom/gcc-sm7250.c > [..] > > + .clk_regs_configure = gcc_sm7250_clk_regs_configure, > > /home/bjorn/sandbox/kernel/workspace/drivers/clk/qcom/gcc-sm7250.c:2228:24: error: incompatible function pointer types initializing 'void (*)(struct device *, struct regmap *)' with an expression of type 'void (struct regmap *)' [-Wincompatible-function-pointer-types] > 2228 | .clk_regs_configure = gcc_sm7250_clk_regs_configure, > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > 1 error generated. > > Thank you, > Bjorn > > > +}; Thanks for catching this. I will fix the error and send a v7. Regards, Sreeshankar K ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6 05/13] dt-bindings: clock: qcom,rpmhcc: Document RPMHCC compatible for SM7250 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (3 preceding siblings ...) 2026-08-24 15:01 ` [PATCH v6 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 06/13] clk: qcom: rpmh: Add SM7250 rpmh clocks Sreeshankar K ` (9 subsequent siblings) 14 siblings, 0 replies; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K, Krzysztof Kozlowski Document RPMHCC compatible for clock rpmh driver on Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index d344b3386..df9e37f90 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -38,6 +38,7 @@ properties: - qcom,sdx75-rpmh-clk - qcom,sm4450-rpmh-clk - qcom,sm6350-rpmh-clk + - qcom,sm7250-rpmh-clk - qcom,sm8150-rpmh-clk - qcom,sm8250-rpmh-clk - qcom,sm8350-rpmh-clk -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v6 06/13] clk: qcom: rpmh: Add SM7250 rpmh clocks 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (4 preceding siblings ...) 2026-08-24 15:01 ` [PATCH v6 05/13] dt-bindings: clock: qcom,rpmhcc: Document RPMHCC compatible " Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 07/13] dt-bindings: power: qcom,rpmhpd: Document RPMh power domain for SM7250 Sreeshankar K ` (8 subsequent siblings) 14 siblings, 0 replies; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K, Dmitry Baryshkov, Konrad Dybcio Add the RPMH clocks present in SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> --- drivers/clk/qcom/clk-rpmh.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 6367b2a5a..f4cafa274 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -1011,6 +1011,29 @@ static const struct clk_rpmh_desc clk_rpmh_hawi = { .num_clks = ARRAY_SIZE(hawi_rpmh_clocks), }; +static struct clk_hw *sm7250_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_d.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_d_ao.hw, + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sm7250 = { + .clks = sm7250_rpmh_clocks, + .num_clks = ARRAY_SIZE(sm7250_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -1120,6 +1143,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75}, { .compatible = "qcom,sm4450-rpmh-clk", .data = &clk_rpmh_sm4450}, { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350}, + { .compatible = "qcom,sm7250-rpmh-clk", .data = &clk_rpmh_sm7250}, { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v6 07/13] dt-bindings: power: qcom,rpmhpd: Document RPMh power domain for SM7250 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (5 preceding siblings ...) 2026-08-24 15:01 ` [PATCH v6 06/13] clk: qcom: rpmh: Add SM7250 rpmh clocks Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-28 9:57 ` Krzysztof Kozlowski 2026-08-24 15:01 ` [PATCH v6 08/13] pmdomain: qcom: rpmhpd: Add RPMh power domains " Sreeshankar K ` (7 subsequent siblings) 14 siblings, 1 reply; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K Document the RPMh power domain for SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 0a45e1f55..e08441915 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -63,6 +63,7 @@ properties: - qcom,sm6350-rpmhpd - qcom,sm6375-rpmpd - qcom,sm7150-rpmhpd + - qcom,sm7250-rpmhpd - qcom,sm8150-rpmhpd - qcom,sm8250-rpmhpd - qcom,sm8350-rpmhpd -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 07/13] dt-bindings: power: qcom,rpmhpd: Document RPMh power domain for SM7250 2026-08-24 15:01 ` [PATCH v6 07/13] dt-bindings: power: qcom,rpmhpd: Document RPMh power domain for SM7250 Sreeshankar K @ 2026-08-28 9:57 ` Krzysztof Kozlowski 0 siblings, 0 replies; 24+ messages in thread From: Krzysztof Kozlowski @ 2026-08-28 9:57 UTC (permalink / raw) To: Sreeshankar K Cc: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh, bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm On Mon, Aug 24, 2026 at 03:01:50PM +0000, Sreeshankar K wrote: > Document the RPMh power domain for SM7250 SoC. > > Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> > --- > Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + > 1 file changed, 1 insertion(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6 08/13] pmdomain: qcom: rpmhpd: Add RPMh power domains for SM7250 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (6 preceding siblings ...) 2026-08-24 15:01 ` [PATCH v6 07/13] dt-bindings: power: qcom,rpmhpd: Document RPMh power domain for SM7250 Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 09/13] dt-bindings: arm: cpus: Document Kryo 475 CPUs Sreeshankar K ` (6 subsequent siblings) 14 siblings, 0 replies; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K, Konrad Dybcio Add RPMh power domains for SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> --- drivers/pmdomain/qcom/rpmhpd.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmhpd.c b/drivers/pmdomain/qcom/rpmhpd.c index 96e4bd2f5..70d0ff5cc 100644 --- a/drivers/pmdomain/qcom/rpmhpd.c +++ b/drivers/pmdomain/qcom/rpmhpd.c @@ -490,6 +490,24 @@ static const struct rpmhpd_desc sm7150_desc = { .num_pds = ARRAY_SIZE(sm7150_rpmhpds), }; +/* SM7250 RPMH powerdomains */ +static struct rpmhpd *sm7250_rpmhpds[] = { + [RPMHPD_CX] = &cx_w_mx_parent, + [RPMHPD_CX_AO] = &cx_ao_w_mx_parent, + [RPMHPD_EBI] = &ebi, + [RPMHPD_GFX] = &gfx, + [RPMHPD_LCX] = &lcx, + [RPMHPD_LMX] = &lmx, + [RPMHPD_MSS] = &mss, + [RPMHPD_MX] = &mx, + [RPMHPD_MX_AO] = &mx_ao, +}; + +static const struct rpmhpd_desc sm7250_desc = { + .rpmhpds = sm7250_rpmhpds, + .num_pds = ARRAY_SIZE(sm7250_rpmhpds), +}; + /* SM8150 RPMH powerdomains */ static struct rpmhpd *sm8150_rpmhpds[] = { [SM8150_CX] = &cx_w_mx_parent, @@ -910,6 +928,7 @@ static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,sm4450-rpmhpd", .data = &sm4450_desc }, { .compatible = "qcom,sm6350-rpmhpd", .data = &sm6350_desc }, { .compatible = "qcom,sm7150-rpmhpd", .data = &sm7150_desc }, + { .compatible = "qcom,sm7250-rpmhpd", .data = &sm7250_desc }, { .compatible = "qcom,sm8150-rpmhpd", .data = &sm8150_desc }, { .compatible = "qcom,sm8250-rpmhpd", .data = &sm8250_desc }, { .compatible = "qcom,sm8350-rpmhpd", .data = &sm8350_desc }, -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v6 09/13] dt-bindings: arm: cpus: Document Kryo 475 CPUs 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (7 preceding siblings ...) 2026-08-24 15:01 ` [PATCH v6 08/13] pmdomain: qcom: rpmhpd: Add RPMh power domains " Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-28 9:58 ` Krzysztof Kozlowski 2026-08-24 15:01 ` [PATCH v6 10/13] dt-bindings: firmware: qcom,scm: Document SM7250 SCM Sreeshankar K ` (5 subsequent siblings) 14 siblings, 1 reply; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K Document Kryo 475 CPUs found in Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 5be89c584..2a90af67c 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -212,6 +212,7 @@ properties: - qcom,kryo465 - qcom,kryo468 - qcom,kryo470 + - qcom,kryo475 - qcom,kryo485 - qcom,kryo560 - qcom,kryo570 -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 09/13] dt-bindings: arm: cpus: Document Kryo 475 CPUs 2026-08-24 15:01 ` [PATCH v6 09/13] dt-bindings: arm: cpus: Document Kryo 475 CPUs Sreeshankar K @ 2026-08-28 9:58 ` Krzysztof Kozlowski 0 siblings, 0 replies; 24+ messages in thread From: Krzysztof Kozlowski @ 2026-08-28 9:58 UTC (permalink / raw) To: Sreeshankar K Cc: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh, bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm On Mon, Aug 24, 2026 at 03:01:52PM +0000, Sreeshankar K wrote: > Document Kryo 475 CPUs found in Qualcomm SM7250 SoC. > > Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> > --- > Documentation/devicetree/bindings/arm/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6 10/13] dt-bindings: firmware: qcom,scm: Document SM7250 SCM 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (8 preceding siblings ...) 2026-08-24 15:01 ` [PATCH v6 09/13] dt-bindings: arm: cpus: Document Kryo 475 CPUs Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 11/13] dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC Sreeshankar K ` (4 subsequent siblings) 14 siblings, 0 replies; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K, Krzysztof Kozlowski Document the SCM compatible for Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 037d4ad8f..0cbdb3b2f 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -74,6 +74,7 @@ properties: - qcom,scm-sm6350 - qcom,scm-sm6375 - qcom,scm-sm7150 + - qcom,scm-sm7250 - qcom,scm-sm8150 - qcom,scm-sm8250 - qcom,scm-sm8350 -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v6 11/13] dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (9 preceding siblings ...) 2026-08-24 15:01 ` [PATCH v6 10/13] dt-bindings: firmware: qcom,scm: Document SM7250 SCM Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-28 9:58 ` Krzysztof Kozlowski 2026-08-24 15:01 ` [PATCH v6 12/13] dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware Sreeshankar K ` (3 subsequent siblings) 14 siblings, 1 reply; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K Document the PDC block on the SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> --- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index 8162a49d4..c30b88589 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -50,6 +50,7 @@ properties: - qcom,sdx75-pdc - qcom,sm4450-pdc - qcom,sm6350-pdc + - qcom,sm7250-pdc - qcom,sm8150-pdc - qcom,sm8250-pdc - qcom,sm8350-pdc -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 11/13] dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC 2026-08-24 15:01 ` [PATCH v6 11/13] dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC Sreeshankar K @ 2026-08-28 9:58 ` Krzysztof Kozlowski 0 siblings, 0 replies; 24+ messages in thread From: Krzysztof Kozlowski @ 2026-08-28 9:58 UTC (permalink / raw) To: Sreeshankar K Cc: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh, bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm On Mon, Aug 24, 2026 at 03:01:54PM +0000, Sreeshankar K wrote: > Document the PDC block on the SM7250 SoC. > > Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> > --- > .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + > 1 file changed, 1 insertion(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6 12/13] dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (10 preceding siblings ...) 2026-08-24 15:01 ` [PATCH v6 11/13] dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-28 9:58 ` Krzysztof Kozlowski 2026-08-24 15:01 ` [PATCH v6 13/13] arm64: dts: qcom: Add SM7250 devicetree file Sreeshankar K ` (2 subsequent siblings) 14 siblings, 1 reply; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K Document the cpufreq hardware on the SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 98eb36bff..2dc2c265c 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -29,6 +29,7 @@ properties: - qcom,sdm845-cpufreq-hw - qcom,sm6115-cpufreq-hw - qcom,sm6350-cpufreq-hw + - qcom,sm7250-cpufreq-hw - qcom,sm8150-cpufreq-hw - const: qcom,cpufreq-hw -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 12/13] dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware 2026-08-24 15:01 ` [PATCH v6 12/13] dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware Sreeshankar K @ 2026-08-28 9:58 ` Krzysztof Kozlowski 0 siblings, 0 replies; 24+ messages in thread From: Krzysztof Kozlowski @ 2026-08-28 9:58 UTC (permalink / raw) To: Sreeshankar K Cc: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh, bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm On Mon, Aug 24, 2026 at 03:01:55PM +0000, Sreeshankar K wrote: > Document the cpufreq hardware on the SM7250 SoC. > > Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org> > --- > Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 + > 1 file changed, 1 insertion(+) Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v6 13/13] arm64: dts: qcom: Add SM7250 devicetree file 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (11 preceding siblings ...) 2026-08-24 15:01 ` [PATCH v6 12/13] dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware Sreeshankar K @ 2026-08-24 15:01 ` Sreeshankar K 2026-08-28 9:56 ` [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Krzysztof Kozlowski 2026-09-01 2:09 ` (subset) " Bjorn Andersson 14 siblings, 0 replies; 24+ messages in thread From: Sreeshankar K @ 2026-08-24 15:01 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm, Sreeshankar K Add base devicetree file for SM7250 SoC. This file adds the basic nodes like cpu, psci and other required configuration for booting up to the serial console. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> --- arch/arm64/boot/dts/qcom/sm7250.dtsi | 771 +++++++++++++++++++++++++++ 1 file changed, 771 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm7250.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm7250.dtsi b/arch/arm64/boot/dts/qcom/sm7250.dtsi new file mode 100644 index 000000000..48480e685 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7250.dtsi @@ -0,0 +1,771 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Sreeshankar K <sreeshankar0910@gmail.com> + */ + +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm7250-gcc.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom,rpmhpd.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo475"; + reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&l2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&cpu_pd0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; + next-level-cache = <&l3_0>; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-size = <0x200000>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo475"; + reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&l2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&cpu_pd1>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + l2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo475"; + reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&l2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&cpu_pd2>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + l2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo475"; + reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&l2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&cpu_pd3>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + l2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo475"; + reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&l2_400>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&cpu_pd4>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + l2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo475"; + reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&l2_500>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&cpu_pd5>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + l2_500: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo475"; + reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <341>; + next-level-cache = <&l2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&cpu_pd6>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + l2_600: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo475"; + reg = <0x0 0x700>; + clocks = <&cpufreq_hw 2>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + dynamic-power-coefficient = <375>; + next-level-cache = <&l2_700>; + qcom,freq-domain = <&cpufreq_hw 2>; + power-domains = <&cpu_pd7>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + l2_700: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core6 { + cpu = <&cpu6>; + }; + }; + + cluster2 { + core7 { + cpu = <&cpu7>; + }; + }; + }; + + domain-idle-states { + cluster_sleep_pc: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + cluster_sleep_cx: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41001244>; + entry-latency-us = <3638>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + }; + + cluster_sleep_aoss: cluster-sleep-2 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b244>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9826>; + }; + }; + + idle-states { + entry-method = "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + local-timer-stop; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm7250", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0>, + <&little_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&big_cpu_sleep_0>, + <&big_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&big_cpu_sleep_0>, + <&big_cpu_sleep_1>; + }; + + cluster_pd: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_sleep_pc>, + <&cluster_sleep_cx>, + <&cluster_sleep_aoss>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: xbl-aop@80700000 { + reg = <0x0 0x80700000 0x0 0x160000>; + no-map; + }; + + cmd_db: cmd-db@80860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + + xbl_uefi_mem: xbl-uefi@80880000 { + reg = <0 0x80880000 0 0x14000>; + no-map; + }; + + smem_mem: smem@80900000 { + compatible = "qcom,smem"; + reg = <0x0 0x80900000 0x0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + removed_mem: removed@80b00000 { + reg = <0x0 0x80b00000 0x0 0x1300000>; + no-map; + }; + + camera_mem: camera@86000000 { + reg = <0x0 0x86000000 0x0 0x500000>; + no-map; + }; + + npu_mem: npu@86500000 { + reg = <0x0 0x86500000 0x0 0x500000>; + no-map; + }; + + video_mem: video@86a00000 { + reg = <0x0 0x86a00000 0x0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp@87400000 { + reg = <0x0 0x87400000 0x0 0x1e00000>; + no-map; + }; + + adsp_mem: adsp@89200000 { + reg = <0x0 0x89200000 0x0 0x2800000>; + no-map; + }; + + wlan_fw_mem: wlan-fw@8ba00000 { + reg = <0x0 0x8ba00000 0x0 0x200000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@8bc00000 { + reg = <0x0 0x8bc00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8bc10000 { + reg = <0x0 0x8bc10000 0x0 0x5400>; + no-map; + }; + + gpu_mem: gpu@8bc15400 { + reg = <0x0 0x8bc15400 0x0 0x2000>; + no-map; + }; + + modem_wlan_mem: modem-wlan@8c000000 { + reg = <0x0 0x8c000000 0x0 0xf800000>; + no-map; + }; + + cdsp_sec_mem: cdsp-sec@9f400000 { + reg = <0x0 0x9f400000 0x0 0xc00000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,sm7250-gcc"; + reg = <0x0 0x00100000 0x0 0x1f0000>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_CX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_id_1: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart2: serial@988000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm7250-pdc", "qcom,pdc"; + reg = <0 0xb220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges = <0 480 42>, + <42 612 28>, + <70 63 1>, + <71 640 15>, + <86 522 52>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x0001100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x0100000>, + <0x0 0x0e700000 0x0 0x00a0000>, + <0x0 0x0c40a000 0x0 0x0026000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + label = "apps_rsc"; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, + <WAKE_TCS 3>, <CONTROL_TCS 1>; + power-domains = <&cluster_pd>; + + rpmhcc: clock-controller { + compatible = "qcom,sm7250-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sm7250-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,sm7250-cpufreq-hw", "qcom,cpufreq-hw"; + reg = <0 0x18323000 0 0x1000>, + <0 0x18325800 0 0x1000>, + <0 0x18327800 0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x0 0x17c20000 0x0 0x1000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; + }; +}; -- 2.43.0 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (12 preceding siblings ...) 2026-08-24 15:01 ` [PATCH v6 13/13] arm64: dts: qcom: Add SM7250 devicetree file Sreeshankar K @ 2026-08-28 9:56 ` Krzysztof Kozlowski 2026-08-28 10:14 ` Sreeshankar K 2026-09-01 2:09 ` (subset) " Bjorn Andersson 14 siblings, 1 reply; 24+ messages in thread From: Krzysztof Kozlowski @ 2026-08-28 9:56 UTC (permalink / raw) To: Sreeshankar K Cc: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh, bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm On Mon, Aug 24, 2026 at 03:01:43PM +0000, Sreeshankar K wrote: > This patchset introduces foundational upstream support for the Qualcomm SM7250 > SoC (internally codenamed Lito). > > SM7250 is an ARMv8.2-A platform manufactured on a 7nm process, featuring an > octa-core Kryo 475 CPU configuration (1x Prime Cortex-A76, 1x Gold Cortex-A76, > and 6x Silver Cortex-A55) and Adreno 620 GPU. > > This patchset is organized as follows: > > Document relevant device tree bindings (SoC ID, Kryo 475 CPUs, SCM, PDC, > RPMh clocks/power domains, GCC and cpufreq hardware). > > Add driver support for SM7250 in socinfo, rpmh-clk, rpmhpd, and GCC. > > Add the base SoC DTSI (sm7250.dtsi) defining the cpus, PSCI, > interrupt controllers, clock providers, power domains, and reserved memory. > > Dependencies: > This patchset depends on the following patch: > > [PATCH] dt-bindings: clock: qcom,sm6375-gcc: Merge SM7150 into SM6375 > Link: https://lore.kernel.org/linux-arm-msm/20260817082457.64797-2-krzysztof.kozlowski@oss.qualcomm.com/T/#t > > [PATCH v5] Link: https://lore.kernel.org/linux-arm-msm/20260824130437.2771-1-sreeshankar0910@gmail.com/T/#t Please keep the previous changelogs and links. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC 2026-08-28 9:56 ` [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Krzysztof Kozlowski @ 2026-08-28 10:14 ` Sreeshankar K 0 siblings, 0 replies; 24+ messages in thread From: Sreeshankar K @ 2026-08-28 10:14 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: robh, krzk+dt, conor+dt, andersson, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh, bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm On Fri, 28 Aug 2026 at 15:26, Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On Mon, Aug 24, 2026 at 03:01:43PM +0000, Sreeshankar K wrote: > > This patchset introduces foundational upstream support for the Qualcomm SM7250 > > SoC (internally codenamed Lito). > > > > SM7250 is an ARMv8.2-A platform manufactured on a 7nm process, featuring an > > octa-core Kryo 475 CPU configuration (1x Prime Cortex-A76, 1x Gold Cortex-A76, > > and 6x Silver Cortex-A55) and Adreno 620 GPU. > > > > This patchset is organized as follows: > > > Document relevant device tree bindings (SoC ID, Kryo 475 CPUs, SCM, PDC, > > RPMh clocks/power domains, GCC and cpufreq hardware). > > > Add driver support for SM7250 in socinfo, rpmh-clk, rpmhpd, and GCC. > > > Add the base SoC DTSI (sm7250.dtsi) defining the cpus, PSCI, > > interrupt controllers, clock providers, power domains, and reserved memory. > > > > Dependencies: > > This patchset depends on the following patch: > > > [PATCH] dt-bindings: clock: qcom,sm6375-gcc: Merge SM7150 into SM6375 > > Link: https://lore.kernel.org/linux-arm-msm/20260817082457.64797-2-krzysztof.kozlowski@oss.qualcomm.com/T/#t > > > > [PATCH v5] Link: https://lore.kernel.org/linux-arm-msm/20260824130437.2771-1-sreeshankar0910@gmail.com/T/#t > > Please keep the previous changelogs and links. > > Best regards, > Krzysztof > I will include changelogs and links of all previous revisions in future revision. Thanks, Sreeshankar K ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: (subset) [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K ` (13 preceding siblings ...) 2026-08-28 9:56 ` [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Krzysztof Kozlowski @ 2026-09-01 2:09 ` Bjorn Andersson 2026-09-01 6:29 ` Sreeshankar K 14 siblings, 1 reply; 24+ messages in thread From: Bjorn Andersson @ 2026-09-01 2:09 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh, Sreeshankar K Cc: bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm On Mon, 24 Aug 2026 15:01:43 +0000, Sreeshankar K wrote: > This patchset introduces foundational upstream support for the Qualcomm SM7250 > SoC (internally codenamed Lito). > > SM7250 is an ARMv8.2-A platform manufactured on a 7nm process, featuring an > octa-core Kryo 475 CPU configuration (1x Prime Cortex-A76, 1x Gold Cortex-A76, > and 6x Silver Cortex-A55) and Adreno 620 GPU. > > [...] Applied, thanks! [09/13] dt-bindings: arm: cpus: Document Kryo 475 CPUs commit: 1c8fe8863780705aba77893fade65f728e82b67a Best regards, -- Bjorn Andersson <andersson@kernel.org> ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: (subset) [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC 2026-09-01 2:09 ` (subset) " Bjorn Andersson @ 2026-09-01 6:29 ` Sreeshankar K 0 siblings, 0 replies; 24+ messages in thread From: Sreeshankar K @ 2026-09-01 6:29 UTC (permalink / raw) To: Bjorn Andersson Cc: robh, krzk+dt, conor+dt, mturquette, sboyd, rafael, viresh.kumar, konradybcio, tglx, ulfh, bmasney, radu, abel.vesa, lpieralisi, taniya.das, danila, davidwronek, mani, robimarko, linux, devicetree, linux-kernel, linux-arm-msm, linux-clk, linux-pm On Tue, 1 Sept 2026 at 07:39, Bjorn Andersson <andersson@kernel.org> wrote: > > > On Mon, 24 Aug 2026 15:01:43 +0000, Sreeshankar K wrote: > > This patchset introduces foundational upstream support for the Qualcomm SM7250 > > SoC (internally codenamed Lito). > > > > SM7250 is an ARMv8.2-A platform manufactured on a 7nm process, featuring an > > octa-core Kryo 475 CPU configuration (1x Prime Cortex-A76, 1x Gold Cortex-A76, > > and 6x Silver Cortex-A55) and Adreno 620 GPU. > > > > [...] > > Applied, thanks! > > [09/13] dt-bindings: arm: cpus: Document Kryo 475 CPUs > commit: 1c8fe8863780705aba77893fade65f728e82b67a > > Best regards, > -- > Bjorn Andersson <andersson@kernel.org> Thanks, Sreeshankar K ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2026-09-01 6:35 UTC | newest] Thread overview: 24+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-08-24 15:01 [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 01/13] dt-bindings: arm: qcom,ids: Add SoC ID for SM7250 Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 02/13] soc: qcom: socinfo: Add SM7250 SoC ID Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 03/13] dt-bindings: clock: Add SM7250 global clock controller Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 Sreeshankar K 2026-08-31 23:26 ` Bjorn Andersson 2026-09-01 6:35 ` Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 05/13] dt-bindings: clock: qcom,rpmhcc: Document RPMHCC compatible " Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 06/13] clk: qcom: rpmh: Add SM7250 rpmh clocks Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 07/13] dt-bindings: power: qcom,rpmhpd: Document RPMh power domain for SM7250 Sreeshankar K 2026-08-28 9:57 ` Krzysztof Kozlowski 2026-08-24 15:01 ` [PATCH v6 08/13] pmdomain: qcom: rpmhpd: Add RPMh power domains " Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 09/13] dt-bindings: arm: cpus: Document Kryo 475 CPUs Sreeshankar K 2026-08-28 9:58 ` Krzysztof Kozlowski 2026-08-24 15:01 ` [PATCH v6 10/13] dt-bindings: firmware: qcom,scm: Document SM7250 SCM Sreeshankar K 2026-08-24 15:01 ` [PATCH v6 11/13] dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC Sreeshankar K 2026-08-28 9:58 ` Krzysztof Kozlowski 2026-08-24 15:01 ` [PATCH v6 12/13] dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware Sreeshankar K 2026-08-28 9:58 ` Krzysztof Kozlowski 2026-08-24 15:01 ` [PATCH v6 13/13] arm64: dts: qcom: Add SM7250 devicetree file Sreeshankar K 2026-08-28 9:56 ` [PATCH v6 00/13] Add initial support for Qualcomm SM7250 SoC Krzysztof Kozlowski 2026-08-28 10:14 ` Sreeshankar K 2026-09-01 2:09 ` (subset) " Bjorn Andersson 2026-09-01 6:29 ` Sreeshankar K
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