Re: [PATCH 2/4] clk: qcom: gcc: Add support for Global Clock controller found on MSM8940

[barnabas.czeman@mainlining.org]

On 2025-11-17 15:17, Konrad Dybcio wrote:
> On 11/17/25 3:02 PM, barnabas.czeman@mainlining.org wrote:
>> On 2025-11-17 13:17, Konrad Dybcio wrote:
>>> On 11/17/25 9:51 AM, Barnabás Czémán wrote:
>>>> 
>>>> 
>>>> On 17 November 2025 09:03:53 CET, Taniya Das 
>>>> <taniya.das@oss.qualcomm.com> wrote:
>>>>> 
>>>>> 
>>>>> On 11/17/2025 3:05 AM, Barnabás Czémán wrote:
>>>>>> 
>>>>>> +static struct clk_branch gcc_ipa_tbu_clk = {
>>>>>> +    .halt_reg = 0x120a0,
>>>>>> +    .halt_check = BRANCH_VOTED,
>>>>>> +    .clkr = {
>>>>>> +        .enable_reg = 0x4500c,
>>>>>> +        .enable_mask = BIT(16),
>>>>>> +        .hw.init = &(struct clk_init_data){
>>>>>> +            .name = "gcc_ipa_tbu_clk",
>>>>>> +            .ops = &clk_branch2_ops,
>>>>>> +        },
>>>>>> +    },
>>>>>> +};
>>>>>> +
>>>>> 
>>>>> Is the TBU clock used on 8940 by a SMMU driver?
>>>> As far as I know no MSM8940 is using same smmu driver and bindings 
>>>> like MSM8937.
>>> 
>>> On msm8939, the clock needed to be turned on for the GPU SMMU
>> I have not got any qcom-iommu issues on 8940 but i think it could come 
>> when i try to add ipa2 driver
>> for the SoC until i do not know where to check it.
> 
> I can't find a definitive answer, but it's most certainly going to be
> necessary to turn it on
> 
> Konrad

I have enabled ipa2-lite for 8940 at downstream and it can cause gpu to 
crash.
I have tried to add TBU clock for apps_iommu but it not fixing the 
issue.

Here are the iommu changes based on 8937 apps_iommu node:
+&apps_iommu {
+       clocks = <&gcc GCC_SMMU_CFG_CLK>,
+                <&gcc GCC_APSS_TCU_CLK>,
+                <&gcc MSM8940_GCC_IPA_TBU_CLK>;
+       clock-names = "iface",
+                     "bus",
+                     "tbu";
+
+       /* IPA */
+       iommu-ctx@18000 {
+               compatible = "qcom,msm-iommu-v1-ns";
+               reg = <0x18000 0x1000>;
+               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+       };
+};
+