* [PATCH 01/29] crypto: talitos/hash - Use CRYPTO_AHASH_BLOCK_ONLY API
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-29 11:25 ` Christophe Leroy (CS GROUP)
2026-05-28 9:08 ` [PATCH 02/29] crypto: talitos - Move driver into dedicated directory Paul Louvel
` (27 subsequent siblings)
28 siblings, 1 reply; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
The hash implementation maintained a software buffer to accumulate
partial blocks across update() calls, copying data to/from scatterlists
with sg_copy_to_buffer()/sg_pcopy_to_buffer() and chaining in a virtual
scatterlist entry. This is unnecessary now with
CRYPTO_AHASH_ALG_BLOCK_ONLY flag.
Remove unnecessary fields in the request and export structure. On
completion, pass any remaining tail bytes back via
ahash_request_complete() so that the core re-submits them with the next
request.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos.c | 149 ++++++++++++++++++-----------------------------
1 file changed, 57 insertions(+), 92 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 584508963241..3610d9f6d5ea 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -941,25 +941,18 @@ struct talitos_ctx {
struct talitos_ahash_req_ctx {
u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
unsigned int hw_context_size;
- u8 buf[2][HASH_MAX_BLOCK_SIZE];
- int buf_idx;
unsigned int swinit;
unsigned int first_request;
unsigned int last_request;
unsigned int to_hash_later;
- unsigned int nbuf;
- struct scatterlist bufsl[2];
- struct scatterlist *psrc;
};
struct talitos_export_state {
u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
- u8 buf[HASH_MAX_BLOCK_SIZE];
unsigned int swinit;
unsigned int first_request;
unsigned int last_request;
unsigned int to_hash_later;
- unsigned int nbuf;
};
static int aead_setkey(struct crypto_aead *authenc,
@@ -1826,14 +1819,8 @@ static void ahash_done(struct device *dev,
struct talitos_edesc *next;
if (is_sec1) {
- if (!req_ctx->last_request && req_ctx->to_hash_later) {
- /* Position any partial block for next update/final/finup */
- req_ctx->buf_idx = (req_ctx->buf_idx + 1) & 1;
- req_ctx->nbuf = req_ctx->to_hash_later;
- }
-
free_edesc_list_from(areq, edesc);
- ahash_request_complete(areq, err);
+ ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
} else {
next = edesc->next_desc;
@@ -1851,14 +1838,9 @@ static void ahash_done(struct device *dev,
return;
}
out:
- if (!req_ctx->last_request && req_ctx->to_hash_later) {
- /* Position any partial block for next update/final/finup */
- req_ctx->buf_idx = (req_ctx->buf_idx + 1) & 1;
- req_ctx->nbuf = req_ctx->to_hash_later;
- }
if (err && next)
free_edesc_list_from(areq, next);
- ahash_request_complete(areq, err);
+ ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
}
}
@@ -1978,7 +1960,7 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
size_t offset = 0;
do {
- src = scatterwalk_ffwd(tmp, req_ctx->psrc, offset);
+ src = scatterwalk_ffwd(tmp, areq->src, offset);
to_hash_this_desc =
min(nbytes, ALIGN_DOWN(desc_max, blocksize));
@@ -1991,8 +1973,7 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
return edesc;
}
- edesc->src =
- scatterwalk_ffwd(edesc->bufsl, req_ctx->psrc, offset);
+ edesc->src = scatterwalk_ffwd(edesc->bufsl, areq->src, offset);
edesc->desc.hdr = ctx->desc_hdr_template;
edesc->first = offset == 0;
edesc->last = nbytes - to_hash_this_desc == 0;
@@ -2045,62 +2026,17 @@ static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
bool is_sec1 = has_ftr_sec1(dev_get_drvdata(ctx->dev));
unsigned int nbytes_to_hash;
unsigned int to_hash_later;
- unsigned int nsg;
- int nents;
struct device *dev = ctx->dev;
- u8 *ctx_buf = req_ctx->buf[req_ctx->buf_idx];
int ret;
- if (!req_ctx->last_request && (nbytes + req_ctx->nbuf <= blocksize)) {
- /* Buffer up to one whole block */
- nents = sg_nents_for_len(areq->src, nbytes);
- if (nents < 0) {
- dev_err(dev, "Invalid number of src SG.\n");
- return nents;
- }
- sg_copy_to_buffer(areq->src, nents,
- ctx_buf + req_ctx->nbuf, nbytes);
- req_ctx->nbuf += nbytes;
- return 0;
- }
-
- /* At least (blocksize + 1) bytes are available to hash */
- nbytes_to_hash = nbytes + req_ctx->nbuf;
- to_hash_later = nbytes_to_hash & (blocksize - 1);
+ nbytes_to_hash = ALIGN_DOWN(nbytes, blocksize);
+ to_hash_later = nbytes - nbytes_to_hash;
- if (req_ctx->last_request)
+ if (req_ctx->last_request) {
+ nbytes_to_hash = nbytes;
to_hash_later = 0;
- else if (to_hash_later)
- /* There is a partial block. Hash the full block(s) now */
- nbytes_to_hash -= to_hash_later;
- else {
- /* Keep one block buffered */
- nbytes_to_hash -= blocksize;
- to_hash_later = blocksize;
- }
-
- /* Chain in any previously buffered data */
- if (req_ctx->nbuf) {
- nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
- sg_init_table(req_ctx->bufsl, nsg);
- sg_set_buf(req_ctx->bufsl, ctx_buf, req_ctx->nbuf);
- if (nsg > 1)
- sg_chain(req_ctx->bufsl, 2, areq->src);
- req_ctx->psrc = req_ctx->bufsl;
- } else
- req_ctx->psrc = areq->src;
-
- if (to_hash_later) {
- nents = sg_nents_for_len(areq->src, nbytes);
- if (nents < 0) {
- dev_err(dev, "Invalid number of src SG.\n");
- return nents;
- }
- sg_pcopy_to_buffer(areq->src, nents,
- req_ctx->buf[(req_ctx->buf_idx + 1) & 1],
- to_hash_later,
- nbytes - to_hash_later);
}
+
req_ctx->to_hash_later = to_hash_later;
edesc = ahash_process_req_prepare(areq, nbytes_to_hash, blocksize,
@@ -2125,8 +2061,6 @@ static int ahash_init(struct ahash_request *areq)
dma_addr_t dma;
/* Initialize the context */
- req_ctx->buf_idx = 0;
- req_ctx->nbuf = 0;
req_ctx->first_request = 1;
req_ctx->swinit = 0; /* assume h/w init of context */
size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
@@ -2223,12 +2157,10 @@ static int ahash_export(struct ahash_request *areq, void *out)
memcpy(export->hw_context, req_ctx->hw_context,
req_ctx->hw_context_size);
- memcpy(export->buf, req_ctx->buf[req_ctx->buf_idx], req_ctx->nbuf);
export->swinit = req_ctx->swinit;
export->first_request = req_ctx->first_request;
export->last_request = req_ctx->last_request;
export->to_hash_later = req_ctx->to_hash_later;
- export->nbuf = req_ctx->nbuf;
return 0;
}
@@ -2249,12 +2181,10 @@ static int ahash_import(struct ahash_request *areq, const void *in)
: TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
req_ctx->hw_context_size = size;
memcpy(req_ctx->hw_context, export->hw_context, size);
- memcpy(req_ctx->buf[0], export->buf, export->nbuf);
req_ctx->swinit = export->swinit;
req_ctx->first_request = export->first_request;
req_ctx->last_request = export->last_request;
req_ctx->to_hash_later = export->to_hash_later;
- req_ctx->nbuf = export->nbuf;
dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
DMA_TO_DEVICE);
@@ -2932,8 +2862,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "md5",
.cra_driver_name = "md5-talitos",
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -2948,8 +2881,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "sha1",
.cra_driver_name = "sha1-talitos",
.cra_blocksize = SHA1_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -2964,8 +2900,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "sha224",
.cra_driver_name = "sha224-talitos",
.cra_blocksize = SHA224_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -2980,8 +2919,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "sha256",
.cra_driver_name = "sha256-talitos",
.cra_blocksize = SHA256_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -2996,8 +2938,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "sha384",
.cra_driver_name = "sha384-talitos",
.cra_blocksize = SHA384_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3012,8 +2957,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "sha512",
.cra_driver_name = "sha512-talitos",
.cra_blocksize = SHA512_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3028,8 +2976,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(md5)",
.cra_driver_name = "hmac-md5-talitos",
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3044,8 +2995,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(sha1)",
.cra_driver_name = "hmac-sha1-talitos",
.cra_blocksize = SHA1_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3060,8 +3014,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(sha224)",
.cra_driver_name = "hmac-sha224-talitos",
.cra_blocksize = SHA224_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3076,8 +3033,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(sha256)",
.cra_driver_name = "hmac-sha256-talitos",
.cra_blocksize = SHA256_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3092,8 +3052,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(sha384)",
.cra_driver_name = "hmac-sha384-talitos",
.cra_blocksize = SHA384_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3108,8 +3071,11 @@ static struct talitos_alg_template driver_algs[] = {
.cra_name = "hmac(sha512)",
.cra_driver_name = "hmac-sha512-talitos",
.cra_blocksize = SHA512_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -3181,7 +3147,6 @@ static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
algt.alg.hash);
ctx->keylen = 0;
- crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
sizeof(struct talitos_ahash_req_ctx));
return talitos_init_common(ctx, talitos_alg);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 01/29] crypto: talitos/hash - Use CRYPTO_AHASH_BLOCK_ONLY API
2026-05-28 9:08 ` [PATCH 01/29] crypto: talitos/hash - Use CRYPTO_AHASH_BLOCK_ONLY API Paul Louvel
@ 2026-05-29 11:25 ` Christophe Leroy (CS GROUP)
0 siblings, 0 replies; 36+ messages in thread
From: Christophe Leroy (CS GROUP) @ 2026-05-29 11:25 UTC (permalink / raw)
To: Paul Louvel, Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, linux-crypto, linux-kernel
Le 28/05/2026 à 11:08, Paul Louvel a écrit :
> The hash implementation maintained a software buffer to accumulate
> partial blocks across update() calls, copying data to/from scatterlists
> with sg_copy_to_buffer()/sg_pcopy_to_buffer() and chaining in a virtual
> scatterlist entry. This is unnecessary now with
> CRYPTO_AHASH_ALG_BLOCK_ONLY flag.
>
> Remove unnecessary fields in the request and export structure. On
> completion, pass any remaining tail bytes back via
> ahash_request_complete() so that the core re-submits them with the next
> request.
>
> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
> ---
> drivers/crypto/talitos.c | 149 ++++++++++++++++++-----------------------------
> 1 file changed, 57 insertions(+), 92 deletions(-)
>
> diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
> index 584508963241..3610d9f6d5ea 100644
> --- a/drivers/crypto/talitos.c
> +++ b/drivers/crypto/talitos.c
> @@ -941,25 +941,18 @@ struct talitos_ctx {
> struct talitos_ahash_req_ctx {
> u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
> unsigned int hw_context_size;
> - u8 buf[2][HASH_MAX_BLOCK_SIZE];
> - int buf_idx;
> unsigned int swinit;
> unsigned int first_request;
> unsigned int last_request;
> unsigned int to_hash_later;
> - unsigned int nbuf;
> - struct scatterlist bufsl[2];
> - struct scatterlist *psrc;
> };
>
> struct talitos_export_state {
> u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
> - u8 buf[HASH_MAX_BLOCK_SIZE];
> unsigned int swinit;
> unsigned int first_request;
> unsigned int last_request;
> unsigned int to_hash_later;
> - unsigned int nbuf;
> };
>
> static int aead_setkey(struct crypto_aead *authenc,
> @@ -1826,14 +1819,8 @@ static void ahash_done(struct device *dev,
> struct talitos_edesc *next;
>
> if (is_sec1) {
> - if (!req_ctx->last_request && req_ctx->to_hash_later) {
> - /* Position any partial block for next update/final/finup */
> - req_ctx->buf_idx = (req_ctx->buf_idx + 1) & 1;
> - req_ctx->nbuf = req_ctx->to_hash_later;
> - }
> -
> free_edesc_list_from(areq, edesc);
> - ahash_request_complete(areq, err);
> + ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
> } else {
> next = edesc->next_desc;
>
> @@ -1851,14 +1838,9 @@ static void ahash_done(struct device *dev,
> return;
> }
> out:
> - if (!req_ctx->last_request && req_ctx->to_hash_later) {
> - /* Position any partial block for next update/final/finup */
> - req_ctx->buf_idx = (req_ctx->buf_idx + 1) & 1;
> - req_ctx->nbuf = req_ctx->to_hash_later;
> - }
> if (err && next)
> free_edesc_list_from(areq, next);
> - ahash_request_complete(areq, err);
> + ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
> }
> }
>
> @@ -1978,7 +1960,7 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
> size_t offset = 0;
>
> do {
> - src = scatterwalk_ffwd(tmp, req_ctx->psrc, offset);
> + src = scatterwalk_ffwd(tmp, areq->src, offset);
>
> to_hash_this_desc =
> min(nbytes, ALIGN_DOWN(desc_max, blocksize));
> @@ -1991,8 +1973,7 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
> return edesc;
> }
>
> - edesc->src =
> - scatterwalk_ffwd(edesc->bufsl, req_ctx->psrc, offset);
> + edesc->src = scatterwalk_ffwd(edesc->bufsl, areq->src, offset);
> edesc->desc.hdr = ctx->desc_hdr_template;
> edesc->first = offset == 0;
> edesc->last = nbytes - to_hash_this_desc == 0;
> @@ -2045,62 +2026,17 @@ static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
> bool is_sec1 = has_ftr_sec1(dev_get_drvdata(ctx->dev));
> unsigned int nbytes_to_hash;
> unsigned int to_hash_later;
> - unsigned int nsg;
> - int nents;
> struct device *dev = ctx->dev;
> - u8 *ctx_buf = req_ctx->buf[req_ctx->buf_idx];
> int ret;
>
> - if (!req_ctx->last_request && (nbytes + req_ctx->nbuf <= blocksize)) {
> - /* Buffer up to one whole block */
> - nents = sg_nents_for_len(areq->src, nbytes);
> - if (nents < 0) {
> - dev_err(dev, "Invalid number of src SG.\n");
> - return nents;
> - }
> - sg_copy_to_buffer(areq->src, nents,
> - ctx_buf + req_ctx->nbuf, nbytes);
> - req_ctx->nbuf += nbytes;
> - return 0;
> - }
> -
> - /* At least (blocksize + 1) bytes are available to hash */
> - nbytes_to_hash = nbytes + req_ctx->nbuf;
> - to_hash_later = nbytes_to_hash & (blocksize - 1);
> + nbytes_to_hash = ALIGN_DOWN(nbytes, blocksize);
> + to_hash_later = nbytes - nbytes_to_hash;
>
> - if (req_ctx->last_request)
> + if (req_ctx->last_request) {
> + nbytes_to_hash = nbytes;
> to_hash_later = 0;
> - else if (to_hash_later)
> - /* There is a partial block. Hash the full block(s) now */
> - nbytes_to_hash -= to_hash_later;
> - else {
> - /* Keep one block buffered */
> - nbytes_to_hash -= blocksize;
> - to_hash_later = blocksize;
> - }
> -
> - /* Chain in any previously buffered data */
> - if (req_ctx->nbuf) {
> - nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
> - sg_init_table(req_ctx->bufsl, nsg);
> - sg_set_buf(req_ctx->bufsl, ctx_buf, req_ctx->nbuf);
> - if (nsg > 1)
> - sg_chain(req_ctx->bufsl, 2, areq->src);
> - req_ctx->psrc = req_ctx->bufsl;
> - } else
> - req_ctx->psrc = areq->src;
> -
> - if (to_hash_later) {
> - nents = sg_nents_for_len(areq->src, nbytes);
> - if (nents < 0) {
> - dev_err(dev, "Invalid number of src SG.\n");
> - return nents;
> - }
> - sg_pcopy_to_buffer(areq->src, nents,
> - req_ctx->buf[(req_ctx->buf_idx + 1) & 1],
> - to_hash_later,
> - nbytes - to_hash_later);
> }
> +
> req_ctx->to_hash_later = to_hash_later;
>
> edesc = ahash_process_req_prepare(areq, nbytes_to_hash, blocksize,
> @@ -2125,8 +2061,6 @@ static int ahash_init(struct ahash_request *areq)
> dma_addr_t dma;
>
> /* Initialize the context */
> - req_ctx->buf_idx = 0;
> - req_ctx->nbuf = 0;
> req_ctx->first_request = 1;
> req_ctx->swinit = 0; /* assume h/w init of context */
> size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
> @@ -2223,12 +2157,10 @@ static int ahash_export(struct ahash_request *areq, void *out)
>
> memcpy(export->hw_context, req_ctx->hw_context,
> req_ctx->hw_context_size);
> - memcpy(export->buf, req_ctx->buf[req_ctx->buf_idx], req_ctx->nbuf);
> export->swinit = req_ctx->swinit;
> export->first_request = req_ctx->first_request;
> export->last_request = req_ctx->last_request;
> export->to_hash_later = req_ctx->to_hash_later;
> - export->nbuf = req_ctx->nbuf;
>
> return 0;
> }
> @@ -2249,12 +2181,10 @@ static int ahash_import(struct ahash_request *areq, const void *in)
> : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
> req_ctx->hw_context_size = size;
> memcpy(req_ctx->hw_context, export->hw_context, size);
> - memcpy(req_ctx->buf[0], export->buf, export->nbuf);
> req_ctx->swinit = export->swinit;
> req_ctx->first_request = export->first_request;
> req_ctx->last_request = export->last_request;
> req_ctx->to_hash_later = export->to_hash_later;
> - req_ctx->nbuf = export->nbuf;
>
> dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
> DMA_TO_DEVICE);
> @@ -2932,8 +2862,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "md5",
> .cra_driver_name = "md5-talitos",
> .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -2948,8 +2881,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "sha1",
> .cra_driver_name = "sha1-talitos",
> .cra_blocksize = SHA1_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -2964,8 +2900,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "sha224",
> .cra_driver_name = "sha224-talitos",
> .cra_blocksize = SHA224_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -2980,8 +2919,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "sha256",
> .cra_driver_name = "sha256-talitos",
> .cra_blocksize = SHA256_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -2996,8 +2938,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "sha384",
> .cra_driver_name = "sha384-talitos",
> .cra_blocksize = SHA384_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -3012,8 +2957,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "sha512",
> .cra_driver_name = "sha512-talitos",
> .cra_blocksize = SHA512_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -3028,8 +2976,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "hmac(md5)",
> .cra_driver_name = "hmac-md5-talitos",
> .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -3044,8 +2995,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "hmac(sha1)",
> .cra_driver_name = "hmac-sha1-talitos",
> .cra_blocksize = SHA1_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -3060,8 +3014,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "hmac(sha224)",
> .cra_driver_name = "hmac-sha224-talitos",
> .cra_blocksize = SHA224_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -3076,8 +3033,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "hmac(sha256)",
> .cra_driver_name = "hmac-sha256-talitos",
> .cra_blocksize = SHA256_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -3092,8 +3052,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "hmac(sha384)",
> .cra_driver_name = "hmac-sha384-talitos",
> .cra_blocksize = SHA384_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -3108,8 +3071,11 @@ static struct talitos_alg_template driver_algs[] = {
> .cra_name = "hmac(sha512)",
> .cra_driver_name = "hmac-sha512-talitos",
> .cra_blocksize = SHA512_BLOCK_SIZE,
> + .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
> .cra_flags = CRYPTO_ALG_ASYNC |
> - CRYPTO_ALG_ALLOCATES_MEMORY,
> + CRYPTO_ALG_ALLOCATES_MEMORY |
> + CRYPTO_AHASH_ALG_BLOCK_ONLY |
> + CRYPTO_AHASH_ALG_FINAL_NONZERO,
> }
> },
> .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
> @@ -3181,7 +3147,6 @@ static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
> algt.alg.hash);
>
> ctx->keylen = 0;
> - crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
> sizeof(struct talitos_ahash_req_ctx));
>
> return talitos_init_common(ctx, talitos_alg);
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 02/29] crypto: talitos - Move driver into dedicated directory
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
2026-05-28 9:08 ` [PATCH 01/29] crypto: talitos/hash - Use CRYPTO_AHASH_BLOCK_ONLY API Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-29 11:25 ` Christophe Leroy (CS GROUP)
2026-05-28 9:08 ` [PATCH 03/29] crypto: talitos - Add missing includes to driver header file Paul Louvel
` (26 subsequent siblings)
28 siblings, 1 reply; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Move the talitos driver files from drivers/crypto/ into
drivers/crypto/talitos/ to accommodate upcoming code
reorganization.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/Kconfig | 38 +---------------------------------
drivers/crypto/Makefile | 2 +-
drivers/crypto/talitos/Kconfig | 36 ++++++++++++++++++++++++++++++++
drivers/crypto/talitos/Makefile | 1 +
drivers/crypto/{ => talitos}/talitos.c | 0
drivers/crypto/{ => talitos}/talitos.h | 0
6 files changed, 39 insertions(+), 38 deletions(-)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index d23b58b81ca3..783b5dc42a42 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -253,43 +253,7 @@ config CRYPTO_DEV_HIFN_795X_RNG
on the HIFN 795x crypto adapters.
source "drivers/crypto/caam/Kconfig"
-
-config CRYPTO_DEV_TALITOS
- tristate "Talitos Freescale Security Engine (SEC)"
- select CRYPTO_AEAD
- select CRYPTO_AUTHENC
- select CRYPTO_SKCIPHER
- select CRYPTO_HASH
- select CRYPTO_LIB_DES
- select HW_RANDOM
- depends on FSL_SOC
- help
- Say 'Y' here to use the Freescale Security Engine (SEC)
- to offload cryptographic algorithm computation.
-
- The Freescale SEC is present on PowerQUICC 'E' processors, such
- as the MPC8349E and MPC8548E.
-
- To compile this driver as a module, choose M here: the module
- will be called talitos.
-
-config CRYPTO_DEV_TALITOS1
- bool "SEC1 (SEC 1.0 and SEC Lite 1.2)"
- depends on CRYPTO_DEV_TALITOS
- depends on PPC_8xx || PPC_82xx
- default y
- help
- Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0
- found on MPC82xx or the Freescale Security Engine (SEC Lite)
- version 1.2 found on MPC8xx
-
-config CRYPTO_DEV_TALITOS2
- bool "SEC2+ (SEC version 2.0 or upper)"
- depends on CRYPTO_DEV_TALITOS
- default y if !PPC_8xx
- help
- Say 'Y' here to use the Freescale Security Engine (SEC)
- version 2 and following as found on MPC83xx, MPC85xx, etc ...
+source "drivers/crypto/talitos/Kconfig"
config CRYPTO_DEV_PPC4XX
tristate "Driver AMCC PPC4xx crypto accelerator"
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 283bbc650b5b..a059139d4a75 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -35,7 +35,7 @@ obj-$(CONFIG_CRYPTO_DEV_SA2UL) += sa2ul.o
obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
obj-$(CONFIG_CRYPTO_DEV_SL3516) += gemini/
obj-y += stm32/
-obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
+obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos/
obj-$(CONFIG_CRYPTO_DEV_TEGRA) += tegra/
obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
diff --git a/drivers/crypto/talitos/Kconfig b/drivers/crypto/talitos/Kconfig
new file mode 100644
index 000000000000..c3470553a966
--- /dev/null
+++ b/drivers/crypto/talitos/Kconfig
@@ -0,0 +1,36 @@
+config CRYPTO_DEV_TALITOS
+ tristate "Talitos Freescale Security Engine (SEC)"
+ select CRYPTO_AEAD
+ select CRYPTO_AUTHENC
+ select CRYPTO_SKCIPHER
+ select CRYPTO_HASH
+ select CRYPTO_LIB_DES
+ select HW_RANDOM
+ depends on FSL_SOC
+ help
+ Say 'Y' here to use the Freescale Security Engine (SEC)
+ to offload cryptographic algorithm computation.
+
+ The Freescale SEC is present on PowerQUICC 'E' processors, such
+ as the MPC8349E and MPC8548E.
+
+ To compile this driver as a module, choose M here: the module
+ will be called talitos.
+
+config CRYPTO_DEV_TALITOS1
+ bool "SEC1 (SEC 1.0 and SEC Lite 1.2)"
+ depends on CRYPTO_DEV_TALITOS
+ depends on PPC_8xx || PPC_82xx
+ default y
+ help
+ Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0
+ found on MPC82xx or the Freescale Security Engine (SEC Lite)
+ version 1.2 found on MPC8xx
+
+config CRYPTO_DEV_TALITOS2
+ bool "SEC2+ (SEC version 2.0 or upper)"
+ depends on CRYPTO_DEV_TALITOS
+ default y if !PPC_8xx
+ help
+ Say 'Y' here to use the Freescale Security Engine (SEC)
+ version 2 and following as found on MPC83xx, MPC85xx, etc ...
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
new file mode 100644
index 000000000000..fcc5db5e63c2
--- /dev/null
+++ b/drivers/crypto/talitos/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos/talitos.c
similarity index 100%
rename from drivers/crypto/talitos.c
rename to drivers/crypto/talitos/talitos.c
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos/talitos.h
similarity index 100%
rename from drivers/crypto/talitos.h
rename to drivers/crypto/talitos/talitos.h
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 02/29] crypto: talitos - Move driver into dedicated directory
2026-05-28 9:08 ` [PATCH 02/29] crypto: talitos - Move driver into dedicated directory Paul Louvel
@ 2026-05-29 11:25 ` Christophe Leroy (CS GROUP)
0 siblings, 0 replies; 36+ messages in thread
From: Christophe Leroy (CS GROUP) @ 2026-05-29 11:25 UTC (permalink / raw)
To: Paul Louvel, Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, linux-crypto, linux-kernel
Le 28/05/2026 à 11:08, Paul Louvel a écrit :
> Move the talitos driver files from drivers/crypto/ into
> drivers/crypto/talitos/ to accommodate upcoming code
> reorganization.
>
> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
> ---
> drivers/crypto/Kconfig | 38 +---------------------------------
> drivers/crypto/Makefile | 2 +-
> drivers/crypto/talitos/Kconfig | 36 ++++++++++++++++++++++++++++++++
> drivers/crypto/talitos/Makefile | 1 +
> drivers/crypto/{ => talitos}/talitos.c | 0
> drivers/crypto/{ => talitos}/talitos.h | 0
> 6 files changed, 39 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index d23b58b81ca3..783b5dc42a42 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -253,43 +253,7 @@ config CRYPTO_DEV_HIFN_795X_RNG
> on the HIFN 795x crypto adapters.
>
> source "drivers/crypto/caam/Kconfig"
> -
> -config CRYPTO_DEV_TALITOS
> - tristate "Talitos Freescale Security Engine (SEC)"
> - select CRYPTO_AEAD
> - select CRYPTO_AUTHENC
> - select CRYPTO_SKCIPHER
> - select CRYPTO_HASH
> - select CRYPTO_LIB_DES
> - select HW_RANDOM
> - depends on FSL_SOC
> - help
> - Say 'Y' here to use the Freescale Security Engine (SEC)
> - to offload cryptographic algorithm computation.
> -
> - The Freescale SEC is present on PowerQUICC 'E' processors, such
> - as the MPC8349E and MPC8548E.
> -
> - To compile this driver as a module, choose M here: the module
> - will be called talitos.
> -
> -config CRYPTO_DEV_TALITOS1
> - bool "SEC1 (SEC 1.0 and SEC Lite 1.2)"
> - depends on CRYPTO_DEV_TALITOS
> - depends on PPC_8xx || PPC_82xx
> - default y
> - help
> - Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0
> - found on MPC82xx or the Freescale Security Engine (SEC Lite)
> - version 1.2 found on MPC8xx
> -
> -config CRYPTO_DEV_TALITOS2
> - bool "SEC2+ (SEC version 2.0 or upper)"
> - depends on CRYPTO_DEV_TALITOS
> - default y if !PPC_8xx
> - help
> - Say 'Y' here to use the Freescale Security Engine (SEC)
> - version 2 and following as found on MPC83xx, MPC85xx, etc ...
> +source "drivers/crypto/talitos/Kconfig"
>
> config CRYPTO_DEV_PPC4XX
> tristate "Driver AMCC PPC4xx crypto accelerator"
> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
> index 283bbc650b5b..a059139d4a75 100644
> --- a/drivers/crypto/Makefile
> +++ b/drivers/crypto/Makefile
> @@ -35,7 +35,7 @@ obj-$(CONFIG_CRYPTO_DEV_SA2UL) += sa2ul.o
> obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
> obj-$(CONFIG_CRYPTO_DEV_SL3516) += gemini/
> obj-y += stm32/
> -obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
> +obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos/
> obj-$(CONFIG_CRYPTO_DEV_TEGRA) += tegra/
> obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
> obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
> diff --git a/drivers/crypto/talitos/Kconfig b/drivers/crypto/talitos/Kconfig
> new file mode 100644
> index 000000000000..c3470553a966
> --- /dev/null
> +++ b/drivers/crypto/talitos/Kconfig
> @@ -0,0 +1,36 @@
> +config CRYPTO_DEV_TALITOS
> + tristate "Talitos Freescale Security Engine (SEC)"
> + select CRYPTO_AEAD
> + select CRYPTO_AUTHENC
> + select CRYPTO_SKCIPHER
> + select CRYPTO_HASH
> + select CRYPTO_LIB_DES
> + select HW_RANDOM
> + depends on FSL_SOC
> + help
> + Say 'Y' here to use the Freescale Security Engine (SEC)
> + to offload cryptographic algorithm computation.
> +
> + The Freescale SEC is present on PowerQUICC 'E' processors, such
> + as the MPC8349E and MPC8548E.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called talitos.
> +
> +config CRYPTO_DEV_TALITOS1
> + bool "SEC1 (SEC 1.0 and SEC Lite 1.2)"
> + depends on CRYPTO_DEV_TALITOS
> + depends on PPC_8xx || PPC_82xx
> + default y
> + help
> + Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0
> + found on MPC82xx or the Freescale Security Engine (SEC Lite)
> + version 1.2 found on MPC8xx
> +
> +config CRYPTO_DEV_TALITOS2
> + bool "SEC2+ (SEC version 2.0 or upper)"
> + depends on CRYPTO_DEV_TALITOS
> + default y if !PPC_8xx
> + help
> + Say 'Y' here to use the Freescale Security Engine (SEC)
> + version 2 and following as found on MPC83xx, MPC85xx, etc ...
> diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
> new file mode 100644
> index 000000000000..fcc5db5e63c2
> --- /dev/null
> +++ b/drivers/crypto/talitos/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
> diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos/talitos.c
> similarity index 100%
> rename from drivers/crypto/talitos.c
> rename to drivers/crypto/talitos/talitos.c
> diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos/talitos.h
> similarity index 100%
> rename from drivers/crypto/talitos.h
> rename to drivers/crypto/talitos/talitos.h
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 03/29] crypto: talitos - Add missing includes to driver header file
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
2026-05-28 9:08 ` [PATCH 01/29] crypto: talitos/hash - Use CRYPTO_AHASH_BLOCK_ONLY API Paul Louvel
2026-05-28 9:08 ` [PATCH 02/29] crypto: talitos - Move driver into dedicated directory Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-29 11:26 ` Christophe Leroy (CS GROUP)
2026-05-28 9:08 ` [PATCH 04/29] crypto: talitos/hwrng - Move into separate file Paul Louvel
` (25 subsequent siblings)
28 siblings, 1 reply; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Add explicit includes for types used by the header file to make
it self-contained and fix implicit include dependencies.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 3 ---
drivers/crypto/talitos/talitos.h | 6 ++++++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 3610d9f6d5ea..8ca587b98d92 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -15,10 +15,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
#include <linux/crypto.h>
-#include <linux/hw_random.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index d4ff8d589f46..56e36a65ddcc 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -5,6 +5,12 @@
* Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
*/
+#include <linux/device.h>
+#include <linux/hw_random.h>
+#include <linux/interrupt.h>
+#include <linux/scatterlist.h>
+#include <linux/types.h>
+
#define TALITOS_TIMEOUT 100000
#define TALITOS1_MAX_DATA_LEN 32768
#define TALITOS2_MAX_DATA_LEN 65535
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 03/29] crypto: talitos - Add missing includes to driver header file
2026-05-28 9:08 ` [PATCH 03/29] crypto: talitos - Add missing includes to driver header file Paul Louvel
@ 2026-05-29 11:26 ` Christophe Leroy (CS GROUP)
0 siblings, 0 replies; 36+ messages in thread
From: Christophe Leroy (CS GROUP) @ 2026-05-29 11:26 UTC (permalink / raw)
To: Paul Louvel, Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, linux-crypto, linux-kernel
Le 28/05/2026 à 11:08, Paul Louvel a écrit :
> Add explicit includes for types used by the header file to make
> it self-contained and fix implicit include dependencies.
>
> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
> ---
> drivers/crypto/talitos/talitos.c | 3 ---
> drivers/crypto/talitos/talitos.h | 6 ++++++
> 2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
> index 3610d9f6d5ea..8ca587b98d92 100644
> --- a/drivers/crypto/talitos/talitos.c
> +++ b/drivers/crypto/talitos/talitos.c
> @@ -15,10 +15,7 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/mod_devicetable.h>
> -#include <linux/device.h>
> -#include <linux/interrupt.h>
> #include <linux/crypto.h>
> -#include <linux/hw_random.h>
> #include <linux/of.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
> diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
> index d4ff8d589f46..56e36a65ddcc 100644
> --- a/drivers/crypto/talitos/talitos.h
> +++ b/drivers/crypto/talitos/talitos.h
> @@ -5,6 +5,12 @@
> * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
> */
>
> +#include <linux/device.h>
> +#include <linux/hw_random.h>
> +#include <linux/interrupt.h>
> +#include <linux/scatterlist.h>
> +#include <linux/types.h>
> +
> #define TALITOS_TIMEOUT 100000
> #define TALITOS1_MAX_DATA_LEN 32768
> #define TALITOS2_MAX_DATA_LEN 65535
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 04/29] crypto: talitos/hwrng - Move into separate file
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (2 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 03/29] crypto: talitos - Add missing includes to driver header file Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-29 11:26 ` Christophe Leroy (CS GROUP)
2026-05-28 9:08 ` [PATCH 05/29] crypto: talitos - Prepare crypto implementation file splitting Paul Louvel
` (24 subsequent siblings)
28 siblings, 1 reply; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Move the hardware random number generator implementation from
talitos.c into a dedicated talitos-rng.c file.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/Makefile | 2 +
drivers/crypto/talitos/talitos-rng.c | 93 ++++++++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.c | 83 --------------------------------
drivers/crypto/talitos/talitos.h | 5 ++
4 files changed, 100 insertions(+), 83 deletions(-)
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
index fcc5db5e63c2..901ec681f010 100644
--- a/drivers/crypto/talitos/Makefile
+++ b/drivers/crypto/talitos/Makefile
@@ -1 +1,3 @@
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
+
+talitos-y := talitos.o talitos-rng.o
diff --git a/drivers/crypto/talitos/talitos-rng.c b/drivers/crypto/talitos/talitos-rng.c
new file mode 100644
index 000000000000..3aa00de33b25
--- /dev/null
+++ b/drivers/crypto/talitos/talitos-rng.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Freescale SEC (talitos) device hardware random number generator implementation
+ *
+ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include "talitos.h"
+
+static int talitos_rng_data_present(struct hwrng *rng, int wait)
+{
+ struct device *dev = (struct device *)rng->priv;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ u32 ofl;
+ int i;
+
+ for (i = 0; i < 20; i++) {
+ ofl = in_be32(priv->reg_rngu + TALITOS_EUSR_LO) &
+ TALITOS_RNGUSR_LO_OFL;
+ if (ofl || !wait)
+ break;
+ udelay(10);
+ }
+
+ return !!ofl;
+}
+
+static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
+{
+ struct device *dev = (struct device *)rng->priv;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ /* rng fifo requires 64-bit accesses */
+ *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO);
+ *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO);
+
+ return sizeof(u32);
+}
+
+static int talitos_rng_init(struct hwrng *rng)
+{
+ struct device *dev = (struct device *)rng->priv;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ unsigned int timeout = TALITOS_TIMEOUT;
+
+ setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR);
+ while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO)
+ & TALITOS_RNGUSR_LO_RD)
+ && --timeout)
+ cpu_relax();
+ if (timeout == 0) {
+ dev_err(dev, "failed to reset rng hw\n");
+ return -ENODEV;
+ }
+
+ /* start generating */
+ setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0);
+
+ return 0;
+}
+
+int talitos_register_rng(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ int err;
+
+ priv->rng.name = dev_driver_string(dev);
+ priv->rng.init = talitos_rng_init;
+ priv->rng.data_present = talitos_rng_data_present;
+ priv->rng.data_read = talitos_rng_data_read;
+ priv->rng.priv = (unsigned long)dev;
+
+ err = hwrng_register(&priv->rng);
+ if (!err)
+ priv->rng_registered = true;
+
+ return err;
+}
+
+void talitos_unregister_rng(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ if (!priv->rng_registered)
+ return;
+
+ hwrng_unregister(&priv->rng);
+ priv->rng_registered = false;
+}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 8ca587b98d92..f5feff8f7d3d 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -820,89 +820,6 @@ DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE, TALITOS2_ISR_CH_0_2_ERR,
DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
1)
-/*
- * hwrng
- */
-static int talitos_rng_data_present(struct hwrng *rng, int wait)
-{
- struct device *dev = (struct device *)rng->priv;
- struct talitos_private *priv = dev_get_drvdata(dev);
- u32 ofl;
- int i;
-
- for (i = 0; i < 20; i++) {
- ofl = in_be32(priv->reg_rngu + TALITOS_EUSR_LO) &
- TALITOS_RNGUSR_LO_OFL;
- if (ofl || !wait)
- break;
- udelay(10);
- }
-
- return !!ofl;
-}
-
-static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
-{
- struct device *dev = (struct device *)rng->priv;
- struct talitos_private *priv = dev_get_drvdata(dev);
-
- /* rng fifo requires 64-bit accesses */
- *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO);
- *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO);
-
- return sizeof(u32);
-}
-
-static int talitos_rng_init(struct hwrng *rng)
-{
- struct device *dev = (struct device *)rng->priv;
- struct talitos_private *priv = dev_get_drvdata(dev);
- unsigned int timeout = TALITOS_TIMEOUT;
-
- setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR);
- while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO)
- & TALITOS_RNGUSR_LO_RD)
- && --timeout)
- cpu_relax();
- if (timeout == 0) {
- dev_err(dev, "failed to reset rng hw\n");
- return -ENODEV;
- }
-
- /* start generating */
- setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0);
-
- return 0;
-}
-
-static int talitos_register_rng(struct device *dev)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
- int err;
-
- priv->rng.name = dev_driver_string(dev);
- priv->rng.init = talitos_rng_init;
- priv->rng.data_present = talitos_rng_data_present;
- priv->rng.data_read = talitos_rng_data_read;
- priv->rng.priv = (unsigned long)dev;
-
- err = hwrng_register(&priv->rng);
- if (!err)
- priv->rng_registered = true;
-
- return err;
-}
-
-static void talitos_unregister_rng(struct device *dev)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
-
- if (!priv->rng_registered)
- return;
-
- hwrng_unregister(&priv->rng);
- priv->rng_registered = false;
-}
/*
* crypto alg
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 56e36a65ddcc..fa8c71b1f90f 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -431,3 +431,8 @@ static inline bool has_ftr_sec1(struct talitos_private *priv)
#define DESC_PTR_LNKTBL_JUMP 0x80
#define DESC_PTR_LNKTBL_RET 0x02
#define DESC_PTR_LNKTBL_NEXT 0x01
+
+/* Hardware RNG */
+
+int talitos_register_rng(struct device *dev);
+void talitos_unregister_rng(struct device *dev);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 04/29] crypto: talitos/hwrng - Move into separate file
2026-05-28 9:08 ` [PATCH 04/29] crypto: talitos/hwrng - Move into separate file Paul Louvel
@ 2026-05-29 11:26 ` Christophe Leroy (CS GROUP)
0 siblings, 0 replies; 36+ messages in thread
From: Christophe Leroy (CS GROUP) @ 2026-05-29 11:26 UTC (permalink / raw)
To: Paul Louvel, Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, linux-crypto, linux-kernel
Le 28/05/2026 à 11:08, Paul Louvel a écrit :
> Move the hardware random number generator implementation from
> talitos.c into a dedicated talitos-rng.c file.
>
> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
> ---
> drivers/crypto/talitos/Makefile | 2 +
> drivers/crypto/talitos/talitos-rng.c | 93 ++++++++++++++++++++++++++++++++++++
> drivers/crypto/talitos/talitos.c | 83 --------------------------------
> drivers/crypto/talitos/talitos.h | 5 ++
> 4 files changed, 100 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
> index fcc5db5e63c2..901ec681f010 100644
> --- a/drivers/crypto/talitos/Makefile
> +++ b/drivers/crypto/talitos/Makefile
> @@ -1 +1,3 @@
> obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
> +
> +talitos-y := talitos.o talitos-rng.o
> diff --git a/drivers/crypto/talitos/talitos-rng.c b/drivers/crypto/talitos/talitos-rng.c
> new file mode 100644
> index 000000000000..3aa00de33b25
> --- /dev/null
> +++ b/drivers/crypto/talitos/talitos-rng.c
> @@ -0,0 +1,93 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +/*
> + * Freescale SEC (talitos) device hardware random number generator implementation
> + *
> + * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +
> +#include "talitos.h"
> +
> +static int talitos_rng_data_present(struct hwrng *rng, int wait)
> +{
> + struct device *dev = (struct device *)rng->priv;
> + struct talitos_private *priv = dev_get_drvdata(dev);
> + u32 ofl;
> + int i;
> +
> + for (i = 0; i < 20; i++) {
> + ofl = in_be32(priv->reg_rngu + TALITOS_EUSR_LO) &
> + TALITOS_RNGUSR_LO_OFL;
> + if (ofl || !wait)
> + break;
> + udelay(10);
> + }
> +
> + return !!ofl;
> +}
> +
> +static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
> +{
> + struct device *dev = (struct device *)rng->priv;
> + struct talitos_private *priv = dev_get_drvdata(dev);
> +
> + /* rng fifo requires 64-bit accesses */
> + *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO);
> + *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO);
> +
> + return sizeof(u32);
> +}
> +
> +static int talitos_rng_init(struct hwrng *rng)
> +{
> + struct device *dev = (struct device *)rng->priv;
> + struct talitos_private *priv = dev_get_drvdata(dev);
> + unsigned int timeout = TALITOS_TIMEOUT;
> +
> + setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR);
> + while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO)
> + & TALITOS_RNGUSR_LO_RD)
> + && --timeout)
> + cpu_relax();
> + if (timeout == 0) {
> + dev_err(dev, "failed to reset rng hw\n");
> + return -ENODEV;
> + }
> +
> + /* start generating */
> + setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0);
> +
> + return 0;
> +}
> +
> +int talitos_register_rng(struct device *dev)
> +{
> + struct talitos_private *priv = dev_get_drvdata(dev);
> + int err;
> +
> + priv->rng.name = dev_driver_string(dev);
> + priv->rng.init = talitos_rng_init;
> + priv->rng.data_present = talitos_rng_data_present;
> + priv->rng.data_read = talitos_rng_data_read;
> + priv->rng.priv = (unsigned long)dev;
> +
> + err = hwrng_register(&priv->rng);
> + if (!err)
> + priv->rng_registered = true;
> +
> + return err;
> +}
> +
> +void talitos_unregister_rng(struct device *dev)
> +{
> + struct talitos_private *priv = dev_get_drvdata(dev);
> +
> + if (!priv->rng_registered)
> + return;
> +
> + hwrng_unregister(&priv->rng);
> + priv->rng_registered = false;
> +}
> diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
> index 8ca587b98d92..f5feff8f7d3d 100644
> --- a/drivers/crypto/talitos/talitos.c
> +++ b/drivers/crypto/talitos/talitos.c
> @@ -820,89 +820,6 @@ DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE, TALITOS2_ISR_CH_0_2_ERR,
> DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
> 1)
>
> -/*
> - * hwrng
> - */
> -static int talitos_rng_data_present(struct hwrng *rng, int wait)
> -{
> - struct device *dev = (struct device *)rng->priv;
> - struct talitos_private *priv = dev_get_drvdata(dev);
> - u32 ofl;
> - int i;
> -
> - for (i = 0; i < 20; i++) {
> - ofl = in_be32(priv->reg_rngu + TALITOS_EUSR_LO) &
> - TALITOS_RNGUSR_LO_OFL;
> - if (ofl || !wait)
> - break;
> - udelay(10);
> - }
> -
> - return !!ofl;
> -}
> -
> -static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
> -{
> - struct device *dev = (struct device *)rng->priv;
> - struct talitos_private *priv = dev_get_drvdata(dev);
> -
> - /* rng fifo requires 64-bit accesses */
> - *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO);
> - *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO);
> -
> - return sizeof(u32);
> -}
> -
> -static int talitos_rng_init(struct hwrng *rng)
> -{
> - struct device *dev = (struct device *)rng->priv;
> - struct talitos_private *priv = dev_get_drvdata(dev);
> - unsigned int timeout = TALITOS_TIMEOUT;
> -
> - setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR);
> - while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO)
> - & TALITOS_RNGUSR_LO_RD)
> - && --timeout)
> - cpu_relax();
> - if (timeout == 0) {
> - dev_err(dev, "failed to reset rng hw\n");
> - return -ENODEV;
> - }
> -
> - /* start generating */
> - setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0);
> -
> - return 0;
> -}
> -
> -static int talitos_register_rng(struct device *dev)
> -{
> - struct talitos_private *priv = dev_get_drvdata(dev);
> - int err;
> -
> - priv->rng.name = dev_driver_string(dev);
> - priv->rng.init = talitos_rng_init;
> - priv->rng.data_present = talitos_rng_data_present;
> - priv->rng.data_read = talitos_rng_data_read;
> - priv->rng.priv = (unsigned long)dev;
> -
> - err = hwrng_register(&priv->rng);
> - if (!err)
> - priv->rng_registered = true;
> -
> - return err;
> -}
> -
> -static void talitos_unregister_rng(struct device *dev)
> -{
> - struct talitos_private *priv = dev_get_drvdata(dev);
> -
> - if (!priv->rng_registered)
> - return;
> -
> - hwrng_unregister(&priv->rng);
> - priv->rng_registered = false;
> -}
>
> /*
> * crypto alg
> diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
> index 56e36a65ddcc..fa8c71b1f90f 100644
> --- a/drivers/crypto/talitos/talitos.h
> +++ b/drivers/crypto/talitos/talitos.h
> @@ -431,3 +431,8 @@ static inline bool has_ftr_sec1(struct talitos_private *priv)
> #define DESC_PTR_LNKTBL_JUMP 0x80
> #define DESC_PTR_LNKTBL_RET 0x02
> #define DESC_PTR_LNKTBL_NEXT 0x01
> +
> +/* Hardware RNG */
> +
> +int talitos_register_rng(struct device *dev);
> +void talitos_unregister_rng(struct device *dev);
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 05/29] crypto: talitos - Prepare crypto implementation file splitting
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (3 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 04/29] crypto: talitos/hwrng - Move into separate file Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-29 13:21 ` Christophe Leroy (CS GROUP)
2026-05-28 9:08 ` [PATCH 06/29] crypto: talitos - Introduce registration helper Paul Louvel
` (23 subsequent siblings)
28 siblings, 1 reply; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Remove the static qualifier on multiple function that will be called
inside each crypto implementation file.
Add them to the main driver header file.
Add the common structures too.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 123 ++++++++++++++-------------------------
drivers/crypto/talitos/talitos.h | 91 +++++++++++++++++++++++++++++
2 files changed, 135 insertions(+), 79 deletions(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index f5feff8f7d3d..3fc1069062da 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -40,8 +40,8 @@
#include "talitos.h"
-static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
- unsigned int len, bool is_sec1)
+void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
+ unsigned int len, bool is_sec1)
{
ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
if (is_sec1) {
@@ -52,8 +52,8 @@ static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
}
}
-static void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
- struct talitos_ptr *src_ptr, bool is_sec1)
+void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
+ struct talitos_ptr *src_ptr, bool is_sec1)
{
dst_ptr->ptr = src_ptr->ptr;
if (is_sec1) {
@@ -64,8 +64,8 @@ static void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
}
}
-static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
- bool is_sec1)
+unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
+ bool is_sec1)
{
if (is_sec1)
return be16_to_cpu(ptr->len1);
@@ -73,14 +73,14 @@ static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
return be16_to_cpu(ptr->len);
}
-static void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
- bool is_sec1)
+void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
+ bool is_sec1)
{
if (!is_sec1)
ptr->j_extent = val;
}
-static void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1)
+void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1)
{
if (!is_sec1)
ptr->j_extent |= val;
@@ -102,15 +102,15 @@ static void __map_single_talitos_ptr(struct device *dev,
to_talitos_ptr(ptr, dma_addr, len, is_sec1);
}
-static void map_single_talitos_ptr(struct device *dev,
- struct talitos_ptr *ptr,
- unsigned int len, void *data,
- enum dma_data_direction dir)
+void map_single_talitos_ptr(struct device *dev,
+ struct talitos_ptr *ptr,
+ unsigned int len, void *data,
+ enum dma_data_direction dir)
{
__map_single_talitos_ptr(dev, ptr, len, data, dir, 0);
}
-static void map_single_talitos_ptr_nosync(struct device *dev,
+void map_single_talitos_ptr_nosync(struct device *dev,
struct talitos_ptr *ptr,
unsigned int len, void *data,
enum dma_data_direction dir)
@@ -122,9 +122,9 @@ static void map_single_talitos_ptr_nosync(struct device *dev,
/*
* unmap bus single (contiguous) h/w descriptor pointer
*/
-static void unmap_single_talitos_ptr(struct device *dev,
- struct talitos_ptr *ptr,
- enum dma_data_direction dir)
+void unmap_single_talitos_ptr(struct device *dev,
+ struct talitos_ptr *ptr,
+ enum dma_data_direction dir)
{
struct talitos_private *priv = dev_get_drvdata(dev);
bool is_sec1 = has_ftr_sec1(priv);
@@ -303,11 +303,11 @@ static void dma_map_request(struct device *dev, struct talitos_request *request,
* callback must check err and feedback in descriptor header
* for device processing status.
*/
-static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
- void (*callback)(struct device *dev,
- struct talitos_desc *desc,
- void *context, int error),
- void *context)
+int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
+ void (*callback)(struct device *dev,
+ struct talitos_desc *desc,
+ void *context, int error),
+ void *context)
{
struct talitos_private *priv = dev_get_drvdata(dev);
struct talitos_request *request;
@@ -830,24 +830,6 @@ DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
* HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP
*/
#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
-#ifdef CONFIG_CRYPTO_DEV_TALITOS2
-#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE)
-#else
-#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA256_BLOCK_SIZE)
-#endif
-#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
-
-struct talitos_ctx {
- struct device *dev;
- int ch;
- __be32 desc_hdr_template;
- u8 key[TALITOS_MAX_KEY_SIZE];
- u8 iv[TALITOS_MAX_IV_LENGTH];
- dma_addr_t dma_key;
- unsigned int keylen;
- unsigned int enckeylen;
- unsigned int authkeylen;
-};
#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
@@ -939,7 +921,7 @@ static int aead_des3_setkey(struct crypto_aead *authenc,
return err;
}
-static void talitos_sg_unmap(struct device *dev,
+void talitos_sg_unmap(struct device *dev,
struct talitos_edesc *edesc,
struct scatterlist *src,
struct scatterlist *dst,
@@ -1124,7 +1106,7 @@ static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
return count;
}
-static int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
+int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
unsigned int len, struct talitos_edesc *edesc,
struct talitos_ptr *ptr, int sg_count,
unsigned int offset, int tbl_off, int elen,
@@ -1161,7 +1143,7 @@ static int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
return sg_count;
}
-static int talitos_sg_map(struct device *dev, struct scatterlist *src,
+int talitos_sg_map(struct device *dev, struct scatterlist *src,
unsigned int len, struct talitos_edesc *edesc,
struct talitos_ptr *ptr, int sg_count,
unsigned int offset, int tbl_off)
@@ -1299,17 +1281,17 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
/*
* allocate and map the extended descriptor
*/
-static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
- struct scatterlist *src,
- struct scatterlist *dst,
- u8 *iv,
- unsigned int assoclen,
- unsigned int cryptlen,
- unsigned int authsize,
- unsigned int ivsize,
- int icv_stashing,
- u32 cryptoflags,
- bool encrypt)
+struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
+ struct scatterlist *src,
+ struct scatterlist *dst,
+ u8 *iv,
+ unsigned int assoclen,
+ unsigned int cryptlen,
+ unsigned int authsize,
+ unsigned int ivsize,
+ int icv_stashing,
+ u32 cryptoflags,
+ bool encrypt)
{
struct talitos_edesc *edesc;
int src_nents, dst_nents, alloc_len, dma_len, src_len, dst_len;
@@ -2172,18 +2154,6 @@ static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
return 0;
}
-
-struct talitos_alg_template {
- u32 type;
- u32 priority;
- union {
- struct skcipher_alg skcipher;
- struct ahash_alg hash;
- struct aead_alg aead;
- } alg;
- __be32 desc_hdr_template;
-};
-
static struct talitos_alg_template driver_algs[] = {
/* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
{ .type = CRYPTO_ALG_TYPE_AEAD,
@@ -2998,14 +2968,8 @@ static struct talitos_alg_template driver_algs[] = {
}
};
-struct talitos_crypto_alg {
- struct list_head entry;
- struct device *dev;
- struct talitos_alg_template algt;
-};
-
-static int talitos_init_common(struct talitos_ctx *ctx,
- struct talitos_crypto_alg *talitos_alg)
+int talitos_init_common(struct talitos_ctx *ctx,
+ struct talitos_crypto_alg *talitos_alg)
{
struct talitos_private *priv;
@@ -3066,7 +3030,7 @@ static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
return talitos_init_common(ctx, talitos_alg);
}
-static void talitos_cra_exit(struct crypto_tfm *tfm)
+void talitos_cra_exit(struct crypto_tfm *tfm)
{
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
struct device *dev = ctx->dev;
@@ -3080,7 +3044,7 @@ static void talitos_cra_exit(struct crypto_tfm *tfm)
* type and primary/secondary execution units required match the hw
* capabilities description provided in the device tree node.
*/
-static int hw_supports(struct device *dev, __be32 desc_hdr_template)
+int talitos_hw_supports(struct device *dev, __be32 desc_hdr_template)
{
struct talitos_private *priv = dev_get_drvdata(dev);
int ret;
@@ -3117,7 +3081,7 @@ static void talitos_remove(struct platform_device *ofdev)
list_del(&t_alg->entry);
}
- if (hw_supports(dev, DESC_HDR_SEL0_RNG))
+ if (talitos_hw_supports(dev, DESC_HDR_SEL0_RNG))
talitos_unregister_rng(dev);
for (i = 0; i < 2; i++)
@@ -3426,7 +3390,7 @@ static int talitos_probe(struct platform_device *ofdev)
}
/* register the RNG, if available */
- if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
+ if (talitos_hw_supports(dev, DESC_HDR_SEL0_RNG)) {
err = talitos_register_rng(dev);
if (err) {
dev_err(dev, "failed to register hwrng: %d\n", err);
@@ -3437,7 +3401,8 @@ static int talitos_probe(struct platform_device *ofdev)
/* register crypto algorithms the device supports */
for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
- if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
+ if (talitos_hw_supports(dev,
+ driver_algs[i].desc_hdr_template)) {
struct talitos_crypto_alg *t_alg;
struct crypto_alg *alg = NULL;
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index fa8c71b1f90f..1f81d336dae8 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -5,7 +5,13 @@
* Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
*/
+#include <crypto/aes.h>
+#include <crypto/internal/aead.h>
+#include <crypto/internal/hash.h>
+#include <crypto/internal/skcipher.h>
+#include <crypto/sha2.h>
#include <linux/device.h>
+#include <linux/dma-mapping.h>
#include <linux/hw_random.h>
#include <linux/interrupt.h>
#include <linux/scatterlist.h>
@@ -19,6 +25,13 @@
#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
+#ifdef CONFIG_CRYPTO_DEV_TALITOS2
+#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE)
+#else
+#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA256_BLOCK_SIZE)
+#endif
+#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
+
/* descriptor pointer entry */
struct talitos_ptr {
union {
@@ -174,6 +187,35 @@ struct talitos_private {
};
+struct talitos_ctx {
+ struct device *dev;
+ int ch;
+ __be32 desc_hdr_template;
+ u8 key[TALITOS_MAX_KEY_SIZE];
+ u8 iv[TALITOS_MAX_IV_LENGTH];
+ dma_addr_t dma_key;
+ unsigned int keylen;
+ unsigned int enckeylen;
+ unsigned int authkeylen;
+};
+
+struct talitos_alg_template {
+ u32 type;
+ u32 priority;
+ union {
+ struct skcipher_alg skcipher;
+ struct ahash_alg hash;
+ struct aead_alg aead;
+ } alg;
+ __be32 desc_hdr_template;
+};
+
+struct talitos_crypto_alg {
+ struct list_head entry;
+ struct device *dev;
+ struct talitos_alg_template algt;
+};
+
/* .features flag */
#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
@@ -432,6 +474,55 @@ static inline bool has_ftr_sec1(struct talitos_private *priv)
#define DESC_PTR_LNKTBL_RET 0x02
#define DESC_PTR_LNKTBL_NEXT 0x01
+void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
+ unsigned int len, bool is_sec1);
+void copy_talitos_ptr(struct talitos_ptr *dst_ptr, struct talitos_ptr *src_ptr,
+ bool is_sec1);
+unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr, bool is_sec1);
+void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val, bool is_sec1);
+void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1);
+
+void map_single_talitos_ptr(struct device *dev, struct talitos_ptr *ptr,
+ unsigned int len, void *data,
+ enum dma_data_direction dir);
+void map_single_talitos_ptr_nosync(struct device *dev, struct talitos_ptr *ptr,
+ unsigned int len, void *data,
+ enum dma_data_direction dir);
+void unmap_single_talitos_ptr(struct device *dev, struct talitos_ptr *ptr,
+ enum dma_data_direction dir);
+
+int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
+ void (*callback)(struct device *dev,
+ struct talitos_desc *desc, void *context,
+ int error),
+ void *context);
+
+void talitos_sg_unmap(struct device *dev, struct talitos_edesc *edesc,
+ struct scatterlist *src, struct scatterlist *dst,
+ unsigned int len, unsigned int offset);
+int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
+ unsigned int len, struct talitos_edesc *edesc,
+ struct talitos_ptr *ptr, int sg_count,
+ unsigned int offset, int tbl_off, int elen, bool force,
+ int align);
+int talitos_sg_map(struct device *dev, struct scatterlist *src,
+ unsigned int len, struct talitos_edesc *edesc,
+ struct talitos_ptr *ptr, int sg_count, unsigned int offset,
+ int tbl_off);
+
+struct talitos_edesc *
+talitos_edesc_alloc(struct device *dev, struct scatterlist *src,
+ struct scatterlist *dst, u8 *iv, unsigned int assoclen,
+ unsigned int cryptlen, unsigned int authsize,
+ unsigned int ivsize, int icv_stashing, u32 cryptoflags,
+ bool encrypt);
+
+int talitos_hw_supports(struct device *dev, __be32 desc_hdr_template);
+
+int talitos_init_common(struct talitos_ctx *ctx,
+ struct talitos_crypto_alg *talitos_alg);
+void talitos_cra_exit(struct crypto_tfm *tfm);
+
/* Hardware RNG */
int talitos_register_rng(struct device *dev);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 05/29] crypto: talitos - Prepare crypto implementation file splitting
2026-05-28 9:08 ` [PATCH 05/29] crypto: talitos - Prepare crypto implementation file splitting Paul Louvel
@ 2026-05-29 13:21 ` Christophe Leroy (CS GROUP)
2026-05-29 16:24 ` David Laight
0 siblings, 1 reply; 36+ messages in thread
From: Christophe Leroy (CS GROUP) @ 2026-05-29 13:21 UTC (permalink / raw)
To: Paul Louvel, Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, linux-crypto, linux-kernel
Hi Paul,
Le 28/05/2026 à 11:08, Paul Louvel a écrit :
> Remove the static qualifier on multiple function that will be called
> inside each crypto implementation file.
> Add them to the main driver header file.
I didn't have time to look at the generated text yet but I'm a bit
sceptic with this change, or more than the change itself, about its
purpose. And even more when I see patches 24 and 25.
Most functions here are small helpers. To be shared between several C
files they deserve becoming static inlines in talitos.h, not global
functions.
Indeed, most of the time is_sec1 is known at build time because in most
cases has_ftr_sec1() will constant fold into true or false during build.
This is because it is very unlikely that someone build a kernel to run
on both MPC 82xx and MPC 83xx at the same time. Therefore it is really
unlikely that this in built with both CRYPTO_DEV_TALITOS1 and
CRYPTO_DEV_TALITOS2 at the same time.
I can understand for a function like talitos_submit() but not for
functions like to_talitos_ptr() or to_talitos_ptr_ext_set() whose
purpose is really to get inlined into the caller.
Christophe
>
> Add the common structures too.
>
> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
> ---
> drivers/crypto/talitos/talitos.c | 123 ++++++++++++++-------------------------
> drivers/crypto/talitos/talitos.h | 91 +++++++++++++++++++++++++++++
> 2 files changed, 135 insertions(+), 79 deletions(-)
>
> diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
> index f5feff8f7d3d..3fc1069062da 100644
> --- a/drivers/crypto/talitos/talitos.c
> +++ b/drivers/crypto/talitos/talitos.c
> @@ -40,8 +40,8 @@
>
> #include "talitos.h"
>
> -static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
> - unsigned int len, bool is_sec1)
> +void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
> + unsigned int len, bool is_sec1)
> {
> ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
> if (is_sec1) {
> @@ -52,8 +52,8 @@ static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
> }
> }
>
> -static void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
> - struct talitos_ptr *src_ptr, bool is_sec1)
> +void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
> + struct talitos_ptr *src_ptr, bool is_sec1)
> {
> dst_ptr->ptr = src_ptr->ptr;
> if (is_sec1) {
> @@ -64,8 +64,8 @@ static void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
> }
> }
>
> -static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
> - bool is_sec1)
> +unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
> + bool is_sec1)
> {
> if (is_sec1)
> return be16_to_cpu(ptr->len1);
> @@ -73,14 +73,14 @@ static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
> return be16_to_cpu(ptr->len);
> }
>
> -static void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
> - bool is_sec1)
> +void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
> + bool is_sec1)
> {
> if (!is_sec1)
> ptr->j_extent = val;
> }
>
> -static void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1)
> +void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1)
> {
> if (!is_sec1)
> ptr->j_extent |= val;
> @@ -102,15 +102,15 @@ static void __map_single_talitos_ptr(struct device *dev,
> to_talitos_ptr(ptr, dma_addr, len, is_sec1);
> }
>
> -static void map_single_talitos_ptr(struct device *dev,
> - struct talitos_ptr *ptr,
> - unsigned int len, void *data,
> - enum dma_data_direction dir)
> +void map_single_talitos_ptr(struct device *dev,
> + struct talitos_ptr *ptr,
> + unsigned int len, void *data,
> + enum dma_data_direction dir)
> {
> __map_single_talitos_ptr(dev, ptr, len, data, dir, 0);
> }
>
> -static void map_single_talitos_ptr_nosync(struct device *dev,
> +void map_single_talitos_ptr_nosync(struct device *dev,
> struct talitos_ptr *ptr,
> unsigned int len, void *data,
> enum dma_data_direction dir)
> @@ -122,9 +122,9 @@ static void map_single_talitos_ptr_nosync(struct device *dev,
> /*
> * unmap bus single (contiguous) h/w descriptor pointer
> */
> -static void unmap_single_talitos_ptr(struct device *dev,
> - struct talitos_ptr *ptr,
> - enum dma_data_direction dir)
> +void unmap_single_talitos_ptr(struct device *dev,
> + struct talitos_ptr *ptr,
> + enum dma_data_direction dir)
> {
> struct talitos_private *priv = dev_get_drvdata(dev);
> bool is_sec1 = has_ftr_sec1(priv);
> @@ -303,11 +303,11 @@ static void dma_map_request(struct device *dev, struct talitos_request *request,
> * callback must check err and feedback in descriptor header
> * for device processing status.
> */
> -static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
> - void (*callback)(struct device *dev,
> - struct talitos_desc *desc,
> - void *context, int error),
> - void *context)
> +int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
> + void (*callback)(struct device *dev,
> + struct talitos_desc *desc,
> + void *context, int error),
> + void *context)
> {
> struct talitos_private *priv = dev_get_drvdata(dev);
> struct talitos_request *request;
> @@ -830,24 +830,6 @@ DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
> * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP
> */
> #define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
> -#ifdef CONFIG_CRYPTO_DEV_TALITOS2
> -#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE)
> -#else
> -#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA256_BLOCK_SIZE)
> -#endif
> -#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
> -
> -struct talitos_ctx {
> - struct device *dev;
> - int ch;
> - __be32 desc_hdr_template;
> - u8 key[TALITOS_MAX_KEY_SIZE];
> - u8 iv[TALITOS_MAX_IV_LENGTH];
> - dma_addr_t dma_key;
> - unsigned int keylen;
> - unsigned int enckeylen;
> - unsigned int authkeylen;
> -};
>
> #define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
> #define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
> @@ -939,7 +921,7 @@ static int aead_des3_setkey(struct crypto_aead *authenc,
> return err;
> }
>
> -static void talitos_sg_unmap(struct device *dev,
> +void talitos_sg_unmap(struct device *dev,
> struct talitos_edesc *edesc,
> struct scatterlist *src,
> struct scatterlist *dst,
> @@ -1124,7 +1106,7 @@ static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
> return count;
> }
>
> -static int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
> +int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
> unsigned int len, struct talitos_edesc *edesc,
> struct talitos_ptr *ptr, int sg_count,
> unsigned int offset, int tbl_off, int elen,
> @@ -1161,7 +1143,7 @@ static int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
> return sg_count;
> }
>
> -static int talitos_sg_map(struct device *dev, struct scatterlist *src,
> +int talitos_sg_map(struct device *dev, struct scatterlist *src,
> unsigned int len, struct talitos_edesc *edesc,
> struct talitos_ptr *ptr, int sg_count,
> unsigned int offset, int tbl_off)
> @@ -1299,17 +1281,17 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
> /*
> * allocate and map the extended descriptor
> */
> -static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
> - struct scatterlist *src,
> - struct scatterlist *dst,
> - u8 *iv,
> - unsigned int assoclen,
> - unsigned int cryptlen,
> - unsigned int authsize,
> - unsigned int ivsize,
> - int icv_stashing,
> - u32 cryptoflags,
> - bool encrypt)
> +struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
> + struct scatterlist *src,
> + struct scatterlist *dst,
> + u8 *iv,
> + unsigned int assoclen,
> + unsigned int cryptlen,
> + unsigned int authsize,
> + unsigned int ivsize,
> + int icv_stashing,
> + u32 cryptoflags,
> + bool encrypt)
> {
> struct talitos_edesc *edesc;
> int src_nents, dst_nents, alloc_len, dma_len, src_len, dst_len;
> @@ -2172,18 +2154,6 @@ static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
> return 0;
> }
>
> -
> -struct talitos_alg_template {
> - u32 type;
> - u32 priority;
> - union {
> - struct skcipher_alg skcipher;
> - struct ahash_alg hash;
> - struct aead_alg aead;
> - } alg;
> - __be32 desc_hdr_template;
> -};
> -
> static struct talitos_alg_template driver_algs[] = {
> /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
> { .type = CRYPTO_ALG_TYPE_AEAD,
> @@ -2998,14 +2968,8 @@ static struct talitos_alg_template driver_algs[] = {
> }
> };
>
> -struct talitos_crypto_alg {
> - struct list_head entry;
> - struct device *dev;
> - struct talitos_alg_template algt;
> -};
> -
> -static int talitos_init_common(struct talitos_ctx *ctx,
> - struct talitos_crypto_alg *talitos_alg)
> +int talitos_init_common(struct talitos_ctx *ctx,
> + struct talitos_crypto_alg *talitos_alg)
> {
> struct talitos_private *priv;
>
> @@ -3066,7 +3030,7 @@ static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
> return talitos_init_common(ctx, talitos_alg);
> }
>
> -static void talitos_cra_exit(struct crypto_tfm *tfm)
> +void talitos_cra_exit(struct crypto_tfm *tfm)
> {
> struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
> struct device *dev = ctx->dev;
> @@ -3080,7 +3044,7 @@ static void talitos_cra_exit(struct crypto_tfm *tfm)
> * type and primary/secondary execution units required match the hw
> * capabilities description provided in the device tree node.
> */
> -static int hw_supports(struct device *dev, __be32 desc_hdr_template)
> +int talitos_hw_supports(struct device *dev, __be32 desc_hdr_template)
> {
> struct talitos_private *priv = dev_get_drvdata(dev);
> int ret;
> @@ -3117,7 +3081,7 @@ static void talitos_remove(struct platform_device *ofdev)
> list_del(&t_alg->entry);
> }
>
> - if (hw_supports(dev, DESC_HDR_SEL0_RNG))
> + if (talitos_hw_supports(dev, DESC_HDR_SEL0_RNG))
> talitos_unregister_rng(dev);
>
> for (i = 0; i < 2; i++)
> @@ -3426,7 +3390,7 @@ static int talitos_probe(struct platform_device *ofdev)
> }
>
> /* register the RNG, if available */
> - if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
> + if (talitos_hw_supports(dev, DESC_HDR_SEL0_RNG)) {
> err = talitos_register_rng(dev);
> if (err) {
> dev_err(dev, "failed to register hwrng: %d\n", err);
> @@ -3437,7 +3401,8 @@ static int talitos_probe(struct platform_device *ofdev)
>
> /* register crypto algorithms the device supports */
> for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
> - if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
> + if (talitos_hw_supports(dev,
> + driver_algs[i].desc_hdr_template)) {
> struct talitos_crypto_alg *t_alg;
> struct crypto_alg *alg = NULL;
>
> diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
> index fa8c71b1f90f..1f81d336dae8 100644
> --- a/drivers/crypto/talitos/talitos.h
> +++ b/drivers/crypto/talitos/talitos.h
> @@ -5,7 +5,13 @@
> * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
> */
>
> +#include <crypto/aes.h>
> +#include <crypto/internal/aead.h>
> +#include <crypto/internal/hash.h>
> +#include <crypto/internal/skcipher.h>
> +#include <crypto/sha2.h>
> #include <linux/device.h>
> +#include <linux/dma-mapping.h>
> #include <linux/hw_random.h>
> #include <linux/interrupt.h>
> #include <linux/scatterlist.h>
> @@ -19,6 +25,13 @@
> #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
> #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
>
> +#ifdef CONFIG_CRYPTO_DEV_TALITOS2
> +#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE)
> +#else
> +#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA256_BLOCK_SIZE)
> +#endif
> +#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
> +
> /* descriptor pointer entry */
> struct talitos_ptr {
> union {
> @@ -174,6 +187,35 @@ struct talitos_private {
>
> };
>
> +struct talitos_ctx {
> + struct device *dev;
> + int ch;
> + __be32 desc_hdr_template;
> + u8 key[TALITOS_MAX_KEY_SIZE];
> + u8 iv[TALITOS_MAX_IV_LENGTH];
> + dma_addr_t dma_key;
> + unsigned int keylen;
> + unsigned int enckeylen;
> + unsigned int authkeylen;
> +};
> +
> +struct talitos_alg_template {
> + u32 type;
> + u32 priority;
> + union {
> + struct skcipher_alg skcipher;
> + struct ahash_alg hash;
> + struct aead_alg aead;
> + } alg;
> + __be32 desc_hdr_template;
> +};
> +
> +struct talitos_crypto_alg {
> + struct list_head entry;
> + struct device *dev;
> + struct talitos_alg_template algt;
> +};
> +
> /* .features flag */
> #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
> #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
> @@ -432,6 +474,55 @@ static inline bool has_ftr_sec1(struct talitos_private *priv)
> #define DESC_PTR_LNKTBL_RET 0x02
> #define DESC_PTR_LNKTBL_NEXT 0x01
>
> +void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
> + unsigned int len, bool is_sec1);
> +void copy_talitos_ptr(struct talitos_ptr *dst_ptr, struct talitos_ptr *src_ptr,
> + bool is_sec1);
> +unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr, bool is_sec1);
> +void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val, bool is_sec1);
> +void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1);
> +
> +void map_single_talitos_ptr(struct device *dev, struct talitos_ptr *ptr,
> + unsigned int len, void *data,
> + enum dma_data_direction dir);
> +void map_single_talitos_ptr_nosync(struct device *dev, struct talitos_ptr *ptr,
> + unsigned int len, void *data,
> + enum dma_data_direction dir);
> +void unmap_single_talitos_ptr(struct device *dev, struct talitos_ptr *ptr,
> + enum dma_data_direction dir);
> +
> +int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
> + void (*callback)(struct device *dev,
> + struct talitos_desc *desc, void *context,
> + int error),
> + void *context);
> +
> +void talitos_sg_unmap(struct device *dev, struct talitos_edesc *edesc,
> + struct scatterlist *src, struct scatterlist *dst,
> + unsigned int len, unsigned int offset);
> +int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
> + unsigned int len, struct talitos_edesc *edesc,
> + struct talitos_ptr *ptr, int sg_count,
> + unsigned int offset, int tbl_off, int elen, bool force,
> + int align);
> +int talitos_sg_map(struct device *dev, struct scatterlist *src,
> + unsigned int len, struct talitos_edesc *edesc,
> + struct talitos_ptr *ptr, int sg_count, unsigned int offset,
> + int tbl_off);
> +
> +struct talitos_edesc *
> +talitos_edesc_alloc(struct device *dev, struct scatterlist *src,
> + struct scatterlist *dst, u8 *iv, unsigned int assoclen,
> + unsigned int cryptlen, unsigned int authsize,
> + unsigned int ivsize, int icv_stashing, u32 cryptoflags,
> + bool encrypt);
> +
> +int talitos_hw_supports(struct device *dev, __be32 desc_hdr_template);
> +
> +int talitos_init_common(struct talitos_ctx *ctx,
> + struct talitos_crypto_alg *talitos_alg);
> +void talitos_cra_exit(struct crypto_tfm *tfm);
> +
> /* Hardware RNG */
>
> int talitos_register_rng(struct device *dev);
>
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 05/29] crypto: talitos - Prepare crypto implementation file splitting
2026-05-29 13:21 ` Christophe Leroy (CS GROUP)
@ 2026-05-29 16:24 ` David Laight
0 siblings, 0 replies; 36+ messages in thread
From: David Laight @ 2026-05-29 16:24 UTC (permalink / raw)
To: Christophe Leroy (CS GROUP)
Cc: Paul Louvel, Herbert Xu, David S. Miller, Thomas Petazzoni,
Herve Codina, linux-crypto, linux-kernel
On Fri, 29 May 2026 15:21:39 +0200
"Christophe Leroy (CS GROUP)" <chleroy@kernel.org> wrote:
> Hi Paul,
>
> Le 28/05/2026 à 11:08, Paul Louvel a écrit :
> > Remove the static qualifier on multiple function that will be called
> > inside each crypto implementation file.
> > Add them to the main driver header file.
>
> I didn't have time to look at the generated text yet but I'm a bit
> sceptic with this change, or more than the change itself, about its
> purpose. And even more when I see patches 24 and 25.
>
> Most functions here are small helpers. To be shared between several C
> files they deserve becoming static inlines in talitos.h, not global
> functions.
>
> Indeed, most of the time is_sec1 is known at build time because in most
> cases has_ftr_sec1() will constant fold into true or false during build.
> This is because it is very unlikely that someone build a kernel to run
> on both MPC 82xx and MPC 83xx at the same time. Therefore it is really
> unlikely that this in built with both CRYPTO_DEV_TALITOS1 and
> CRYPTO_DEV_TALITOS2 at the same time.
>
> I can understand for a function like talitos_submit() but not for
> functions like to_talitos_ptr() or to_talitos_ptr_ext_set() whose
> purpose is really to get inlined into the caller.
I also spotted a couple of indirect calls being added.
They will be slower than you might think.
If there are only two options it is better to use an 'if'.
-- David
>
> Christophe
>
>
> >
> > Add the common structures too.
> >
> > Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
> > ---
> > drivers/crypto/talitos/talitos.c | 123 ++++++++++++++-------------------------
> > drivers/crypto/talitos/talitos.h | 91 +++++++++++++++++++++++++++++
> > 2 files changed, 135 insertions(+), 79 deletions(-)
> >
> > diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
> > index f5feff8f7d3d..3fc1069062da 100644
> > --- a/drivers/crypto/talitos/talitos.c
> > +++ b/drivers/crypto/talitos/talitos.c
> > @@ -40,8 +40,8 @@
> >
> > #include "talitos.h"
> >
> > -static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
> > - unsigned int len, bool is_sec1)
> > +void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
> > + unsigned int len, bool is_sec1)
> > {
> > ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
> > if (is_sec1) {
> > @@ -52,8 +52,8 @@ static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
> > }
> > }
> >
> > -static void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
> > - struct talitos_ptr *src_ptr, bool is_sec1)
> > +void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
> > + struct talitos_ptr *src_ptr, bool is_sec1)
> > {
> > dst_ptr->ptr = src_ptr->ptr;
> > if (is_sec1) {
> > @@ -64,8 +64,8 @@ static void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
> > }
> > }
> >
> > -static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
> > - bool is_sec1)
> > +unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
> > + bool is_sec1)
> > {
> > if (is_sec1)
> > return be16_to_cpu(ptr->len1);
> > @@ -73,14 +73,14 @@ static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
> > return be16_to_cpu(ptr->len);
> > }
> >
> > -static void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
> > - bool is_sec1)
> > +void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
> > + bool is_sec1)
> > {
> > if (!is_sec1)
> > ptr->j_extent = val;
> > }
> >
> > -static void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1)
> > +void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1)
> > {
> > if (!is_sec1)
> > ptr->j_extent |= val;
> > @@ -102,15 +102,15 @@ static void __map_single_talitos_ptr(struct device *dev,
> > to_talitos_ptr(ptr, dma_addr, len, is_sec1);
> > }
> >
> > -static void map_single_talitos_ptr(struct device *dev,
> > - struct talitos_ptr *ptr,
> > - unsigned int len, void *data,
> > - enum dma_data_direction dir)
> > +void map_single_talitos_ptr(struct device *dev,
> > + struct talitos_ptr *ptr,
> > + unsigned int len, void *data,
> > + enum dma_data_direction dir)
> > {
> > __map_single_talitos_ptr(dev, ptr, len, data, dir, 0);
> > }
> >
> > -static void map_single_talitos_ptr_nosync(struct device *dev,
> > +void map_single_talitos_ptr_nosync(struct device *dev,
> > struct talitos_ptr *ptr,
> > unsigned int len, void *data,
> > enum dma_data_direction dir)
> > @@ -122,9 +122,9 @@ static void map_single_talitos_ptr_nosync(struct device *dev,
> > /*
> > * unmap bus single (contiguous) h/w descriptor pointer
> > */
> > -static void unmap_single_talitos_ptr(struct device *dev,
> > - struct talitos_ptr *ptr,
> > - enum dma_data_direction dir)
> > +void unmap_single_talitos_ptr(struct device *dev,
> > + struct talitos_ptr *ptr,
> > + enum dma_data_direction dir)
> > {
> > struct talitos_private *priv = dev_get_drvdata(dev);
> > bool is_sec1 = has_ftr_sec1(priv);
> > @@ -303,11 +303,11 @@ static void dma_map_request(struct device *dev, struct talitos_request *request,
> > * callback must check err and feedback in descriptor header
> > * for device processing status.
> > */
> > -static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
> > - void (*callback)(struct device *dev,
> > - struct talitos_desc *desc,
> > - void *context, int error),
> > - void *context)
> > +int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
> > + void (*callback)(struct device *dev,
> > + struct talitos_desc *desc,
> > + void *context, int error),
> > + void *context)
> > {
> > struct talitos_private *priv = dev_get_drvdata(dev);
> > struct talitos_request *request;
> > @@ -830,24 +830,6 @@ DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
> > * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP
> > */
> > #define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
> > -#ifdef CONFIG_CRYPTO_DEV_TALITOS2
> > -#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE)
> > -#else
> > -#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA256_BLOCK_SIZE)
> > -#endif
> > -#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
> > -
> > -struct talitos_ctx {
> > - struct device *dev;
> > - int ch;
> > - __be32 desc_hdr_template;
> > - u8 key[TALITOS_MAX_KEY_SIZE];
> > - u8 iv[TALITOS_MAX_IV_LENGTH];
> > - dma_addr_t dma_key;
> > - unsigned int keylen;
> > - unsigned int enckeylen;
> > - unsigned int authkeylen;
> > -};
> >
> > #define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
> > #define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
> > @@ -939,7 +921,7 @@ static int aead_des3_setkey(struct crypto_aead *authenc,
> > return err;
> > }
> >
> > -static void talitos_sg_unmap(struct device *dev,
> > +void talitos_sg_unmap(struct device *dev,
> > struct talitos_edesc *edesc,
> > struct scatterlist *src,
> > struct scatterlist *dst,
> > @@ -1124,7 +1106,7 @@ static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
> > return count;
> > }
> >
> > -static int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
> > +int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
> > unsigned int len, struct talitos_edesc *edesc,
> > struct talitos_ptr *ptr, int sg_count,
> > unsigned int offset, int tbl_off, int elen,
> > @@ -1161,7 +1143,7 @@ static int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
> > return sg_count;
> > }
> >
> > -static int talitos_sg_map(struct device *dev, struct scatterlist *src,
> > +int talitos_sg_map(struct device *dev, struct scatterlist *src,
> > unsigned int len, struct talitos_edesc *edesc,
> > struct talitos_ptr *ptr, int sg_count,
> > unsigned int offset, int tbl_off)
> > @@ -1299,17 +1281,17 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
> > /*
> > * allocate and map the extended descriptor
> > */
> > -static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
> > - struct scatterlist *src,
> > - struct scatterlist *dst,
> > - u8 *iv,
> > - unsigned int assoclen,
> > - unsigned int cryptlen,
> > - unsigned int authsize,
> > - unsigned int ivsize,
> > - int icv_stashing,
> > - u32 cryptoflags,
> > - bool encrypt)
> > +struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
> > + struct scatterlist *src,
> > + struct scatterlist *dst,
> > + u8 *iv,
> > + unsigned int assoclen,
> > + unsigned int cryptlen,
> > + unsigned int authsize,
> > + unsigned int ivsize,
> > + int icv_stashing,
> > + u32 cryptoflags,
> > + bool encrypt)
> > {
> > struct talitos_edesc *edesc;
> > int src_nents, dst_nents, alloc_len, dma_len, src_len, dst_len;
> > @@ -2172,18 +2154,6 @@ static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
> > return 0;
> > }
> >
> > -
> > -struct talitos_alg_template {
> > - u32 type;
> > - u32 priority;
> > - union {
> > - struct skcipher_alg skcipher;
> > - struct ahash_alg hash;
> > - struct aead_alg aead;
> > - } alg;
> > - __be32 desc_hdr_template;
> > -};
> > -
> > static struct talitos_alg_template driver_algs[] = {
> > /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
> > { .type = CRYPTO_ALG_TYPE_AEAD,
> > @@ -2998,14 +2968,8 @@ static struct talitos_alg_template driver_algs[] = {
> > }
> > };
> >
> > -struct talitos_crypto_alg {
> > - struct list_head entry;
> > - struct device *dev;
> > - struct talitos_alg_template algt;
> > -};
> > -
> > -static int talitos_init_common(struct talitos_ctx *ctx,
> > - struct talitos_crypto_alg *talitos_alg)
> > +int talitos_init_common(struct talitos_ctx *ctx,
> > + struct talitos_crypto_alg *talitos_alg)
> > {
> > struct talitos_private *priv;
> >
> > @@ -3066,7 +3030,7 @@ static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
> > return talitos_init_common(ctx, talitos_alg);
> > }
> >
> > -static void talitos_cra_exit(struct crypto_tfm *tfm)
> > +void talitos_cra_exit(struct crypto_tfm *tfm)
> > {
> > struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
> > struct device *dev = ctx->dev;
> > @@ -3080,7 +3044,7 @@ static void talitos_cra_exit(struct crypto_tfm *tfm)
> > * type and primary/secondary execution units required match the hw
> > * capabilities description provided in the device tree node.
> > */
> > -static int hw_supports(struct device *dev, __be32 desc_hdr_template)
> > +int talitos_hw_supports(struct device *dev, __be32 desc_hdr_template)
> > {
> > struct talitos_private *priv = dev_get_drvdata(dev);
> > int ret;
> > @@ -3117,7 +3081,7 @@ static void talitos_remove(struct platform_device *ofdev)
> > list_del(&t_alg->entry);
> > }
> >
> > - if (hw_supports(dev, DESC_HDR_SEL0_RNG))
> > + if (talitos_hw_supports(dev, DESC_HDR_SEL0_RNG))
> > talitos_unregister_rng(dev);
> >
> > for (i = 0; i < 2; i++)
> > @@ -3426,7 +3390,7 @@ static int talitos_probe(struct platform_device *ofdev)
> > }
> >
> > /* register the RNG, if available */
> > - if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
> > + if (talitos_hw_supports(dev, DESC_HDR_SEL0_RNG)) {
> > err = talitos_register_rng(dev);
> > if (err) {
> > dev_err(dev, "failed to register hwrng: %d\n", err);
> > @@ -3437,7 +3401,8 @@ static int talitos_probe(struct platform_device *ofdev)
> >
> > /* register crypto algorithms the device supports */
> > for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
> > - if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
> > + if (talitos_hw_supports(dev,
> > + driver_algs[i].desc_hdr_template)) {
> > struct talitos_crypto_alg *t_alg;
> > struct crypto_alg *alg = NULL;
> >
> > diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
> > index fa8c71b1f90f..1f81d336dae8 100644
> > --- a/drivers/crypto/talitos/talitos.h
> > +++ b/drivers/crypto/talitos/talitos.h
> > @@ -5,7 +5,13 @@
> > * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
> > */
> >
> > +#include <crypto/aes.h>
> > +#include <crypto/internal/aead.h>
> > +#include <crypto/internal/hash.h>
> > +#include <crypto/internal/skcipher.h>
> > +#include <crypto/sha2.h>
> > #include <linux/device.h>
> > +#include <linux/dma-mapping.h>
> > #include <linux/hw_random.h>
> > #include <linux/interrupt.h>
> > #include <linux/scatterlist.h>
> > @@ -19,6 +25,13 @@
> > #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
> > #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
> >
> > +#ifdef CONFIG_CRYPTO_DEV_TALITOS2
> > +#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE)
> > +#else
> > +#define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA256_BLOCK_SIZE)
> > +#endif
> > +#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
> > +
> > /* descriptor pointer entry */
> > struct talitos_ptr {
> > union {
> > @@ -174,6 +187,35 @@ struct talitos_private {
> >
> > };
> >
> > +struct talitos_ctx {
> > + struct device *dev;
> > + int ch;
> > + __be32 desc_hdr_template;
> > + u8 key[TALITOS_MAX_KEY_SIZE];
> > + u8 iv[TALITOS_MAX_IV_LENGTH];
> > + dma_addr_t dma_key;
> > + unsigned int keylen;
> > + unsigned int enckeylen;
> > + unsigned int authkeylen;
> > +};
> > +
> > +struct talitos_alg_template {
> > + u32 type;
> > + u32 priority;
> > + union {
> > + struct skcipher_alg skcipher;
> > + struct ahash_alg hash;
> > + struct aead_alg aead;
> > + } alg;
> > + __be32 desc_hdr_template;
> > +};
> > +
> > +struct talitos_crypto_alg {
> > + struct list_head entry;
> > + struct device *dev;
> > + struct talitos_alg_template algt;
> > +};
> > +
> > /* .features flag */
> > #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
> > #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
> > @@ -432,6 +474,55 @@ static inline bool has_ftr_sec1(struct talitos_private *priv)
> > #define DESC_PTR_LNKTBL_RET 0x02
> > #define DESC_PTR_LNKTBL_NEXT 0x01
> >
> > +void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
> > + unsigned int len, bool is_sec1);
> > +void copy_talitos_ptr(struct talitos_ptr *dst_ptr, struct talitos_ptr *src_ptr,
> > + bool is_sec1);
> > +unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr, bool is_sec1);
> > +void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val, bool is_sec1);
> > +void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1);
> > +
> > +void map_single_talitos_ptr(struct device *dev, struct talitos_ptr *ptr,
> > + unsigned int len, void *data,
> > + enum dma_data_direction dir);
> > +void map_single_talitos_ptr_nosync(struct device *dev, struct talitos_ptr *ptr,
> > + unsigned int len, void *data,
> > + enum dma_data_direction dir);
> > +void unmap_single_talitos_ptr(struct device *dev, struct talitos_ptr *ptr,
> > + enum dma_data_direction dir);
> > +
> > +int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
> > + void (*callback)(struct device *dev,
> > + struct talitos_desc *desc, void *context,
> > + int error),
> > + void *context);
> > +
> > +void talitos_sg_unmap(struct device *dev, struct talitos_edesc *edesc,
> > + struct scatterlist *src, struct scatterlist *dst,
> > + unsigned int len, unsigned int offset);
> > +int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
> > + unsigned int len, struct talitos_edesc *edesc,
> > + struct talitos_ptr *ptr, int sg_count,
> > + unsigned int offset, int tbl_off, int elen, bool force,
> > + int align);
> > +int talitos_sg_map(struct device *dev, struct scatterlist *src,
> > + unsigned int len, struct talitos_edesc *edesc,
> > + struct talitos_ptr *ptr, int sg_count, unsigned int offset,
> > + int tbl_off);
> > +
> > +struct talitos_edesc *
> > +talitos_edesc_alloc(struct device *dev, struct scatterlist *src,
> > + struct scatterlist *dst, u8 *iv, unsigned int assoclen,
> > + unsigned int cryptlen, unsigned int authsize,
> > + unsigned int ivsize, int icv_stashing, u32 cryptoflags,
> > + bool encrypt);
> > +
> > +int talitos_hw_supports(struct device *dev, __be32 desc_hdr_template);
> > +
> > +int talitos_init_common(struct talitos_ctx *ctx,
> > + struct talitos_crypto_alg *talitos_alg);
> > +void talitos_cra_exit(struct crypto_tfm *tfm);
> > +
> > /* Hardware RNG */
> >
> > int talitos_register_rng(struct device *dev);
> >
>
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 06/29] crypto: talitos - Introduce registration helper
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (4 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 05/29] crypto: talitos - Prepare crypto implementation file splitting Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 07/29] crypto: talitos/hash - Move into separate file Paul Louvel
` (22 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Add talitos_register_common() that will be called in each respective
crypto implementation file.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 53 ++++++++++++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.h | 3 +++
2 files changed, 56 insertions(+)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 3fc1069062da..869739dcc4d7 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -3095,6 +3095,59 @@ static void talitos_remove(struct platform_device *ofdev)
tasklet_kill(&priv->done_task[1]);
}
+static void talitos_alg_set_common(struct talitos_private *priv,
+ struct crypto_alg *alg, u32 custom_priority,
+ u32 type)
+{
+ alg->cra_module = THIS_MODULE;
+ if (custom_priority)
+ alg->cra_priority = custom_priority;
+ else
+ alg->cra_priority = TALITOS_CRA_PRIORITY;
+ if (has_ftr_sec1(priv) && type != CRYPTO_ALG_TYPE_AHASH)
+ alg->cra_alignmask = 3;
+ else
+ alg->cra_alignmask = 0;
+ alg->cra_ctxsize = sizeof(struct talitos_ctx);
+ alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
+}
+
+int talitos_register_common(struct device *dev,
+ struct talitos_alg_template *template)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ struct talitos_crypto_alg *t_alg;
+ struct crypto_alg *alg;
+ int ret;
+
+ t_alg = devm_kzalloc(dev, sizeof(struct talitos_crypto_alg),
+ GFP_KERNEL);
+ if (!t_alg)
+ return -ENOMEM;
+
+ t_alg->algt = *template;
+
+ switch (t_alg->algt.type) {
+ default:
+ dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
+ devm_kfree(dev, t_alg);
+ return -EINVAL;
+ }
+
+ if (ret) {
+ dev_err(dev, "%s alg registration failed\n",
+ alg->cra_driver_name);
+ devm_kfree(dev, t_alg);
+ return 0;
+ }
+
+ t_alg->dev = dev;
+
+ list_add_tail(&t_alg->entry, &priv->alg_list);
+
+ return 0;
+}
+
static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
struct talitos_alg_template
*template)
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 1f81d336dae8..afed9947f4c0 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -523,6 +523,9 @@ int talitos_init_common(struct talitos_ctx *ctx,
struct talitos_crypto_alg *talitos_alg);
void talitos_cra_exit(struct crypto_tfm *tfm);
+int talitos_register_common(struct device *dev,
+ struct talitos_alg_template *template);
+
/* Hardware RNG */
int talitos_register_rng(struct device *dev);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 07/29] crypto: talitos/hash - Move into separate file
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (5 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 06/29] crypto: talitos - Introduce registration helper Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 08/29] crypto: talitos/skcipher " Paul Louvel
` (21 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Move the ahash algorithm implementations from talitos.c into a dedicated
talitos-hash.c file.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/Makefile | 2 +-
drivers/crypto/talitos/talitos-hash.c | 832 ++++++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.c | 807 +--------------------------------
drivers/crypto/talitos/talitos.h | 4 +
4 files changed, 847 insertions(+), 798 deletions(-)
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
index 901ec681f010..40d37f9364ef 100644
--- a/drivers/crypto/talitos/Makefile
+++ b/drivers/crypto/talitos/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
-talitos-y := talitos.o talitos-rng.o
+talitos-y := talitos.o talitos-rng.o talitos-hash.o
diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos/talitos-hash.c
new file mode 100644
index 000000000000..5792e7093392
--- /dev/null
+++ b/drivers/crypto/talitos/talitos-hash.c
@@ -0,0 +1,832 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Freescale SEC (talitos) hash implementation
+ *
+ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <linux/scatterlist.h>
+
+#include <crypto/hash.h>
+#include <crypto/internal/hash.h>
+#include <crypto/md5.h>
+#include <crypto/scatterwalk.h>
+#include <crypto/sha1.h>
+
+#include "talitos.h"
+
+#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
+#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
+
+struct talitos_ahash_req_ctx {
+ u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
+ unsigned int hw_context_size;
+ unsigned int swinit;
+ unsigned int first_request;
+ unsigned int last_request;
+ unsigned int to_hash_later;
+};
+
+struct talitos_export_state {
+ u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
+ unsigned int swinit;
+ unsigned int first_request;
+ unsigned int last_request;
+ unsigned int to_hash_later;
+};
+
+static void common_nonsnoop_hash_unmap(struct device *dev,
+ struct talitos_edesc *edesc,
+ struct ahash_request *areq)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+ struct talitos_desc *desc = &edesc->desc;
+
+ unmap_single_talitos_ptr(dev, &desc->ptr[5], DMA_FROM_DEVICE);
+
+ if (edesc->last && req_ctx->last_request)
+ memcpy(areq->result, req_ctx->hw_context,
+ crypto_ahash_digestsize(tfm));
+
+ if (edesc->src)
+ talitos_sg_unmap(dev, edesc, edesc->src, NULL, 0, 0);
+
+ /* When using hashctx-in, must unmap it. */
+ if (from_talitos_ptr_len(&desc->ptr[1], is_sec1))
+ unmap_single_talitos_ptr(dev, &desc->ptr[1],
+ DMA_TO_DEVICE);
+
+ if (edesc->dma_len)
+ dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
+ DMA_BIDIRECTIONAL);
+}
+
+static void free_edesc_list_from(struct ahash_request *areq, struct talitos_edesc *edesc)
+{
+ struct talitos_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
+ struct talitos_edesc *next;
+
+ while (edesc) {
+ next = edesc->next_desc;
+ common_nonsnoop_hash_unmap(ctx->dev, edesc, areq);
+ kfree(edesc);
+ edesc = next;
+ }
+}
+
+static void ahash_done(struct device *dev,
+ struct talitos_desc *desc, void *context,
+ int err)
+{
+ struct ahash_request *areq = context;
+ struct talitos_edesc *edesc =
+ container_of(desc, struct talitos_edesc, desc);
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ bool is_sec1 = has_ftr_sec1(dev_get_drvdata(dev));
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct talitos_edesc *next;
+
+ if (is_sec1) {
+ free_edesc_list_from(areq, edesc);
+ ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
+ } else {
+ next = edesc->next_desc;
+
+ common_nonsnoop_hash_unmap(dev, edesc, areq);
+ kfree(edesc);
+
+ if (err)
+ goto out;
+
+ if (next) {
+ err = talitos_submit(dev, ctx->ch, &next->desc,
+ ahash_done, areq);
+ if (err != -EINPROGRESS)
+ goto out;
+ return;
+ }
+out:
+ if (err && next)
+ free_edesc_list_from(areq, next);
+ ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
+ }
+}
+
+/*
+ * SEC1 doesn't like hashing of 0 sized message, so we do the padding
+ * ourself and submit a padded block
+ */
+static void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
+ struct talitos_edesc *edesc,
+ struct talitos_ptr *ptr)
+{
+ static u8 padded_hash[64] = {
+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ };
+
+ pr_err_once("Bug in SEC1, padding ourself\n");
+ edesc->desc.hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
+ map_single_talitos_ptr(ctx->dev, ptr, sizeof(padded_hash),
+ (char *)padded_hash, DMA_TO_DEVICE);
+}
+
+static void common_nonsnoop_hash(struct talitos_edesc *edesc,
+ struct ahash_request *areq,
+ unsigned int length)
+{
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct device *dev = ctx->dev;
+ struct talitos_desc *desc = &edesc->desc;
+ bool sync_needed = false;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+ int sg_count;
+
+ /* first DWORD empty */
+
+ /* hash context in */
+ if (!edesc->first || !req_ctx->first_request || req_ctx->swinit) {
+ map_single_talitos_ptr_nosync(dev, &desc->ptr[1],
+ req_ctx->hw_context_size,
+ req_ctx->hw_context,
+ DMA_TO_DEVICE);
+ req_ctx->swinit = 0;
+ }
+ /* Indicate next op is not the first. */
+ req_ctx->first_request = 0;
+
+ /* HMAC key */
+ if (ctx->keylen)
+ to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen,
+ is_sec1);
+
+ sg_count = edesc->src_nents ?: 1;
+ if (is_sec1 && sg_count > 1)
+ sg_copy_to_buffer(edesc->src, sg_count, edesc->buf, length);
+ else if (length)
+ sg_count = dma_map_sg(dev, edesc->src, sg_count, DMA_TO_DEVICE);
+
+ /*
+ * data in
+ */
+ sg_count = talitos_sg_map(dev, edesc->src, length, edesc, &desc->ptr[3],
+ sg_count, 0, 0);
+ if (sg_count > 1)
+ sync_needed = true;
+
+ /* fifth DWORD empty */
+
+ /* hash/HMAC out -or- hash context out */
+ if (edesc->last && req_ctx->last_request)
+ map_single_talitos_ptr(dev, &desc->ptr[5],
+ crypto_ahash_digestsize(tfm),
+ req_ctx->hw_context, DMA_FROM_DEVICE);
+ else
+ map_single_talitos_ptr_nosync(dev, &desc->ptr[5],
+ req_ctx->hw_context_size,
+ req_ctx->hw_context,
+ DMA_FROM_DEVICE);
+
+ /* last DWORD empty */
+
+ if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) == 0)
+ talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
+
+ if (sync_needed)
+ dma_sync_single_for_device(dev, edesc->dma_link_tbl,
+ edesc->dma_len, DMA_BIDIRECTIONAL);
+}
+
+static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
+ struct scatterlist *src,
+ unsigned int nbytes)
+{
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+
+ return talitos_edesc_alloc(ctx->dev, src, NULL, NULL, 0,
+ nbytes, 0, 0, 0, areq->base.flags, false);
+}
+
+static struct talitos_edesc *
+ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
+ unsigned int blocksize, bool is_sec1)
+{
+ struct talitos_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct talitos_edesc *first = NULL, *prev_edesc = NULL, *edesc;
+ size_t desc_max = is_sec1 ? TALITOS1_MAX_DATA_LEN :
+ TALITOS2_MAX_DATA_LEN;
+ struct scatterlist tmp[2];
+ size_t to_hash_this_desc;
+ struct scatterlist *src;
+ size_t offset = 0;
+
+ do {
+ src = scatterwalk_ffwd(tmp, areq->src, offset);
+
+ to_hash_this_desc =
+ min(nbytes, ALIGN_DOWN(desc_max, blocksize));
+
+ /* Allocate extended descriptor */
+ edesc = ahash_edesc_alloc(areq, src, to_hash_this_desc);
+ if (IS_ERR(edesc)) {
+ if (first)
+ free_edesc_list_from(areq, first);
+ return edesc;
+ }
+
+ edesc->src = scatterwalk_ffwd(edesc->bufsl, areq->src, offset);
+ edesc->desc.hdr = ctx->desc_hdr_template;
+ edesc->first = offset == 0;
+ edesc->last = nbytes - to_hash_this_desc == 0;
+
+ /* On last one, request SEC to pad; otherwise continue */
+ if (req_ctx->last_request && edesc->last)
+ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
+ else
+ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
+
+ /* request SEC to INIT hash. */
+ if (req_ctx->first_request && edesc->first && !req_ctx->swinit)
+ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
+
+ /*
+ * When the tfm context has a keylen, it's an HMAC.
+ * A first or last (ie. not middle) descriptor must request HMAC.
+ */
+ if (ctx->keylen && ((req_ctx->first_request && edesc->first) ||
+ (req_ctx->last_request && edesc->last)))
+ edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
+
+ /* clear the DN bit */
+ if (is_sec1 && !edesc->last)
+ edesc->desc.hdr &= ~DESC_HDR_DONE_NOTIFY;
+
+ common_nonsnoop_hash(edesc, areq, to_hash_this_desc);
+
+ offset += to_hash_this_desc;
+ nbytes -= to_hash_this_desc;
+
+ if (!prev_edesc)
+ first = edesc;
+ else
+ prev_edesc->next_desc = edesc;
+ prev_edesc = edesc;
+ } while (nbytes);
+
+ return first;
+}
+
+static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
+{
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct talitos_edesc *edesc;
+ unsigned int blocksize =
+ crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
+ bool is_sec1 = has_ftr_sec1(dev_get_drvdata(ctx->dev));
+ unsigned int nbytes_to_hash;
+ unsigned int to_hash_later;
+ struct device *dev = ctx->dev;
+ int ret;
+
+ nbytes_to_hash = ALIGN_DOWN(nbytes, blocksize);
+ to_hash_later = nbytes - nbytes_to_hash;
+
+ if (req_ctx->last_request) {
+ nbytes_to_hash = nbytes;
+ to_hash_later = 0;
+ }
+
+ req_ctx->to_hash_later = to_hash_later;
+
+ edesc = ahash_process_req_prepare(areq, nbytes_to_hash, blocksize,
+ is_sec1);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+ ret = talitos_submit(dev, ctx->ch, &edesc->desc, ahash_done, areq);
+ if (ret != -EINPROGRESS)
+ free_edesc_list_from(areq, edesc);
+
+ return ret;
+}
+
+static int ahash_init(struct ahash_request *areq)
+{
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct device *dev = ctx->dev;
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ unsigned int size;
+ dma_addr_t dma;
+
+ /* Initialize the context */
+ req_ctx->first_request = 1;
+ req_ctx->swinit = 0; /* assume h/w init of context */
+ size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
+ ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
+ : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
+ req_ctx->hw_context_size = size;
+ req_ctx->last_request = 0;
+
+ dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
+ DMA_TO_DEVICE);
+ dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
+
+ return 0;
+}
+
+/*
+ * on h/w without explicit sha224 support, we initialize h/w context
+ * manually with sha224 constants, and tell it to run sha256.
+ */
+static int ahash_init_sha224_swinit(struct ahash_request *areq)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+
+ req_ctx->hw_context[0] = SHA224_H0;
+ req_ctx->hw_context[1] = SHA224_H1;
+ req_ctx->hw_context[2] = SHA224_H2;
+ req_ctx->hw_context[3] = SHA224_H3;
+ req_ctx->hw_context[4] = SHA224_H4;
+ req_ctx->hw_context[5] = SHA224_H5;
+ req_ctx->hw_context[6] = SHA224_H6;
+ req_ctx->hw_context[7] = SHA224_H7;
+
+ /* init 64-bit count */
+ req_ctx->hw_context[8] = 0;
+ req_ctx->hw_context[9] = 0;
+
+ ahash_init(areq);
+ req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
+
+ return 0;
+}
+
+static int ahash_update(struct ahash_request *areq)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+
+ req_ctx->last_request = 0;
+
+ return ahash_process_req(areq, areq->nbytes);
+}
+
+static int ahash_final(struct ahash_request *areq)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+
+ req_ctx->last_request = 1;
+
+ return ahash_process_req(areq, 0);
+}
+
+static int ahash_finup(struct ahash_request *areq)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+
+ req_ctx->last_request = 1;
+
+ return ahash_process_req(areq, areq->nbytes);
+}
+
+static int ahash_digest(struct ahash_request *areq)
+{
+ ahash_init(areq);
+ return ahash_finup(areq);
+}
+
+static int ahash_digest_sha224_swinit(struct ahash_request *areq)
+{
+ ahash_init_sha224_swinit(areq);
+ return ahash_finup(areq);
+}
+
+static int ahash_export(struct ahash_request *areq, void *out)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct talitos_export_state *export = out;
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct device *dev = ctx->dev;
+ dma_addr_t dma;
+
+ dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
+ DMA_FROM_DEVICE);
+ dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_FROM_DEVICE);
+
+ memcpy(export->hw_context, req_ctx->hw_context,
+ req_ctx->hw_context_size);
+ export->swinit = req_ctx->swinit;
+ export->first_request = req_ctx->first_request;
+ export->last_request = req_ctx->last_request;
+ export->to_hash_later = req_ctx->to_hash_later;
+
+ return 0;
+}
+
+static int ahash_import(struct ahash_request *areq, const void *in)
+{
+ struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
+ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
+ struct device *dev = ctx->dev;
+ const struct talitos_export_state *export = in;
+ unsigned int size;
+ dma_addr_t dma;
+
+ memset(req_ctx, 0, sizeof(*req_ctx));
+ size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
+ ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
+ : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
+ req_ctx->hw_context_size = size;
+ memcpy(req_ctx->hw_context, export->hw_context, size);
+ req_ctx->swinit = export->swinit;
+ req_ctx->first_request = export->first_request;
+ req_ctx->last_request = export->last_request;
+ req_ctx->to_hash_later = export->to_hash_later;
+
+ dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
+ DMA_TO_DEVICE);
+ dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
+
+ return 0;
+}
+
+static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
+ u8 *hash)
+{
+ struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
+
+ struct scatterlist sg[1];
+ struct ahash_request *req;
+ struct crypto_wait wait;
+ int ret;
+
+ crypto_init_wait(&wait);
+
+ req = ahash_request_alloc(tfm, GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ /* Keep tfm keylen == 0 during hash of the long key */
+ ctx->keylen = 0;
+ ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
+ crypto_req_done, &wait);
+
+ sg_init_one(&sg[0], key, keylen);
+
+ ahash_request_set_crypt(req, sg, hash, keylen);
+ ret = crypto_wait_req(crypto_ahash_digest(req), &wait);
+
+ ahash_request_free(req);
+
+ return ret;
+}
+
+static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
+ unsigned int keylen)
+{
+ struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
+ struct device *dev = ctx->dev;
+ unsigned int blocksize =
+ crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
+ unsigned int digestsize = crypto_ahash_digestsize(tfm);
+ unsigned int keysize = keylen;
+ u8 hash[SHA512_DIGEST_SIZE];
+ int ret;
+
+ if (keylen <= blocksize)
+ memcpy(ctx->key, key, keysize);
+ else {
+ /* Must get the hash of the long key */
+ ret = keyhash(tfm, key, keylen, hash);
+
+ if (ret)
+ return -EINVAL;
+
+ keysize = digestsize;
+ memcpy(ctx->key, hash, digestsize);
+ }
+
+ if (ctx->keylen)
+ dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
+
+ ctx->keylen = keysize;
+ ctx->dma_key = dma_map_single(dev, ctx->key, keysize, DMA_TO_DEVICE);
+
+ return 0;
+}
+
+static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
+{
+ struct crypto_alg *alg = tfm->__crt_alg;
+ struct talitos_crypto_alg *talitos_alg;
+ struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
+
+ talitos_alg = container_of(__crypto_ahash_alg(alg),
+ struct talitos_crypto_alg,
+ algt.alg.hash);
+
+ ctx->keylen = 0;
+ sizeof(struct talitos_ahash_req_ctx));
+
+ return talitos_init_common(ctx, talitos_alg);
+}
+
+static struct talitos_alg_template hash_driver_algs[] = {
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = MD5_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "md5",
+ .cra_driver_name = "md5-talitos",
+ .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_MD5,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA1_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "sha1",
+ .cra_driver_name = "sha1-talitos",
+ .cra_blocksize = SHA1_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA1,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA224_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "sha224",
+ .cra_driver_name = "sha224-talitos",
+ .cra_blocksize = SHA224_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA224,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA256_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "sha256",
+ .cra_driver_name = "sha256-talitos",
+ .cra_blocksize = SHA256_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA256,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA384_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "sha384",
+ .cra_driver_name = "sha384-talitos",
+ .cra_blocksize = SHA384_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA384,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA512_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "sha512",
+ .cra_driver_name = "sha512-talitos",
+ .cra_blocksize = SHA512_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA512,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = MD5_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(md5)",
+ .cra_driver_name = "hmac-md5-talitos",
+ .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_MD5,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA1_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(sha1)",
+ .cra_driver_name = "hmac-sha1-talitos",
+ .cra_blocksize = SHA1_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA1,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA224_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(sha224)",
+ .cra_driver_name = "hmac-sha224-talitos",
+ .cra_blocksize = SHA224_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA224,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA256_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(sha256)",
+ .cra_driver_name = "hmac-sha256-talitos",
+ .cra_blocksize = SHA256_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA256,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA384_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(sha384)",
+ .cra_driver_name = "hmac-sha384-talitos",
+ .cra_blocksize = SHA384_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA384,
+ },
+ { .type = CRYPTO_ALG_TYPE_AHASH,
+ .alg.hash = {
+ .halg.digestsize = SHA512_DIGEST_SIZE,
+ .halg.statesize = sizeof(struct talitos_export_state),
+ .halg.base = {
+ .cra_name = "hmac(sha512)",
+ .cra_driver_name = "hmac-sha512-talitos",
+ .cra_blocksize = SHA512_BLOCK_SIZE,
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ }
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA512,
+ }
+};
+
+int talitos_register_hash(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ struct ahash_alg *ahash_alg;
+ struct crypto_alg *alg;
+ size_t i;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(hash_driver_algs); i++) {
+ if (!talitos_hw_supports(dev,
+ hash_driver_algs[i].desc_hdr_template))
+ continue;
+
+ ahash_alg = &hash_driver_algs[i].alg.hash;
+ alg = &ahash_alg->halg.base;
+
+ alg->cra_init = talitos_cra_init_ahash;
+ alg->cra_exit = talitos_cra_exit;
+ ahash_alg->init = ahash_init;
+ ahash_alg->update = ahash_update;
+ ahash_alg->final = ahash_final;
+ ahash_alg->finup = ahash_finup;
+ ahash_alg->digest = ahash_digest;
+ if (!strncmp(alg->cra_name, "hmac", 4))
+ ahash_alg->setkey = ahash_setkey;
+ ahash_alg->import = ahash_import;
+ ahash_alg->export = ahash_export;
+
+ if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
+ !strncmp(alg->cra_name, "hmac", 4)) {
+ /* not supported */
+ continue;
+ }
+
+ if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
+ (!strcmp(alg->cra_name, "sha224") ||
+ !strcmp(alg->cra_name, "hmac(sha224)"))) {
+ ahash_alg->init = ahash_init_sha224_swinit;
+ ahash_alg->digest = ahash_digest_sha224_swinit;
+ hash_driver_algs[i].desc_hdr_template =
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA256;
+ }
+
+ ret = talitos_register_common(dev, &hash_driver_algs[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 869739dcc4d7..b8bcb970d7d5 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -831,26 +831,6 @@ DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
*/
#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
-#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
-#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
-
-struct talitos_ahash_req_ctx {
- u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
- unsigned int hw_context_size;
- unsigned int swinit;
- unsigned int first_request;
- unsigned int last_request;
- unsigned int to_hash_later;
-};
-
-struct talitos_export_state {
- u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
- unsigned int swinit;
- unsigned int first_request;
- unsigned int last_request;
- unsigned int to_hash_later;
-};
-
static int aead_setkey(struct crypto_aead *authenc,
const u8 *key, unsigned int keylen)
{
@@ -1659,501 +1639,6 @@ static int skcipher_decrypt(struct skcipher_request *areq)
return common_nonsnoop(edesc, areq, skcipher_done);
}
-static void common_nonsnoop_hash_unmap(struct device *dev,
- struct talitos_edesc *edesc,
- struct ahash_request *areq)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
- struct talitos_desc *desc = &edesc->desc;
-
- unmap_single_talitos_ptr(dev, &desc->ptr[5], DMA_FROM_DEVICE);
-
- if (edesc->last && req_ctx->last_request)
- memcpy(areq->result, req_ctx->hw_context,
- crypto_ahash_digestsize(tfm));
-
- if (edesc->src)
- talitos_sg_unmap(dev, edesc, edesc->src, NULL, 0, 0);
-
- /* When using hashctx-in, must unmap it. */
- if (from_talitos_ptr_len(&desc->ptr[1], is_sec1))
- unmap_single_talitos_ptr(dev, &desc->ptr[1],
- DMA_TO_DEVICE);
-
- if (edesc->dma_len)
- dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
- DMA_BIDIRECTIONAL);
-}
-
-static void free_edesc_list_from(struct ahash_request *areq, struct talitos_edesc *edesc)
-{
- struct talitos_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
- struct talitos_edesc *next;
-
- while (edesc) {
- next = edesc->next_desc;
- common_nonsnoop_hash_unmap(ctx->dev, edesc, areq);
- kfree(edesc);
- edesc = next;
- }
-}
-
-static void ahash_done(struct device *dev,
- struct talitos_desc *desc, void *context,
- int err)
-{
- struct ahash_request *areq = context;
- struct talitos_edesc *edesc =
- container_of(desc, struct talitos_edesc, desc);
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- bool is_sec1 = has_ftr_sec1(dev_get_drvdata(dev));
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct talitos_edesc *next;
-
- if (is_sec1) {
- free_edesc_list_from(areq, edesc);
- ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
- } else {
- next = edesc->next_desc;
-
- common_nonsnoop_hash_unmap(dev, edesc, areq);
- kfree(edesc);
-
- if (err)
- goto out;
-
- if (next) {
- err = talitos_submit(dev, ctx->ch, &next->desc,
- ahash_done, areq);
- if (err != -EINPROGRESS)
- goto out;
- return;
- }
-out:
- if (err && next)
- free_edesc_list_from(areq, next);
- ahash_request_complete(areq, err ?: req_ctx->to_hash_later);
- }
-}
-
-/*
- * SEC1 doesn't like hashing of 0 sized message, so we do the padding
- * ourself and submit a padded block
- */
-static void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
- struct talitos_edesc *edesc,
- struct talitos_ptr *ptr)
-{
- static u8 padded_hash[64] = {
- 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- };
-
- pr_err_once("Bug in SEC1, padding ourself\n");
- edesc->desc.hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
- map_single_talitos_ptr(ctx->dev, ptr, sizeof(padded_hash),
- (char *)padded_hash, DMA_TO_DEVICE);
-}
-
-static void common_nonsnoop_hash(struct talitos_edesc *edesc,
- struct ahash_request *areq,
- unsigned int length)
-{
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct device *dev = ctx->dev;
- struct talitos_desc *desc = &edesc->desc;
- bool sync_needed = false;
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
- int sg_count;
-
- /* first DWORD empty */
-
- /* hash context in */
- if (!edesc->first || !req_ctx->first_request || req_ctx->swinit) {
- map_single_talitos_ptr_nosync(dev, &desc->ptr[1],
- req_ctx->hw_context_size,
- req_ctx->hw_context,
- DMA_TO_DEVICE);
- req_ctx->swinit = 0;
- }
- /* Indicate next op is not the first. */
- req_ctx->first_request = 0;
-
- /* HMAC key */
- if (ctx->keylen)
- to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen,
- is_sec1);
-
- sg_count = edesc->src_nents ?: 1;
- if (is_sec1 && sg_count > 1)
- sg_copy_to_buffer(edesc->src, sg_count, edesc->buf, length);
- else if (length)
- sg_count = dma_map_sg(dev, edesc->src, sg_count, DMA_TO_DEVICE);
-
- /*
- * data in
- */
- sg_count = talitos_sg_map(dev, edesc->src, length, edesc, &desc->ptr[3],
- sg_count, 0, 0);
- if (sg_count > 1)
- sync_needed = true;
-
- /* fifth DWORD empty */
-
- /* hash/HMAC out -or- hash context out */
- if (edesc->last && req_ctx->last_request)
- map_single_talitos_ptr(dev, &desc->ptr[5],
- crypto_ahash_digestsize(tfm),
- req_ctx->hw_context, DMA_FROM_DEVICE);
- else
- map_single_talitos_ptr_nosync(dev, &desc->ptr[5],
- req_ctx->hw_context_size,
- req_ctx->hw_context,
- DMA_FROM_DEVICE);
-
- /* last DWORD empty */
-
- if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) == 0)
- talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
-
- if (sync_needed)
- dma_sync_single_for_device(dev, edesc->dma_link_tbl,
- edesc->dma_len, DMA_BIDIRECTIONAL);
-}
-
-static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
- struct scatterlist *src,
- unsigned int nbytes)
-{
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
-
- return talitos_edesc_alloc(ctx->dev, src, NULL, NULL, 0,
- nbytes, 0, 0, 0, areq->base.flags, false);
-}
-
-static struct talitos_edesc *
-ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
- unsigned int blocksize, bool is_sec1)
-{
- struct talitos_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct talitos_edesc *first = NULL, *prev_edesc = NULL, *edesc;
- size_t desc_max = is_sec1 ? TALITOS1_MAX_DATA_LEN :
- TALITOS2_MAX_DATA_LEN;
- struct scatterlist tmp[2];
- size_t to_hash_this_desc;
- struct scatterlist *src;
- size_t offset = 0;
-
- do {
- src = scatterwalk_ffwd(tmp, areq->src, offset);
-
- to_hash_this_desc =
- min(nbytes, ALIGN_DOWN(desc_max, blocksize));
-
- /* Allocate extended descriptor */
- edesc = ahash_edesc_alloc(areq, src, to_hash_this_desc);
- if (IS_ERR(edesc)) {
- if (first)
- free_edesc_list_from(areq, first);
- return edesc;
- }
-
- edesc->src = scatterwalk_ffwd(edesc->bufsl, areq->src, offset);
- edesc->desc.hdr = ctx->desc_hdr_template;
- edesc->first = offset == 0;
- edesc->last = nbytes - to_hash_this_desc == 0;
-
- /* On last one, request SEC to pad; otherwise continue */
- if (req_ctx->last_request && edesc->last)
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
- else
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
-
- /* request SEC to INIT hash. */
- if (req_ctx->first_request && edesc->first && !req_ctx->swinit)
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
-
- /*
- * When the tfm context has a keylen, it's an HMAC.
- * A first or last (ie. not middle) descriptor must request HMAC.
- */
- if (ctx->keylen && ((req_ctx->first_request && edesc->first) ||
- (req_ctx->last_request && edesc->last)))
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
-
- /* clear the DN bit */
- if (is_sec1 && !edesc->last)
- edesc->desc.hdr &= ~DESC_HDR_DONE_NOTIFY;
-
- common_nonsnoop_hash(edesc, areq, to_hash_this_desc);
-
- offset += to_hash_this_desc;
- nbytes -= to_hash_this_desc;
-
- if (!prev_edesc)
- first = edesc;
- else
- prev_edesc->next_desc = edesc;
- prev_edesc = edesc;
- } while (nbytes);
-
- return first;
-}
-
-static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
-{
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct talitos_edesc *edesc;
- unsigned int blocksize =
- crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
- bool is_sec1 = has_ftr_sec1(dev_get_drvdata(ctx->dev));
- unsigned int nbytes_to_hash;
- unsigned int to_hash_later;
- struct device *dev = ctx->dev;
- int ret;
-
- nbytes_to_hash = ALIGN_DOWN(nbytes, blocksize);
- to_hash_later = nbytes - nbytes_to_hash;
-
- if (req_ctx->last_request) {
- nbytes_to_hash = nbytes;
- to_hash_later = 0;
- }
-
- req_ctx->to_hash_later = to_hash_later;
-
- edesc = ahash_process_req_prepare(areq, nbytes_to_hash, blocksize,
- is_sec1);
- if (IS_ERR(edesc))
- return PTR_ERR(edesc);
-
- ret = talitos_submit(dev, ctx->ch, &edesc->desc, ahash_done, areq);
- if (ret != -EINPROGRESS)
- free_edesc_list_from(areq, edesc);
-
- return ret;
-}
-
-static int ahash_init(struct ahash_request *areq)
-{
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct device *dev = ctx->dev;
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- unsigned int size;
- dma_addr_t dma;
-
- /* Initialize the context */
- req_ctx->first_request = 1;
- req_ctx->swinit = 0; /* assume h/w init of context */
- size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
- ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
- : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
- req_ctx->hw_context_size = size;
- req_ctx->last_request = 0;
-
- dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
- DMA_TO_DEVICE);
- dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
-
- return 0;
-}
-
-/*
- * on h/w without explicit sha224 support, we initialize h/w context
- * manually with sha224 constants, and tell it to run sha256.
- */
-static int ahash_init_sha224_swinit(struct ahash_request *areq)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
-
- req_ctx->hw_context[0] = SHA224_H0;
- req_ctx->hw_context[1] = SHA224_H1;
- req_ctx->hw_context[2] = SHA224_H2;
- req_ctx->hw_context[3] = SHA224_H3;
- req_ctx->hw_context[4] = SHA224_H4;
- req_ctx->hw_context[5] = SHA224_H5;
- req_ctx->hw_context[6] = SHA224_H6;
- req_ctx->hw_context[7] = SHA224_H7;
-
- /* init 64-bit count */
- req_ctx->hw_context[8] = 0;
- req_ctx->hw_context[9] = 0;
-
- ahash_init(areq);
- req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
-
- return 0;
-}
-
-static int ahash_update(struct ahash_request *areq)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
-
- req_ctx->last_request = 0;
-
- return ahash_process_req(areq, areq->nbytes);
-}
-
-static int ahash_final(struct ahash_request *areq)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
-
- req_ctx->last_request = 1;
-
- return ahash_process_req(areq, 0);
-}
-
-static int ahash_finup(struct ahash_request *areq)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
-
- req_ctx->last_request = 1;
-
- return ahash_process_req(areq, areq->nbytes);
-}
-
-static int ahash_digest(struct ahash_request *areq)
-{
- ahash_init(areq);
- return ahash_finup(areq);
-}
-
-static int ahash_digest_sha224_swinit(struct ahash_request *areq)
-{
- ahash_init_sha224_swinit(areq);
- return ahash_finup(areq);
-}
-
-static int ahash_export(struct ahash_request *areq, void *out)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct talitos_export_state *export = out;
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct device *dev = ctx->dev;
- dma_addr_t dma;
-
- dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
- DMA_FROM_DEVICE);
- dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_FROM_DEVICE);
-
- memcpy(export->hw_context, req_ctx->hw_context,
- req_ctx->hw_context_size);
- export->swinit = req_ctx->swinit;
- export->first_request = req_ctx->first_request;
- export->last_request = req_ctx->last_request;
- export->to_hash_later = req_ctx->to_hash_later;
-
- return 0;
-}
-
-static int ahash_import(struct ahash_request *areq, const void *in)
-{
- struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
- struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- struct device *dev = ctx->dev;
- const struct talitos_export_state *export = in;
- unsigned int size;
- dma_addr_t dma;
-
- memset(req_ctx, 0, sizeof(*req_ctx));
- size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
- ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
- : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
- req_ctx->hw_context_size = size;
- memcpy(req_ctx->hw_context, export->hw_context, size);
- req_ctx->swinit = export->swinit;
- req_ctx->first_request = export->first_request;
- req_ctx->last_request = export->last_request;
- req_ctx->to_hash_later = export->to_hash_later;
-
- dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
- DMA_TO_DEVICE);
- dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
-
- return 0;
-}
-
-static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
- u8 *hash)
-{
- struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
-
- struct scatterlist sg[1];
- struct ahash_request *req;
- struct crypto_wait wait;
- int ret;
-
- crypto_init_wait(&wait);
-
- req = ahash_request_alloc(tfm, GFP_KERNEL);
- if (!req)
- return -ENOMEM;
-
- /* Keep tfm keylen == 0 during hash of the long key */
- ctx->keylen = 0;
- ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
- crypto_req_done, &wait);
-
- sg_init_one(&sg[0], key, keylen);
-
- ahash_request_set_crypt(req, sg, hash, keylen);
- ret = crypto_wait_req(crypto_ahash_digest(req), &wait);
-
- ahash_request_free(req);
-
- return ret;
-}
-
-static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
- unsigned int keylen)
-{
- struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
- struct device *dev = ctx->dev;
- unsigned int blocksize =
- crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
- unsigned int digestsize = crypto_ahash_digestsize(tfm);
- unsigned int keysize = keylen;
- u8 hash[SHA512_DIGEST_SIZE];
- int ret;
-
- if (keylen <= blocksize)
- memcpy(ctx->key, key, keysize);
- else {
- /* Must get the hash of the long key */
- ret = keyhash(tfm, key, keylen, hash);
-
- if (ret)
- return -EINVAL;
-
- keysize = digestsize;
- memcpy(ctx->key, hash, digestsize);
- }
-
- if (ctx->keylen)
- dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
-
- ctx->keylen = keysize;
- ctx->dma_key = dma_map_single(dev, ctx->key, keysize, DMA_TO_DEVICE);
-
- return 0;
-}
-
static struct talitos_alg_template driver_algs[] = {
/* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
{ .type = CRYPTO_ALG_TYPE_AEAD,
@@ -2737,235 +2222,6 @@ static struct talitos_alg_template driver_algs[] = {
DESC_HDR_MODE0_DEU_CBC |
DESC_HDR_MODE0_DEU_3DES,
},
- /* AHASH algorithms. */
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = MD5_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "md5",
- .cra_driver_name = "md5-talitos",
- .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_MD5,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA1_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha1",
- .cra_driver_name = "sha1-talitos",
- .cra_blocksize = SHA1_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA1,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA224_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha224",
- .cra_driver_name = "sha224-talitos",
- .cra_blocksize = SHA224_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA224,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA256_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha256",
- .cra_driver_name = "sha256-talitos",
- .cra_blocksize = SHA256_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA256,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA384_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha384",
- .cra_driver_name = "sha384-talitos",
- .cra_blocksize = SHA384_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA384,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA512_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha512",
- .cra_driver_name = "sha512-talitos",
- .cra_blocksize = SHA512_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA512,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = MD5_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(md5)",
- .cra_driver_name = "hmac-md5-talitos",
- .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_MD5,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA1_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha1)",
- .cra_driver_name = "hmac-sha1-talitos",
- .cra_blocksize = SHA1_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA1,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA224_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha224)",
- .cra_driver_name = "hmac-sha224-talitos",
- .cra_blocksize = SHA224_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA224,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA256_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha256)",
- .cra_driver_name = "hmac-sha256-talitos",
- .cra_blocksize = SHA256_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA256,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA384_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha384)",
- .cra_driver_name = "hmac-sha384-talitos",
- .cra_blocksize = SHA384_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA384,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA512_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha512)",
- .cra_driver_name = "hmac-sha512-talitos",
- .cra_blocksize = SHA512_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA512,
- }
};
int talitos_init_common(struct talitos_ctx *ctx,
@@ -3014,22 +2270,6 @@ static int talitos_cra_init_skcipher(struct crypto_skcipher *tfm)
return talitos_init_common(ctx, talitos_alg);
}
-static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
-{
- struct crypto_alg *alg = tfm->__crt_alg;
- struct talitos_crypto_alg *talitos_alg;
- struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
-
- talitos_alg = container_of(__crypto_ahash_alg(alg),
- struct talitos_crypto_alg,
- algt.alg.hash);
-
- ctx->keylen = 0;
- sizeof(struct talitos_ahash_req_ctx));
-
- return talitos_init_common(ctx, talitos_alg);
-}
-
void talitos_cra_exit(struct crypto_tfm *tfm)
{
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
@@ -3128,6 +2368,12 @@ int talitos_register_common(struct device *dev,
t_alg->algt = *template;
switch (t_alg->algt.type) {
+ case CRYPTO_ALG_TYPE_AHASH:
+ alg = &t_alg->algt.alg.hash.halg.base;
+ talitos_alg_set_common(priv, alg, t_alg->algt.priority,
+ t_alg->algt.type);
+ ret = crypto_register_ahash(&t_alg->algt.alg.hash);
+ break;
default:
dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
devm_kfree(dev, t_alg);
@@ -3193,37 +2439,6 @@ static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
return ERR_PTR(-ENOTSUPP);
}
break;
- case CRYPTO_ALG_TYPE_AHASH:
- alg = &t_alg->algt.alg.hash.halg.base;
- alg->cra_init = talitos_cra_init_ahash;
- alg->cra_exit = talitos_cra_exit;
- t_alg->algt.alg.hash.init = ahash_init;
- t_alg->algt.alg.hash.update = ahash_update;
- t_alg->algt.alg.hash.final = ahash_final;
- t_alg->algt.alg.hash.finup = ahash_finup;
- t_alg->algt.alg.hash.digest = ahash_digest;
- if (!strncmp(alg->cra_name, "hmac", 4))
- t_alg->algt.alg.hash.setkey = ahash_setkey;
- t_alg->algt.alg.hash.import = ahash_import;
- t_alg->algt.alg.hash.export = ahash_export;
-
- if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
- !strncmp(alg->cra_name, "hmac", 4)) {
- devm_kfree(dev, t_alg);
- return ERR_PTR(-ENOTSUPP);
- }
- if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
- (!strcmp(alg->cra_name, "sha224") ||
- !strcmp(alg->cra_name, "hmac(sha224)"))) {
- t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
- t_alg->algt.alg.hash.digest =
- ahash_digest_sha224_swinit;
- t_alg->algt.desc_hdr_template =
- DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA256;
- }
- break;
default:
dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
devm_kfree(dev, t_alg);
@@ -3452,6 +2667,10 @@ static int talitos_probe(struct platform_device *ofdev)
dev_info(dev, "hwrng\n");
}
+ err = talitos_register_hash(dev);
+ if (err)
+ goto err_out;
+
/* register crypto algorithms the device supports */
for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
if (talitos_hw_supports(dev,
@@ -3479,12 +2698,6 @@ static int talitos_probe(struct platform_device *ofdev)
&t_alg->algt.alg.aead);
alg = &t_alg->algt.alg.aead.base;
break;
-
- case CRYPTO_ALG_TYPE_AHASH:
- err = crypto_register_ahash(
- &t_alg->algt.alg.hash);
- alg = &t_alg->algt.alg.hash.halg.base;
- break;
}
if (err) {
dev_err(dev, "%s alg registration failed\n",
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index afed9947f4c0..e703c18cb81f 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -530,3 +530,7 @@ int talitos_register_common(struct device *dev,
int talitos_register_rng(struct device *dev);
void talitos_unregister_rng(struct device *dev);
+
+/* Hash */
+
+int talitos_register_hash(struct device *dev);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 08/29] crypto: talitos/skcipher - Move into separate file
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (6 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 07/29] crypto: talitos/hash - Move into separate file Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 09/29] crypto: talitos/aead " Paul Louvel
` (20 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Move the skcipher algorithm implementations from talitos.c into
a dedicated talitos-skcipher.c file.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/Makefile | 2 +-
drivers/crypto/talitos/talitos-skcipher.c | 396 ++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.c | 377 +---------------------------
drivers/crypto/talitos/talitos.h | 1 +
4 files changed, 408 insertions(+), 368 deletions(-)
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
index 40d37f9364ef..d4f19f2f6375 100644
--- a/drivers/crypto/talitos/Makefile
+++ b/drivers/crypto/talitos/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
-talitos-y := talitos.o talitos-rng.o talitos-hash.o
+talitos-y := talitos.o talitos-rng.o talitos-hash.o talitos-skcipher.o
diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/talitos/talitos-skcipher.c
new file mode 100644
index 000000000000..4f742930ec47
--- /dev/null
+++ b/drivers/crypto/talitos/talitos-skcipher.c
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Freescale SEC (talitos) skcipher implementation
+ *
+ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <crypto/internal/des.h>
+#include <crypto/internal/skcipher.h>
+
+#include "talitos.h"
+
+static void common_nonsnoop_unmap(struct device *dev,
+ struct talitos_edesc *edesc,
+ struct skcipher_request *areq)
+{
+ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
+
+ talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen, 0);
+ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
+
+ if (edesc->dma_len)
+ dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
+ DMA_BIDIRECTIONAL);
+}
+
+static void skcipher_done(struct device *dev,
+ struct talitos_desc *desc, void *context,
+ int err)
+{
+ struct skcipher_request *areq = context;
+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ unsigned int ivsize = crypto_skcipher_ivsize(cipher);
+ struct talitos_edesc *edesc;
+
+ edesc = container_of(desc, struct talitos_edesc, desc);
+
+ common_nonsnoop_unmap(dev, edesc, areq);
+ memcpy(areq->iv, ctx->iv, ivsize);
+
+ kfree(edesc);
+
+ skcipher_request_complete(areq, err);
+}
+
+static int common_nonsnoop(struct talitos_edesc *edesc,
+ struct skcipher_request *areq,
+ void (*callback) (struct device *dev,
+ struct talitos_desc *desc,
+ void *context, int error))
+{
+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ struct device *dev = ctx->dev;
+ struct talitos_desc *desc = &edesc->desc;
+ unsigned int cryptlen = areq->cryptlen;
+ unsigned int ivsize = crypto_skcipher_ivsize(cipher);
+ int sg_count, ret;
+ bool sync_needed = false;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+ bool is_ctr = (desc->hdr & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_AESU &&
+ (desc->hdr & DESC_HDR_MODE0_AESU_MASK) == DESC_HDR_MODE0_AESU_CTR;
+
+ /* first DWORD empty */
+
+ /* cipher iv */
+ to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize, is_sec1);
+
+ /* cipher key */
+ to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, is_sec1);
+
+ sg_count = edesc->src_nents ?: 1;
+ if (is_sec1 && sg_count > 1)
+ sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
+ cryptlen);
+ else
+ sg_count = dma_map_sg(dev, areq->src, sg_count,
+ (areq->src == areq->dst) ?
+ DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
+ /*
+ * cipher in
+ */
+ sg_count = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[3],
+ sg_count, 0, 0, 0, false, is_ctr ? 16 : 1);
+ if (sg_count > 1)
+ sync_needed = true;
+
+ /* cipher out */
+ if (areq->src != areq->dst) {
+ sg_count = edesc->dst_nents ? : 1;
+ if (!is_sec1 || sg_count == 1)
+ dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
+ }
+
+ ret = talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[4],
+ sg_count, 0, (edesc->src_nents + 1));
+ if (ret > 1)
+ sync_needed = true;
+
+ /* iv out */
+ map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv,
+ DMA_FROM_DEVICE);
+
+ /* last DWORD empty */
+
+ if (sync_needed)
+ dma_sync_single_for_device(dev, edesc->dma_link_tbl,
+ edesc->dma_len, DMA_BIDIRECTIONAL);
+
+ ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
+ if (ret != -EINPROGRESS) {
+ common_nonsnoop_unmap(dev, edesc, areq);
+ kfree(edesc);
+ }
+ return ret;
+}
+
+static int skcipher_setkey(struct crypto_skcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ struct device *dev = ctx->dev;
+
+ if (ctx->keylen)
+ dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
+
+ memcpy(&ctx->key, key, keylen);
+ ctx->keylen = keylen;
+
+ ctx->dma_key = dma_map_single(dev, ctx->key, keylen, DMA_TO_DEVICE);
+
+ return 0;
+}
+
+static int skcipher_des_setkey(struct crypto_skcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return verify_skcipher_des_key(cipher, key) ?:
+ skcipher_setkey(cipher, key, keylen);
+}
+
+static int skcipher_des3_setkey(struct crypto_skcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return verify_skcipher_des3_key(cipher, key) ?:
+ skcipher_setkey(cipher, key, keylen);
+}
+
+static int skcipher_aes_setkey(struct crypto_skcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ if (keylen == AES_KEYSIZE_128 || keylen == AES_KEYSIZE_192 ||
+ keylen == AES_KEYSIZE_256)
+ return skcipher_setkey(cipher, key, keylen);
+
+ return -EINVAL;
+}
+
+static struct talitos_edesc *skcipher_edesc_alloc(struct skcipher_request *
+ areq, bool encrypt)
+{
+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ unsigned int ivsize = crypto_skcipher_ivsize(cipher);
+
+ return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
+ areq->iv, 0, areq->cryptlen, 0, ivsize, 0,
+ areq->base.flags, encrypt);
+}
+
+static int skcipher_encrypt(struct skcipher_request *areq)
+{
+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ struct talitos_edesc *edesc;
+ unsigned int blocksize =
+ crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher));
+
+ if (!areq->cryptlen)
+ return 0;
+
+ if (areq->cryptlen % blocksize)
+ return -EINVAL;
+
+ /* allocate extended descriptor */
+ edesc = skcipher_edesc_alloc(areq, true);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+ /* set encrypt */
+ edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
+
+ return common_nonsnoop(edesc, areq, skcipher_done);
+}
+
+static int skcipher_decrypt(struct skcipher_request *areq)
+{
+ struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
+ struct talitos_edesc *edesc;
+ unsigned int blocksize =
+ crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher));
+
+ if (!areq->cryptlen)
+ return 0;
+
+ if (areq->cryptlen % blocksize)
+ return -EINVAL;
+
+ /* allocate extended descriptor */
+ edesc = skcipher_edesc_alloc(areq, false);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+ edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
+
+ return common_nonsnoop(edesc, areq, skcipher_done);
+}
+
+static int talitos_cra_init_skcipher(struct crypto_skcipher *tfm)
+{
+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
+ struct talitos_crypto_alg *talitos_alg;
+ struct talitos_ctx *ctx = crypto_skcipher_ctx(tfm);
+
+ talitos_alg = container_of(alg, struct talitos_crypto_alg,
+ algt.alg.skcipher);
+
+ return talitos_init_common(ctx, talitos_alg);
+}
+
+static struct talitos_alg_template skcipher_driver_algs[] = {
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ecb(aes)",
+ .base.cra_driver_name = "ecb-aes-talitos",
+ .base.cra_blocksize = AES_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .setkey = skcipher_aes_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "cbc(aes)",
+ .base.cra_driver_name = "cbc-aes-talitos",
+ .base.cra_blocksize = AES_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+ .setkey = skcipher_aes_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ctr(aes)",
+ .base.cra_driver_name = "ctr-aes-talitos",
+ .base.cra_blocksize = 1,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+ .setkey = skcipher_aes_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_AESU_CTR_NONSNOOP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CTR,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ctr(aes)",
+ .base.cra_driver_name = "ctr-aes-talitos",
+ .base.cra_blocksize = 1,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+ .setkey = skcipher_aes_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CTR,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ecb(des)",
+ .base.cra_driver_name = "ecb-des-talitos",
+ .base.cra_blocksize = DES_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = DES_KEY_SIZE,
+ .max_keysize = DES_KEY_SIZE,
+ .setkey = skcipher_des_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "cbc(des)",
+ .base.cra_driver_name = "cbc-des-talitos",
+ .base.cra_blocksize = DES_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = DES_KEY_SIZE,
+ .max_keysize = DES_KEY_SIZE,
+ .ivsize = DES_BLOCK_SIZE,
+ .setkey = skcipher_des_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "ecb(des3_ede)",
+ .base.cra_driver_name = "ecb-3des-talitos",
+ .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = DES3_EDE_KEY_SIZE,
+ .max_keysize = DES3_EDE_KEY_SIZE,
+ .setkey = skcipher_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_3DES,
+ },
+ { .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .alg.skcipher = {
+ .base.cra_name = "cbc(des3_ede)",
+ .base.cra_driver_name = "cbc-3des-talitos",
+ .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .base.cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ .min_keysize = DES3_EDE_KEY_SIZE,
+ .max_keysize = DES3_EDE_KEY_SIZE,
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .setkey = skcipher_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES,
+ },
+};
+
+int talitos_register_skcipher(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ struct skcipher_alg *skcipher_alg;
+ struct crypto_alg *alg;
+ size_t i;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(skcipher_driver_algs); i++) {
+ if (!talitos_hw_supports(
+ dev, skcipher_driver_algs[i].desc_hdr_template))
+ continue;
+
+ skcipher_alg = &skcipher_driver_algs[i].alg.skcipher;
+ alg = &skcipher_alg->base;
+
+ alg->cra_exit = talitos_cra_exit;
+ skcipher_alg->init = talitos_cra_init_skcipher;
+ skcipher_alg->setkey = skcipher_alg->setkey ?: skcipher_setkey;
+ skcipher_alg->encrypt = skcipher_encrypt;
+ skcipher_alg->decrypt = skcipher_decrypt;
+
+ if (!strcmp(alg->cra_name, "ctr(aes)") && !has_ftr_sec1(priv) &&
+ DESC_TYPE(skcipher_driver_algs[i].desc_hdr_template) !=
+ DESC_TYPE(DESC_HDR_TYPE_AESU_CTR_NONSNOOP)) {
+ continue;
+ }
+
+ ret = talitos_register_common(dev, &skcipher_driver_algs[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index b8bcb970d7d5..cd37bc379f86 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -1430,215 +1430,6 @@ static int aead_decrypt(struct aead_request *req)
return ipsec_esp(edesc, req, false, ipsec_esp_decrypt_swauth_done);
}
-static int skcipher_setkey(struct crypto_skcipher *cipher,
- const u8 *key, unsigned int keylen)
-{
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- struct device *dev = ctx->dev;
-
- if (ctx->keylen)
- dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
-
- memcpy(&ctx->key, key, keylen);
- ctx->keylen = keylen;
-
- ctx->dma_key = dma_map_single(dev, ctx->key, keylen, DMA_TO_DEVICE);
-
- return 0;
-}
-
-static int skcipher_des_setkey(struct crypto_skcipher *cipher,
- const u8 *key, unsigned int keylen)
-{
- return verify_skcipher_des_key(cipher, key) ?:
- skcipher_setkey(cipher, key, keylen);
-}
-
-static int skcipher_des3_setkey(struct crypto_skcipher *cipher,
- const u8 *key, unsigned int keylen)
-{
- return verify_skcipher_des3_key(cipher, key) ?:
- skcipher_setkey(cipher, key, keylen);
-}
-
-static int skcipher_aes_setkey(struct crypto_skcipher *cipher,
- const u8 *key, unsigned int keylen)
-{
- if (keylen == AES_KEYSIZE_128 || keylen == AES_KEYSIZE_192 ||
- keylen == AES_KEYSIZE_256)
- return skcipher_setkey(cipher, key, keylen);
-
- return -EINVAL;
-}
-
-static void common_nonsnoop_unmap(struct device *dev,
- struct talitos_edesc *edesc,
- struct skcipher_request *areq)
-{
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
-
- talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen, 0);
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
-
- if (edesc->dma_len)
- dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
- DMA_BIDIRECTIONAL);
-}
-
-static void skcipher_done(struct device *dev,
- struct talitos_desc *desc, void *context,
- int err)
-{
- struct skcipher_request *areq = context;
- struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- unsigned int ivsize = crypto_skcipher_ivsize(cipher);
- struct talitos_edesc *edesc;
-
- edesc = container_of(desc, struct talitos_edesc, desc);
-
- common_nonsnoop_unmap(dev, edesc, areq);
- memcpy(areq->iv, ctx->iv, ivsize);
-
- kfree(edesc);
-
- skcipher_request_complete(areq, err);
-}
-
-static int common_nonsnoop(struct talitos_edesc *edesc,
- struct skcipher_request *areq,
- void (*callback) (struct device *dev,
- struct talitos_desc *desc,
- void *context, int error))
-{
- struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- struct device *dev = ctx->dev;
- struct talitos_desc *desc = &edesc->desc;
- unsigned int cryptlen = areq->cryptlen;
- unsigned int ivsize = crypto_skcipher_ivsize(cipher);
- int sg_count, ret;
- bool sync_needed = false;
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
- bool is_ctr = (desc->hdr & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_AESU &&
- (desc->hdr & DESC_HDR_MODE0_AESU_MASK) == DESC_HDR_MODE0_AESU_CTR;
-
- /* first DWORD empty */
-
- /* cipher iv */
- to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize, is_sec1);
-
- /* cipher key */
- to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, is_sec1);
-
- sg_count = edesc->src_nents ?: 1;
- if (is_sec1 && sg_count > 1)
- sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
- cryptlen);
- else
- sg_count = dma_map_sg(dev, areq->src, sg_count,
- (areq->src == areq->dst) ?
- DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
- /*
- * cipher in
- */
- sg_count = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[3],
- sg_count, 0, 0, 0, false, is_ctr ? 16 : 1);
- if (sg_count > 1)
- sync_needed = true;
-
- /* cipher out */
- if (areq->src != areq->dst) {
- sg_count = edesc->dst_nents ? : 1;
- if (!is_sec1 || sg_count == 1)
- dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
- }
-
- ret = talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[4],
- sg_count, 0, (edesc->src_nents + 1));
- if (ret > 1)
- sync_needed = true;
-
- /* iv out */
- map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv,
- DMA_FROM_DEVICE);
-
- /* last DWORD empty */
-
- if (sync_needed)
- dma_sync_single_for_device(dev, edesc->dma_link_tbl,
- edesc->dma_len, DMA_BIDIRECTIONAL);
-
- ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
- if (ret != -EINPROGRESS) {
- common_nonsnoop_unmap(dev, edesc, areq);
- kfree(edesc);
- }
- return ret;
-}
-
-static struct talitos_edesc *skcipher_edesc_alloc(struct skcipher_request *
- areq, bool encrypt)
-{
- struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- unsigned int ivsize = crypto_skcipher_ivsize(cipher);
-
- return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
- areq->iv, 0, areq->cryptlen, 0, ivsize, 0,
- areq->base.flags, encrypt);
-}
-
-static int skcipher_encrypt(struct skcipher_request *areq)
-{
- struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- struct talitos_edesc *edesc;
- unsigned int blocksize =
- crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher));
-
- if (!areq->cryptlen)
- return 0;
-
- if (areq->cryptlen % blocksize)
- return -EINVAL;
-
- /* allocate extended descriptor */
- edesc = skcipher_edesc_alloc(areq, true);
- if (IS_ERR(edesc))
- return PTR_ERR(edesc);
-
- /* set encrypt */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
-
- return common_nonsnoop(edesc, areq, skcipher_done);
-}
-
-static int skcipher_decrypt(struct skcipher_request *areq)
-{
- struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
- struct talitos_edesc *edesc;
- unsigned int blocksize =
- crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher));
-
- if (!areq->cryptlen)
- return 0;
-
- if (areq->cryptlen % blocksize)
- return -EINVAL;
-
- /* allocate extended descriptor */
- edesc = skcipher_edesc_alloc(areq, false);
- if (IS_ERR(edesc))
- return PTR_ERR(edesc);
-
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
-
- return common_nonsnoop(edesc, areq, skcipher_done);
-}
-
static struct talitos_alg_template driver_algs[] = {
/* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
{ .type = CRYPTO_ALG_TYPE_AEAD,
@@ -2097,131 +1888,6 @@ static struct talitos_alg_template driver_algs[] = {
DESC_HDR_MODE1_MDEU_PAD |
DESC_HDR_MODE1_MDEU_MD5_HMAC,
},
- /* SKCIPHER algorithms. */
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(aes)",
- .base.cra_driver_name = "ecb-aes-talitos",
- .base.cra_blocksize = AES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(aes)",
- .base.cra_driver_name = "cbc-aes-talitos",
- .base.cra_blocksize = AES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ctr(aes)",
- .base.cra_driver_name = "ctr-aes-talitos",
- .base.cra_blocksize = 1,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_AESU_CTR_NONSNOOP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CTR,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ctr(aes)",
- .base.cra_driver_name = "ctr-aes-talitos",
- .base.cra_blocksize = 1,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CTR,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(des)",
- .base.cra_driver_name = "ecb-des-talitos",
- .base.cra_blocksize = DES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES_KEY_SIZE,
- .max_keysize = DES_KEY_SIZE,
- .setkey = skcipher_des_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(des)",
- .base.cra_driver_name = "cbc-des-talitos",
- .base.cra_blocksize = DES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES_KEY_SIZE,
- .max_keysize = DES_KEY_SIZE,
- .ivsize = DES_BLOCK_SIZE,
- .setkey = skcipher_des_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(des3_ede)",
- .base.cra_driver_name = "ecb-3des-talitos",
- .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES3_EDE_KEY_SIZE,
- .max_keysize = DES3_EDE_KEY_SIZE,
- .setkey = skcipher_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_3DES,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(des3_ede)",
- .base.cra_driver_name = "cbc-3des-talitos",
- .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- .min_keysize = DES3_EDE_KEY_SIZE,
- .max_keysize = DES3_EDE_KEY_SIZE,
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .setkey = skcipher_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES,
- },
};
int talitos_init_common(struct talitos_ctx *ctx,
@@ -2258,18 +1924,6 @@ static int talitos_cra_init_aead(struct crypto_aead *tfm)
return talitos_init_common(ctx, talitos_alg);
}
-static int talitos_cra_init_skcipher(struct crypto_skcipher *tfm)
-{
- struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
- struct talitos_crypto_alg *talitos_alg;
- struct talitos_ctx *ctx = crypto_skcipher_ctx(tfm);
-
- talitos_alg = container_of(alg, struct talitos_crypto_alg,
- algt.alg.skcipher);
-
- return talitos_init_common(ctx, talitos_alg);
-}
-
void talitos_cra_exit(struct crypto_tfm *tfm)
{
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
@@ -2374,6 +2028,12 @@ int talitos_register_common(struct device *dev,
t_alg->algt.type);
ret = crypto_register_ahash(&t_alg->algt.alg.hash);
break;
+ case CRYPTO_ALG_TYPE_SKCIPHER:
+ alg = &t_alg->algt.alg.skcipher.base;
+ talitos_alg_set_common(priv, alg, t_alg->algt.priority,
+ t_alg->algt.type);
+ ret = crypto_register_skcipher(&t_alg->algt.alg.skcipher);
+ break;
default:
dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
devm_kfree(dev, t_alg);
@@ -2410,21 +2070,6 @@ static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
t_alg->algt = *template;
switch (t_alg->algt.type) {
- case CRYPTO_ALG_TYPE_SKCIPHER:
- alg = &t_alg->algt.alg.skcipher.base;
- alg->cra_exit = talitos_cra_exit;
- t_alg->algt.alg.skcipher.init = talitos_cra_init_skcipher;
- t_alg->algt.alg.skcipher.setkey =
- t_alg->algt.alg.skcipher.setkey ?: skcipher_setkey;
- t_alg->algt.alg.skcipher.encrypt = skcipher_encrypt;
- t_alg->algt.alg.skcipher.decrypt = skcipher_decrypt;
- if (!strcmp(alg->cra_name, "ctr(aes)") && !has_ftr_sec1(priv) &&
- DESC_TYPE(t_alg->algt.desc_hdr_template) !=
- DESC_TYPE(DESC_HDR_TYPE_AESU_CTR_NONSNOOP)) {
- devm_kfree(dev, t_alg);
- return ERR_PTR(-ENOTSUPP);
- }
- break;
case CRYPTO_ALG_TYPE_AEAD:
alg = &t_alg->algt.alg.aead.base;
alg->cra_exit = talitos_cra_exit;
@@ -2671,6 +2316,10 @@ static int talitos_probe(struct platform_device *ofdev)
if (err)
goto err_out;
+ err = talitos_register_skcipher(dev);
+ if (err)
+ goto err_out;
+
/* register crypto algorithms the device supports */
for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
if (talitos_hw_supports(dev,
@@ -2687,12 +2336,6 @@ static int talitos_probe(struct platform_device *ofdev)
}
switch (t_alg->algt.type) {
- case CRYPTO_ALG_TYPE_SKCIPHER:
- err = crypto_register_skcipher(
- &t_alg->algt.alg.skcipher);
- alg = &t_alg->algt.alg.skcipher.base;
- break;
-
case CRYPTO_ALG_TYPE_AEAD:
err = crypto_register_aead(
&t_alg->algt.alg.aead);
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index e703c18cb81f..7e7d41673fa5 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -534,3 +534,4 @@ void talitos_unregister_rng(struct device *dev);
/* Hash */
int talitos_register_hash(struct device *dev);
+int talitos_register_skcipher(struct device *dev);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 09/29] crypto: talitos/aead - Move into separate file
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (7 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 08/29] crypto: talitos/skcipher " Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 10/29] crypto: talitos - Remove alg settings in talitos_register_common() Paul Louvel
` (19 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Move the AEAD algorithm implementations from talitos.c into
a dedicated talitos-aead.c file.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/Makefile | 2 +-
drivers/crypto/talitos/talitos-aead.c | 894 ++++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.c | 947 +---------------------------------
drivers/crypto/talitos/talitos.h | 3 +
4 files changed, 907 insertions(+), 939 deletions(-)
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
index d4f19f2f6375..9e80bb094507 100644
--- a/drivers/crypto/talitos/Makefile
+++ b/drivers/crypto/talitos/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
-talitos-y := talitos.o talitos-rng.o talitos-hash.o talitos-skcipher.o
+talitos-y := talitos.o talitos-rng.o talitos-hash.o talitos-skcipher.o talitos-aead.o
diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos/talitos-aead.c
new file mode 100644
index 000000000000..ce6bd6133fd0
--- /dev/null
+++ b/drivers/crypto/talitos/talitos-aead.c
@@ -0,0 +1,894 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <crypto/authenc.h>
+#include <crypto/internal/des.h>
+#include <crypto/internal/aead.h>
+#include <crypto/md5.h>
+#include <crypto/sha1.h>
+#include <crypto/sha2.h>
+
+#include "talitos.h"
+
+/*
+ * Defines a priority for doing AEAD with descriptors type
+ * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP
+ */
+#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
+
+static int aead_setkey(struct crypto_aead *authenc,
+ const u8 *key, unsigned int keylen)
+{
+ struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
+ struct device *dev = ctx->dev;
+ struct crypto_authenc_keys keys;
+
+ if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
+ goto badkey;
+
+ if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
+ goto badkey;
+
+ if (ctx->keylen)
+ dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
+
+ memcpy(ctx->key, keys.authkey, keys.authkeylen);
+ memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
+
+ ctx->keylen = keys.authkeylen + keys.enckeylen;
+ ctx->enckeylen = keys.enckeylen;
+ ctx->authkeylen = keys.authkeylen;
+ ctx->dma_key = dma_map_single(dev, ctx->key, ctx->keylen,
+ DMA_TO_DEVICE);
+
+ memzero_explicit(&keys, sizeof(keys));
+ return 0;
+
+badkey:
+ memzero_explicit(&keys, sizeof(keys));
+ return -EINVAL;
+}
+
+static int aead_des3_setkey(struct crypto_aead *authenc,
+ const u8 *key, unsigned int keylen)
+{
+ struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
+ struct device *dev = ctx->dev;
+ struct crypto_authenc_keys keys;
+ int err;
+
+ err = crypto_authenc_extractkeys(&keys, key, keylen);
+ if (unlikely(err))
+ goto out;
+
+ err = -EINVAL;
+ if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
+ goto out;
+
+ err = verify_aead_des3_key(authenc, keys.enckey, keys.enckeylen);
+ if (err)
+ goto out;
+
+ if (ctx->keylen)
+ dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
+
+ memcpy(ctx->key, keys.authkey, keys.authkeylen);
+ memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
+
+ ctx->keylen = keys.authkeylen + keys.enckeylen;
+ ctx->enckeylen = keys.enckeylen;
+ ctx->authkeylen = keys.authkeylen;
+ ctx->dma_key = dma_map_single(dev, ctx->key, ctx->keylen,
+ DMA_TO_DEVICE);
+
+out:
+ memzero_explicit(&keys, sizeof(keys));
+ return err;
+}
+
+static void ipsec_esp_unmap(struct device *dev,
+ struct talitos_edesc *edesc,
+ struct aead_request *areq, bool encrypt)
+{
+ struct crypto_aead *aead = crypto_aead_reqtfm(areq);
+ struct talitos_ctx *ctx = crypto_aead_ctx(aead);
+ unsigned int ivsize = crypto_aead_ivsize(aead);
+ unsigned int authsize = crypto_aead_authsize(aead);
+ unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
+ bool is_ipsec_esp = edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP;
+ struct talitos_ptr *civ_ptr = &edesc->desc.ptr[is_ipsec_esp ? 2 : 3];
+
+ if (is_ipsec_esp)
+ unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6],
+ DMA_FROM_DEVICE);
+ unmap_single_talitos_ptr(dev, civ_ptr, DMA_TO_DEVICE);
+
+ talitos_sg_unmap(dev, edesc, areq->src, areq->dst,
+ cryptlen + authsize, areq->assoclen);
+
+ if (edesc->dma_len)
+ dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
+ DMA_BIDIRECTIONAL);
+
+ if (!is_ipsec_esp) {
+ unsigned int dst_nents = edesc->dst_nents ? : 1;
+
+ sg_pcopy_to_buffer(areq->dst, dst_nents, ctx->iv, ivsize,
+ areq->assoclen + cryptlen - ivsize);
+ }
+}
+
+/*
+ * ipsec_esp descriptor callbacks
+ */
+static void ipsec_esp_encrypt_done(struct device *dev,
+ struct talitos_desc *desc, void *context,
+ int err)
+{
+ struct aead_request *areq = context;
+ struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
+ unsigned int ivsize = crypto_aead_ivsize(authenc);
+ struct talitos_edesc *edesc;
+
+ edesc = container_of(desc, struct talitos_edesc, desc);
+
+ ipsec_esp_unmap(dev, edesc, areq, true);
+
+ dma_unmap_single(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
+
+ kfree(edesc);
+
+ aead_request_complete(areq, err);
+}
+
+static void ipsec_esp_decrypt_swauth_done(struct device *dev,
+ struct talitos_desc *desc,
+ void *context, int err)
+{
+ struct aead_request *req = context;
+ struct crypto_aead *authenc = crypto_aead_reqtfm(req);
+ unsigned int authsize = crypto_aead_authsize(authenc);
+ struct talitos_edesc *edesc;
+ char *oicv, *icv;
+
+ edesc = container_of(desc, struct talitos_edesc, desc);
+
+ ipsec_esp_unmap(dev, edesc, req, false);
+
+ if (!err) {
+ /* auth check */
+ oicv = edesc->buf + edesc->dma_len;
+ icv = oicv - authsize;
+
+ err = crypto_memneq(oicv, icv, authsize) ? -EBADMSG : 0;
+ }
+
+ kfree(edesc);
+
+ aead_request_complete(req, err);
+}
+
+static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
+ struct talitos_desc *desc,
+ void *context, int err)
+{
+ struct aead_request *req = context;
+ struct talitos_edesc *edesc;
+
+ edesc = container_of(desc, struct talitos_edesc, desc);
+
+ ipsec_esp_unmap(dev, edesc, req, false);
+
+ /* check ICV auth status */
+ if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
+ DESC_HDR_LO_ICCR1_PASS))
+ err = -EBADMSG;
+
+ kfree(edesc);
+
+ aead_request_complete(req, err);
+}
+
+/*
+ * fill in and submit ipsec_esp descriptor
+ */
+static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
+ bool encrypt,
+ void (*callback)(struct device *dev,
+ struct talitos_desc *desc,
+ void *context, int error))
+{
+ struct crypto_aead *aead = crypto_aead_reqtfm(areq);
+ unsigned int authsize = crypto_aead_authsize(aead);
+ struct talitos_ctx *ctx = crypto_aead_ctx(aead);
+ struct device *dev = ctx->dev;
+ struct talitos_desc *desc = &edesc->desc;
+ unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
+ unsigned int ivsize = crypto_aead_ivsize(aead);
+ int tbl_off = 0;
+ int sg_count, ret;
+ int elen = 0;
+ bool sync_needed = false;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+ bool is_ipsec_esp = desc->hdr & DESC_HDR_TYPE_IPSEC_ESP;
+ struct talitos_ptr *civ_ptr = &desc->ptr[is_ipsec_esp ? 2 : 3];
+ struct talitos_ptr *ckey_ptr = &desc->ptr[is_ipsec_esp ? 3 : 2];
+ dma_addr_t dma_icv = edesc->dma_link_tbl + edesc->dma_len - authsize;
+
+ /* hmac key */
+ to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen, is_sec1);
+
+ sg_count = edesc->src_nents ?: 1;
+ if (is_sec1 && sg_count > 1)
+ sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
+ areq->assoclen + cryptlen);
+ else
+ sg_count = dma_map_sg(dev, areq->src, sg_count,
+ (areq->src == areq->dst) ?
+ DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
+
+ /* hmac data */
+ ret = talitos_sg_map(dev, areq->src, areq->assoclen, edesc,
+ &desc->ptr[1], sg_count, 0, tbl_off);
+
+ if (ret > 1) {
+ tbl_off += ret;
+ sync_needed = true;
+ }
+
+ /* cipher iv */
+ to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize, is_sec1);
+
+ /* cipher key */
+ to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen,
+ ctx->enckeylen, is_sec1);
+
+ /*
+ * cipher in
+ * map and adjust cipher len to aead request cryptlen.
+ * extent is bytes of HMAC postpended to ciphertext,
+ * typically 12 for ipsec
+ */
+ if (is_ipsec_esp && (desc->hdr & DESC_HDR_MODE1_MDEU_CICV))
+ elen = authsize;
+
+ ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4],
+ sg_count, areq->assoclen, tbl_off, elen,
+ false, 1);
+
+ if (ret > 1) {
+ tbl_off += ret;
+ sync_needed = true;
+ }
+
+ /* cipher out */
+ if (areq->src != areq->dst) {
+ sg_count = edesc->dst_nents ? : 1;
+ if (!is_sec1 || sg_count == 1)
+ dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
+ }
+
+ if (is_ipsec_esp && encrypt)
+ elen = authsize;
+ else
+ elen = 0;
+ ret = talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, &desc->ptr[5],
+ sg_count, areq->assoclen, tbl_off, elen,
+ is_ipsec_esp && !encrypt, 1);
+ tbl_off += ret;
+
+ if (!encrypt && is_ipsec_esp) {
+ struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
+
+ /* Add an entry to the link table for ICV data */
+ to_talitos_ptr_ext_set(tbl_ptr - 1, 0, is_sec1);
+ to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET, is_sec1);
+
+ /* icv data follows link tables */
+ to_talitos_ptr(tbl_ptr, dma_icv, authsize, is_sec1);
+ to_talitos_ptr_ext_or(&desc->ptr[5], authsize, is_sec1);
+ sync_needed = true;
+ } else if (!encrypt) {
+ to_talitos_ptr(&desc->ptr[6], dma_icv, authsize, is_sec1);
+ sync_needed = true;
+ } else if (!is_ipsec_esp) {
+ talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6],
+ sg_count, areq->assoclen + cryptlen, tbl_off);
+ }
+
+ /* iv out */
+ if (is_ipsec_esp)
+ map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
+ DMA_FROM_DEVICE);
+
+ if (sync_needed)
+ dma_sync_single_for_device(dev, edesc->dma_link_tbl,
+ edesc->dma_len,
+ DMA_BIDIRECTIONAL);
+
+ ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
+ if (ret != -EINPROGRESS) {
+ ipsec_esp_unmap(dev, edesc, areq, encrypt);
+ kfree(edesc);
+ }
+ return ret;
+}
+
+static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
+ int icv_stashing, bool encrypt)
+{
+ struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
+ unsigned int authsize = crypto_aead_authsize(authenc);
+ struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
+ unsigned int ivsize = crypto_aead_ivsize(authenc);
+ unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
+
+ return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
+ iv, areq->assoclen, cryptlen,
+ authsize, ivsize, icv_stashing,
+ areq->base.flags, encrypt);
+}
+
+static int aead_encrypt(struct aead_request *req)
+{
+ struct crypto_aead *authenc = crypto_aead_reqtfm(req);
+ struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
+ struct talitos_edesc *edesc;
+
+ /* allocate extended descriptor */
+ edesc = aead_edesc_alloc(req, req->iv, 0, true);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+ /* set encrypt */
+ edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
+
+ return ipsec_esp(edesc, req, true, ipsec_esp_encrypt_done);
+}
+
+static int aead_decrypt(struct aead_request *req)
+{
+ struct crypto_aead *authenc = crypto_aead_reqtfm(req);
+ unsigned int authsize = crypto_aead_authsize(authenc);
+ struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
+ struct talitos_private *priv = dev_get_drvdata(ctx->dev);
+ struct talitos_edesc *edesc;
+ void *icvdata;
+
+ /* allocate extended descriptor */
+ edesc = aead_edesc_alloc(req, req->iv, 1, false);
+ if (IS_ERR(edesc))
+ return PTR_ERR(edesc);
+
+ if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) &&
+ (priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
+ ((!edesc->src_nents && !edesc->dst_nents) ||
+ priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
+
+ /* decrypt and check the ICV */
+ edesc->desc.hdr = ctx->desc_hdr_template |
+ DESC_HDR_DIR_INBOUND |
+ DESC_HDR_MODE1_MDEU_CICV;
+
+ /* reset integrity check result bits */
+
+ return ipsec_esp(edesc, req, false,
+ ipsec_esp_decrypt_hwauth_done);
+ }
+
+ /* Have to check the ICV with software */
+ edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
+
+ /* stash incoming ICV for later cmp with ICV generated by the h/w */
+ icvdata = edesc->buf + edesc->dma_len;
+
+ sg_pcopy_to_buffer(req->src, edesc->src_nents ? : 1, icvdata, authsize,
+ req->assoclen + req->cryptlen - authsize);
+
+ return ipsec_esp(edesc, req, false, ipsec_esp_decrypt_swauth_done);
+}
+
+static int talitos_cra_init_aead(struct crypto_aead *tfm)
+{
+ struct aead_alg *alg = crypto_aead_alg(tfm);
+ struct talitos_crypto_alg *talitos_alg;
+ struct talitos_ctx *ctx = crypto_aead_ctx(tfm);
+
+ talitos_alg = container_of(alg, struct talitos_crypto_alg,
+ algt.alg.aead);
+
+ return talitos_init_common(ctx, talitos_alg);
+}
+
+static struct talitos_alg_template aead_driver_algs[] = {
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha1),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha1-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA1_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha1),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha1-"
+ "cbc-aes-talitos-hsna",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA1_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha1),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha1-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA1_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha1),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha1-"
+ "cbc-3des-talitos-hsna",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA1_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha224),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha224-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA224_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha224),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha224-"
+ "cbc-aes-talitos-hsna",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA224_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha224),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha224-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA224_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha224),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha224-"
+ "cbc-3des-talitos-hsna",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA224_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha256),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha256-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA256_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha256),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha256-"
+ "cbc-aes-talitos-hsna",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA256_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha256),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha256-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA256_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha256),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha256-"
+ "cbc-3des-talitos-hsna",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA256_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha384),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha384-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA384_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha384),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha384-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA384_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha512),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-sha512-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = SHA512_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(sha512),"
+ "cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-sha512-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = SHA512_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(md5),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-md5-"
+ "cbc-aes-talitos",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = MD5_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(md5),cbc(aes))",
+ .cra_driver_name = "authenc-hmac-md5-"
+ "cbc-aes-talitos-hsna",
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = AES_BLOCK_SIZE,
+ .maxauthsize = MD5_DIGEST_SIZE,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-md5-"
+ "cbc-3des-talitos",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = MD5_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC,
+ },
+ { .type = CRYPTO_ALG_TYPE_AEAD,
+ .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .alg.aead = {
+ .base = {
+ .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
+ .cra_driver_name = "authenc-hmac-md5-"
+ "cbc-3des-talitos-hsna",
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_ALLOCATES_MEMORY,
+ },
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .maxauthsize = MD5_DIGEST_SIZE,
+ .setkey = aead_des3_setkey,
+ },
+ .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC,
+ },
+};
+
+int talitos_register_aead(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ struct aead_alg *aead_alg;
+ struct crypto_alg *alg;
+ size_t i;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(aead_driver_algs); i++) {
+ if (!talitos_hw_supports(dev,
+ aead_driver_algs[i].desc_hdr_template))
+ continue;
+
+ aead_alg = &aead_driver_algs[i].alg.aead;
+ alg = &aead_alg->base;
+
+ alg->cra_exit = talitos_cra_exit;
+ aead_alg->init = talitos_cra_init_aead;
+ aead_alg->setkey = aead_alg->setkey ?: aead_setkey;
+ aead_alg->encrypt = aead_encrypt;
+ aead_alg->decrypt = aead_decrypt;
+ if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
+ !strncmp(alg->cra_name, "authenc(hmac(sha224)", 20)) {
+ continue;
+ }
+
+ ret = talitos_register_common(dev, &aead_driver_algs[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index cd37bc379f86..41d7d0e570e3 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -820,87 +820,6 @@ DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE, TALITOS2_ISR_CH_0_2_ERR,
DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
1)
-
-/*
- * crypto alg
- */
-#define TALITOS_CRA_PRIORITY 3000
-/*
- * Defines a priority for doing AEAD with descriptors type
- * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP
- */
-#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
-
-static int aead_setkey(struct crypto_aead *authenc,
- const u8 *key, unsigned int keylen)
-{
- struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
- struct device *dev = ctx->dev;
- struct crypto_authenc_keys keys;
-
- if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
- goto badkey;
-
- if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
- goto badkey;
-
- if (ctx->keylen)
- dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
-
- memcpy(ctx->key, keys.authkey, keys.authkeylen);
- memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
-
- ctx->keylen = keys.authkeylen + keys.enckeylen;
- ctx->enckeylen = keys.enckeylen;
- ctx->authkeylen = keys.authkeylen;
- ctx->dma_key = dma_map_single(dev, ctx->key, ctx->keylen,
- DMA_TO_DEVICE);
-
- memzero_explicit(&keys, sizeof(keys));
- return 0;
-
-badkey:
- memzero_explicit(&keys, sizeof(keys));
- return -EINVAL;
-}
-
-static int aead_des3_setkey(struct crypto_aead *authenc,
- const u8 *key, unsigned int keylen)
-{
- struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
- struct device *dev = ctx->dev;
- struct crypto_authenc_keys keys;
- int err;
-
- err = crypto_authenc_extractkeys(&keys, key, keylen);
- if (unlikely(err))
- goto out;
-
- err = -EINVAL;
- if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
- goto out;
-
- err = verify_aead_des3_key(authenc, keys.enckey, keys.enckeylen);
- if (err)
- goto out;
-
- if (ctx->keylen)
- dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
-
- memcpy(ctx->key, keys.authkey, keys.authkeylen);
- memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
-
- ctx->keylen = keys.authkeylen + keys.enckeylen;
- ctx->enckeylen = keys.enckeylen;
- ctx->authkeylen = keys.authkeylen;
- ctx->dma_key = dma_map_single(dev, ctx->key, ctx->keylen,
- DMA_TO_DEVICE);
-
-out:
- memzero_explicit(&keys, sizeof(keys));
- return err;
-}
-
void talitos_sg_unmap(struct device *dev,
struct talitos_edesc *edesc,
struct scatterlist *src,
@@ -929,109 +848,6 @@ void talitos_sg_unmap(struct device *dev,
}
}
-static void ipsec_esp_unmap(struct device *dev,
- struct talitos_edesc *edesc,
- struct aead_request *areq, bool encrypt)
-{
- struct crypto_aead *aead = crypto_aead_reqtfm(areq);
- struct talitos_ctx *ctx = crypto_aead_ctx(aead);
- unsigned int ivsize = crypto_aead_ivsize(aead);
- unsigned int authsize = crypto_aead_authsize(aead);
- unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
- bool is_ipsec_esp = edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP;
- struct talitos_ptr *civ_ptr = &edesc->desc.ptr[is_ipsec_esp ? 2 : 3];
-
- if (is_ipsec_esp)
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6],
- DMA_FROM_DEVICE);
- unmap_single_talitos_ptr(dev, civ_ptr, DMA_TO_DEVICE);
-
- talitos_sg_unmap(dev, edesc, areq->src, areq->dst,
- cryptlen + authsize, areq->assoclen);
-
- if (edesc->dma_len)
- dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
- DMA_BIDIRECTIONAL);
-
- if (!is_ipsec_esp) {
- unsigned int dst_nents = edesc->dst_nents ? : 1;
-
- sg_pcopy_to_buffer(areq->dst, dst_nents, ctx->iv, ivsize,
- areq->assoclen + cryptlen - ivsize);
- }
-}
-
-/*
- * ipsec_esp descriptor callbacks
- */
-static void ipsec_esp_encrypt_done(struct device *dev,
- struct talitos_desc *desc, void *context,
- int err)
-{
- struct aead_request *areq = context;
- struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
- unsigned int ivsize = crypto_aead_ivsize(authenc);
- struct talitos_edesc *edesc;
-
- edesc = container_of(desc, struct talitos_edesc, desc);
-
- ipsec_esp_unmap(dev, edesc, areq, true);
-
- dma_unmap_single(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
-
- kfree(edesc);
-
- aead_request_complete(areq, err);
-}
-
-static void ipsec_esp_decrypt_swauth_done(struct device *dev,
- struct talitos_desc *desc,
- void *context, int err)
-{
- struct aead_request *req = context;
- struct crypto_aead *authenc = crypto_aead_reqtfm(req);
- unsigned int authsize = crypto_aead_authsize(authenc);
- struct talitos_edesc *edesc;
- char *oicv, *icv;
-
- edesc = container_of(desc, struct talitos_edesc, desc);
-
- ipsec_esp_unmap(dev, edesc, req, false);
-
- if (!err) {
- /* auth check */
- oicv = edesc->buf + edesc->dma_len;
- icv = oicv - authsize;
-
- err = crypto_memneq(oicv, icv, authsize) ? -EBADMSG : 0;
- }
-
- kfree(edesc);
-
- aead_request_complete(req, err);
-}
-
-static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
- struct talitos_desc *desc,
- void *context, int err)
-{
- struct aead_request *req = context;
- struct talitos_edesc *edesc;
-
- edesc = container_of(desc, struct talitos_edesc, desc);
-
- ipsec_esp_unmap(dev, edesc, req, false);
-
- /* check ICV auth status */
- if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
- DESC_HDR_LO_ICCR1_PASS))
- err = -EBADMSG;
-
- kfree(edesc);
-
- aead_request_complete(req, err);
-}
-
/*
* convert scatterlist to SEC h/w link table format
* stop at cryptlen bytes
@@ -1132,132 +948,6 @@ int talitos_sg_map(struct device *dev, struct scatterlist *src,
tbl_off, 0, false, 1);
}
-/*
- * fill in and submit ipsec_esp descriptor
- */
-static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
- bool encrypt,
- void (*callback)(struct device *dev,
- struct talitos_desc *desc,
- void *context, int error))
-{
- struct crypto_aead *aead = crypto_aead_reqtfm(areq);
- unsigned int authsize = crypto_aead_authsize(aead);
- struct talitos_ctx *ctx = crypto_aead_ctx(aead);
- struct device *dev = ctx->dev;
- struct talitos_desc *desc = &edesc->desc;
- unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
- unsigned int ivsize = crypto_aead_ivsize(aead);
- int tbl_off = 0;
- int sg_count, ret;
- int elen = 0;
- bool sync_needed = false;
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
- bool is_ipsec_esp = desc->hdr & DESC_HDR_TYPE_IPSEC_ESP;
- struct talitos_ptr *civ_ptr = &desc->ptr[is_ipsec_esp ? 2 : 3];
- struct talitos_ptr *ckey_ptr = &desc->ptr[is_ipsec_esp ? 3 : 2];
- dma_addr_t dma_icv = edesc->dma_link_tbl + edesc->dma_len - authsize;
-
- /* hmac key */
- to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen, is_sec1);
-
- sg_count = edesc->src_nents ?: 1;
- if (is_sec1 && sg_count > 1)
- sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
- areq->assoclen + cryptlen);
- else
- sg_count = dma_map_sg(dev, areq->src, sg_count,
- (areq->src == areq->dst) ?
- DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
-
- /* hmac data */
- ret = talitos_sg_map(dev, areq->src, areq->assoclen, edesc,
- &desc->ptr[1], sg_count, 0, tbl_off);
-
- if (ret > 1) {
- tbl_off += ret;
- sync_needed = true;
- }
-
- /* cipher iv */
- to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize, is_sec1);
-
- /* cipher key */
- to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen,
- ctx->enckeylen, is_sec1);
-
- /*
- * cipher in
- * map and adjust cipher len to aead request cryptlen.
- * extent is bytes of HMAC postpended to ciphertext,
- * typically 12 for ipsec
- */
- if (is_ipsec_esp && (desc->hdr & DESC_HDR_MODE1_MDEU_CICV))
- elen = authsize;
-
- ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4],
- sg_count, areq->assoclen, tbl_off, elen,
- false, 1);
-
- if (ret > 1) {
- tbl_off += ret;
- sync_needed = true;
- }
-
- /* cipher out */
- if (areq->src != areq->dst) {
- sg_count = edesc->dst_nents ? : 1;
- if (!is_sec1 || sg_count == 1)
- dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
- }
-
- if (is_ipsec_esp && encrypt)
- elen = authsize;
- else
- elen = 0;
- ret = talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, &desc->ptr[5],
- sg_count, areq->assoclen, tbl_off, elen,
- is_ipsec_esp && !encrypt, 1);
- tbl_off += ret;
-
- if (!encrypt && is_ipsec_esp) {
- struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
-
- /* Add an entry to the link table for ICV data */
- to_talitos_ptr_ext_set(tbl_ptr - 1, 0, is_sec1);
- to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET, is_sec1);
-
- /* icv data follows link tables */
- to_talitos_ptr(tbl_ptr, dma_icv, authsize, is_sec1);
- to_talitos_ptr_ext_or(&desc->ptr[5], authsize, is_sec1);
- sync_needed = true;
- } else if (!encrypt) {
- to_talitos_ptr(&desc->ptr[6], dma_icv, authsize, is_sec1);
- sync_needed = true;
- } else if (!is_ipsec_esp) {
- talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6],
- sg_count, areq->assoclen + cryptlen, tbl_off);
- }
-
- /* iv out */
- if (is_ipsec_esp)
- map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
- DMA_FROM_DEVICE);
-
- if (sync_needed)
- dma_sync_single_for_device(dev, edesc->dma_link_tbl,
- edesc->dma_len,
- DMA_BIDIRECTIONAL);
-
- ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
- if (ret != -EINPROGRESS) {
- ipsec_esp_unmap(dev, edesc, areq, encrypt);
- kfree(edesc);
- }
- return ret;
-}
-
/*
* allocate and map the extended descriptor
*/
@@ -1356,540 +1046,6 @@ struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
return edesc;
}
-static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
- int icv_stashing, bool encrypt)
-{
- struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
- unsigned int authsize = crypto_aead_authsize(authenc);
- struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
- unsigned int ivsize = crypto_aead_ivsize(authenc);
- unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
-
- return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
- iv, areq->assoclen, cryptlen,
- authsize, ivsize, icv_stashing,
- areq->base.flags, encrypt);
-}
-
-static int aead_encrypt(struct aead_request *req)
-{
- struct crypto_aead *authenc = crypto_aead_reqtfm(req);
- struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
- struct talitos_edesc *edesc;
-
- /* allocate extended descriptor */
- edesc = aead_edesc_alloc(req, req->iv, 0, true);
- if (IS_ERR(edesc))
- return PTR_ERR(edesc);
-
- /* set encrypt */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
-
- return ipsec_esp(edesc, req, true, ipsec_esp_encrypt_done);
-}
-
-static int aead_decrypt(struct aead_request *req)
-{
- struct crypto_aead *authenc = crypto_aead_reqtfm(req);
- unsigned int authsize = crypto_aead_authsize(authenc);
- struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
- struct talitos_private *priv = dev_get_drvdata(ctx->dev);
- struct talitos_edesc *edesc;
- void *icvdata;
-
- /* allocate extended descriptor */
- edesc = aead_edesc_alloc(req, req->iv, 1, false);
- if (IS_ERR(edesc))
- return PTR_ERR(edesc);
-
- if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) &&
- (priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
- ((!edesc->src_nents && !edesc->dst_nents) ||
- priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
-
- /* decrypt and check the ICV */
- edesc->desc.hdr = ctx->desc_hdr_template |
- DESC_HDR_DIR_INBOUND |
- DESC_HDR_MODE1_MDEU_CICV;
-
- /* reset integrity check result bits */
-
- return ipsec_esp(edesc, req, false,
- ipsec_esp_decrypt_hwauth_done);
- }
-
- /* Have to check the ICV with software */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
-
- /* stash incoming ICV for later cmp with ICV generated by the h/w */
- icvdata = edesc->buf + edesc->dma_len;
-
- sg_pcopy_to_buffer(req->src, edesc->src_nents ? : 1, icvdata, authsize,
- req->assoclen + req->cryptlen - authsize);
-
- return ipsec_esp(edesc, req, false, ipsec_esp_decrypt_swauth_done);
-}
-
-static struct talitos_alg_template driver_algs[] = {
- /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha384),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha384-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA384_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha384),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha384-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA384_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha512),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha512-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA512_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha512),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha512-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA512_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(aes))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(aes))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
-};
-
int talitos_init_common(struct talitos_ctx *ctx,
struct talitos_crypto_alg *talitos_alg)
{
@@ -1912,18 +1068,6 @@ int talitos_init_common(struct talitos_ctx *ctx,
return 0;
}
-static int talitos_cra_init_aead(struct crypto_aead *tfm)
-{
- struct aead_alg *alg = crypto_aead_alg(tfm);
- struct talitos_crypto_alg *talitos_alg;
- struct talitos_ctx *ctx = crypto_aead_ctx(tfm);
-
- talitos_alg = container_of(alg, struct talitos_crypto_alg,
- algt.alg.aead);
-
- return talitos_init_common(ctx, talitos_alg);
-}
-
void talitos_cra_exit(struct crypto_tfm *tfm)
{
struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
@@ -2034,6 +1178,12 @@ int talitos_register_common(struct device *dev,
t_alg->algt.type);
ret = crypto_register_skcipher(&t_alg->algt.alg.skcipher);
break;
+ case CRYPTO_ALG_TYPE_AEAD:
+ alg = &t_alg->algt.alg.aead.base;
+ talitos_alg_set_common(priv, alg, t_alg->algt.priority,
+ t_alg->algt.type);
+ ret = crypto_register_aead(&t_alg->algt.alg.aead);
+ break;
default:
dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
devm_kfree(dev, t_alg);
@@ -2054,59 +1204,6 @@ int talitos_register_common(struct device *dev,
return 0;
}
-static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
- struct talitos_alg_template
- *template)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
- struct talitos_crypto_alg *t_alg;
- struct crypto_alg *alg;
-
- t_alg = devm_kzalloc(dev, sizeof(struct talitos_crypto_alg),
- GFP_KERNEL);
- if (!t_alg)
- return ERR_PTR(-ENOMEM);
-
- t_alg->algt = *template;
-
- switch (t_alg->algt.type) {
- case CRYPTO_ALG_TYPE_AEAD:
- alg = &t_alg->algt.alg.aead.base;
- alg->cra_exit = talitos_cra_exit;
- t_alg->algt.alg.aead.init = talitos_cra_init_aead;
- t_alg->algt.alg.aead.setkey = t_alg->algt.alg.aead.setkey ?:
- aead_setkey;
- t_alg->algt.alg.aead.encrypt = aead_encrypt;
- t_alg->algt.alg.aead.decrypt = aead_decrypt;
- if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
- !strncmp(alg->cra_name, "authenc(hmac(sha224)", 20)) {
- devm_kfree(dev, t_alg);
- return ERR_PTR(-ENOTSUPP);
- }
- break;
- default:
- dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
- devm_kfree(dev, t_alg);
- return ERR_PTR(-EINVAL);
- }
-
- alg->cra_module = THIS_MODULE;
- if (t_alg->algt.priority)
- alg->cra_priority = t_alg->algt.priority;
- else
- alg->cra_priority = TALITOS_CRA_PRIORITY;
- if (has_ftr_sec1(priv) && t_alg->algt.type != CRYPTO_ALG_TYPE_AHASH)
- alg->cra_alignmask = 3;
- else
- alg->cra_alignmask = 0;
- alg->cra_ctxsize = sizeof(struct talitos_ctx);
- alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
-
- t_alg->dev = dev;
-
- return t_alg;
-}
-
static int talitos_probe_irq(struct platform_device *ofdev)
{
struct device *dev = &ofdev->dev;
@@ -2320,36 +1417,10 @@ static int talitos_probe(struct platform_device *ofdev)
if (err)
goto err_out;
- /* register crypto algorithms the device supports */
- for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
- if (talitos_hw_supports(dev,
- driver_algs[i].desc_hdr_template)) {
- struct talitos_crypto_alg *t_alg;
- struct crypto_alg *alg = NULL;
-
- t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
- if (IS_ERR(t_alg)) {
- err = PTR_ERR(t_alg);
- if (err == -ENOTSUPP)
- continue;
- goto err_out;
- }
+ err = talitos_register_aead(dev);
+ if (err)
+ goto err_out;
- switch (t_alg->algt.type) {
- case CRYPTO_ALG_TYPE_AEAD:
- err = crypto_register_aead(
- &t_alg->algt.alg.aead);
- alg = &t_alg->algt.alg.aead.base;
- break;
- }
- if (err) {
- dev_err(dev, "%s alg registration failed\n",
- alg->cra_driver_name);
- devm_kfree(dev, t_alg);
- } else
- list_add_tail(&t_alg->entry, &priv->alg_list);
- }
- }
if (!list_empty(&priv->alg_list))
dev_info(dev, "%s algorithms registered in /proc/crypto\n",
(char *)of_get_property(np, "compatible", NULL));
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 7e7d41673fa5..438be8c8f08d 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -21,6 +21,8 @@
#define TALITOS1_MAX_DATA_LEN 32768
#define TALITOS2_MAX_DATA_LEN 65535
+#define TALITOS_CRA_PRIORITY 3000
+
#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
@@ -535,3 +537,4 @@ void talitos_unregister_rng(struct device *dev);
int talitos_register_hash(struct device *dev);
int talitos_register_skcipher(struct device *dev);
+int talitos_register_aead(struct device *dev);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 10/29] crypto: talitos - Remove alg settings in talitos_register_common()
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (8 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 09/29] crypto: talitos/aead " Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 11/29] crypto: talitos - Remove unused priority field in struct talitos_alg_template Paul Louvel
` (18 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Algorithm properties should be set at definition time.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-aead.c | 131 +++++++++++++++++++++++-------
drivers/crypto/talitos/talitos-hash.c | 72 +++++++++++++---
drivers/crypto/talitos/talitos-skcipher.c | 51 ++++++++++--
drivers/crypto/talitos/talitos.c | 23 ------
4 files changed, 206 insertions(+), 71 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos/talitos-aead.c
index ce6bd6133fd0..c09ed08be2ef 100644
--- a/drivers/crypto/talitos/talitos-aead.c
+++ b/drivers/crypto/talitos/talitos-aead.c
@@ -409,7 +409,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-aes-talitos",
.cra_blocksize = AES_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
@@ -423,7 +427,6 @@ static struct talitos_alg_template aead_driver_algs[] = {
DESC_HDR_MODE1_MDEU_SHA1_HMAC,
},
{ .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
.alg.aead = {
.base = {
.cra_name = "authenc(hmac(sha1),cbc(aes))",
@@ -431,7 +434,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-aes-talitos-hsna",
.cra_blocksize = AES_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
@@ -453,7 +460,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-3des-talitos",
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
@@ -469,7 +480,6 @@ static struct talitos_alg_template aead_driver_algs[] = {
DESC_HDR_MODE1_MDEU_SHA1_HMAC,
},
{ .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
.alg.aead = {
.base = {
.cra_name = "authenc(hmac(sha1),"
@@ -478,7 +488,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-3des-talitos-hsna",
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
@@ -501,7 +515,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-aes-talitos",
.cra_blocksize = AES_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
@@ -515,7 +533,6 @@ static struct talitos_alg_template aead_driver_algs[] = {
DESC_HDR_MODE1_MDEU_SHA224_HMAC,
},
{ .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
.alg.aead = {
.base = {
.cra_name = "authenc(hmac(sha224),cbc(aes))",
@@ -523,7 +540,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-aes-talitos-hsna",
.cra_blocksize = AES_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
@@ -545,7 +566,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-3des-talitos",
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
@@ -561,7 +586,6 @@ static struct talitos_alg_template aead_driver_algs[] = {
DESC_HDR_MODE1_MDEU_SHA224_HMAC,
},
{ .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
.alg.aead = {
.base = {
.cra_name = "authenc(hmac(sha224),"
@@ -570,7 +594,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-3des-talitos-hsna",
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA224_DIGEST_SIZE,
@@ -593,7 +621,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-aes-talitos",
.cra_blocksize = AES_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
@@ -607,7 +639,6 @@ static struct talitos_alg_template aead_driver_algs[] = {
DESC_HDR_MODE1_MDEU_SHA256_HMAC,
},
{ .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
.alg.aead = {
.base = {
.cra_name = "authenc(hmac(sha256),cbc(aes))",
@@ -615,7 +646,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-aes-talitos-hsna",
.cra_blocksize = AES_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
@@ -637,7 +672,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-3des-talitos",
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
@@ -653,7 +692,6 @@ static struct talitos_alg_template aead_driver_algs[] = {
DESC_HDR_MODE1_MDEU_SHA256_HMAC,
},
{ .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
.alg.aead = {
.base = {
.cra_name = "authenc(hmac(sha256),"
@@ -662,7 +700,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-3des-talitos-hsna",
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
@@ -685,7 +727,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-aes-talitos",
.cra_blocksize = AES_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA384_DIGEST_SIZE,
@@ -707,7 +753,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-3des-talitos",
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA384_DIGEST_SIZE,
@@ -730,7 +780,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-aes-talitos",
.cra_blocksize = AES_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA512_DIGEST_SIZE,
@@ -752,7 +806,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-3des-talitos",
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA512_DIGEST_SIZE,
@@ -775,7 +833,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-aes-talitos",
.cra_blocksize = AES_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
@@ -789,7 +851,6 @@ static struct talitos_alg_template aead_driver_algs[] = {
DESC_HDR_MODE1_MDEU_MD5_HMAC,
},
{ .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
.alg.aead = {
.base = {
.cra_name = "authenc(hmac(md5),cbc(aes))",
@@ -797,7 +858,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-aes-talitos-hsna",
.cra_blocksize = AES_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
@@ -818,7 +883,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-3des-talitos",
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
@@ -834,7 +903,6 @@ static struct talitos_alg_template aead_driver_algs[] = {
DESC_HDR_MODE1_MDEU_MD5_HMAC,
},
{ .type = CRYPTO_ALG_TYPE_AEAD,
- .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
.alg.aead = {
.base = {
.cra_name = "authenc(hmac(md5),cbc(des3_ede))",
@@ -842,7 +910,11 @@ static struct talitos_alg_template aead_driver_algs[] = {
"cbc-3des-talitos-hsna",
.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
},
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = MD5_DIGEST_SIZE,
@@ -875,6 +947,9 @@ int talitos_register_aead(struct device *dev)
aead_alg = &aead_driver_algs[i].alg.aead;
alg = &aead_alg->base;
+ if (has_ftr_sec1(priv))
+ alg->cra_alignmask = 3;
+
alg->cra_exit = talitos_cra_exit;
aead_alg->init = talitos_cra_init_aead;
aead_alg->setkey = aead_alg->setkey ?: aead_setkey;
diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos/talitos-hash.c
index 5792e7093392..3793b6fd5b75 100644
--- a/drivers/crypto/talitos/talitos-hash.c
+++ b/drivers/crypto/talitos/talitos-hash.c
@@ -559,8 +559,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -578,8 +582,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -597,8 +605,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -616,8 +628,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -635,8 +651,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -654,8 +674,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -673,8 +697,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -692,8 +720,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -711,8 +743,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -730,8 +766,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -749,8 +789,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
@@ -768,8 +812,12 @@ static struct talitos_alg_template hash_driver_algs[] = {
.cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
.cra_flags = CRYPTO_ALG_ASYNC |
CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY |
+ CRYPTO_AHASH_ALG_BLOCK_ONLY |
CRYPTO_AHASH_ALG_FINAL_NONZERO,
+ .cra_priority = TALITOS_CRA_PRIORITY,
+ .cra_ctxsize = sizeof(struct talitos_ctx),
+ .cra_module = THIS_MODULE,
}
},
.desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/talitos/talitos-skcipher.c
index 4f742930ec47..ff7b8f9344c4 100644
--- a/drivers/crypto/talitos/talitos-skcipher.c
+++ b/drivers/crypto/talitos/talitos-skcipher.c
@@ -239,7 +239,11 @@ static struct talitos_alg_template skcipher_driver_algs[] = {
.base.cra_driver_name = "ecb-aes-talitos",
.base.cra_blocksize = AES_BLOCK_SIZE,
.base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .base.cra_priority = TALITOS_CRA_PRIORITY,
+ .base.cra_ctxsize = sizeof(struct talitos_ctx),
+ .base.cra_module = THIS_MODULE,
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.setkey = skcipher_aes_setkey,
@@ -253,7 +257,11 @@ static struct talitos_alg_template skcipher_driver_algs[] = {
.base.cra_driver_name = "cbc-aes-talitos",
.base.cra_blocksize = AES_BLOCK_SIZE,
.base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .base.cra_priority = TALITOS_CRA_PRIORITY,
+ .base.cra_ctxsize = sizeof(struct talitos_ctx),
+ .base.cra_module = THIS_MODULE,
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
@@ -269,7 +277,11 @@ static struct talitos_alg_template skcipher_driver_algs[] = {
.base.cra_driver_name = "ctr-aes-talitos",
.base.cra_blocksize = 1,
.base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .base.cra_priority = TALITOS_CRA_PRIORITY,
+ .base.cra_ctxsize = sizeof(struct talitos_ctx),
+ .base.cra_module = THIS_MODULE,
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
@@ -285,7 +297,11 @@ static struct talitos_alg_template skcipher_driver_algs[] = {
.base.cra_driver_name = "ctr-aes-talitos",
.base.cra_blocksize = 1,
.base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .base.cra_priority = TALITOS_CRA_PRIORITY,
+ .base.cra_ctxsize = sizeof(struct talitos_ctx),
+ .base.cra_module = THIS_MODULE,
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
.ivsize = AES_BLOCK_SIZE,
@@ -301,7 +317,11 @@ static struct talitos_alg_template skcipher_driver_algs[] = {
.base.cra_driver_name = "ecb-des-talitos",
.base.cra_blocksize = DES_BLOCK_SIZE,
.base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .base.cra_priority = TALITOS_CRA_PRIORITY,
+ .base.cra_ctxsize = sizeof(struct talitos_ctx),
+ .base.cra_module = THIS_MODULE,
.min_keysize = DES_KEY_SIZE,
.max_keysize = DES_KEY_SIZE,
.setkey = skcipher_des_setkey,
@@ -315,7 +335,11 @@ static struct talitos_alg_template skcipher_driver_algs[] = {
.base.cra_driver_name = "cbc-des-talitos",
.base.cra_blocksize = DES_BLOCK_SIZE,
.base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .base.cra_priority = TALITOS_CRA_PRIORITY,
+ .base.cra_ctxsize = sizeof(struct talitos_ctx),
+ .base.cra_module = THIS_MODULE,
.min_keysize = DES_KEY_SIZE,
.max_keysize = DES_KEY_SIZE,
.ivsize = DES_BLOCK_SIZE,
@@ -331,7 +355,11 @@ static struct talitos_alg_template skcipher_driver_algs[] = {
.base.cra_driver_name = "ecb-3des-talitos",
.base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .base.cra_priority = TALITOS_CRA_PRIORITY,
+ .base.cra_ctxsize = sizeof(struct talitos_ctx),
+ .base.cra_module = THIS_MODULE,
.min_keysize = DES3_EDE_KEY_SIZE,
.max_keysize = DES3_EDE_KEY_SIZE,
.setkey = skcipher_des3_setkey,
@@ -346,7 +374,11 @@ static struct talitos_alg_template skcipher_driver_algs[] = {
.base.cra_driver_name = "cbc-3des-talitos",
.base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
.base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY,
+ CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_KERN_DRIVER_ONLY,
+ .base.cra_priority = TALITOS_CRA_PRIORITY,
+ .base.cra_ctxsize = sizeof(struct talitos_ctx),
+ .base.cra_module = THIS_MODULE,
.min_keysize = DES3_EDE_KEY_SIZE,
.max_keysize = DES3_EDE_KEY_SIZE,
.ivsize = DES3_EDE_BLOCK_SIZE,
@@ -375,6 +407,9 @@ int talitos_register_skcipher(struct device *dev)
skcipher_alg = &skcipher_driver_algs[i].alg.skcipher;
alg = &skcipher_alg->base;
+ if (has_ftr_sec1(priv))
+ alg->cra_alignmask = 3;
+
alg->cra_exit = talitos_cra_exit;
skcipher_alg->init = talitos_cra_init_skcipher;
skcipher_alg->setkey = skcipher_alg->setkey ?: skcipher_setkey;
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 41d7d0e570e3..f38a156a0459 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -1133,23 +1133,6 @@ static void talitos_remove(struct platform_device *ofdev)
tasklet_kill(&priv->done_task[1]);
}
-static void talitos_alg_set_common(struct talitos_private *priv,
- struct crypto_alg *alg, u32 custom_priority,
- u32 type)
-{
- alg->cra_module = THIS_MODULE;
- if (custom_priority)
- alg->cra_priority = custom_priority;
- else
- alg->cra_priority = TALITOS_CRA_PRIORITY;
- if (has_ftr_sec1(priv) && type != CRYPTO_ALG_TYPE_AHASH)
- alg->cra_alignmask = 3;
- else
- alg->cra_alignmask = 0;
- alg->cra_ctxsize = sizeof(struct talitos_ctx);
- alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
-}
-
int talitos_register_common(struct device *dev,
struct talitos_alg_template *template)
{
@@ -1168,20 +1151,14 @@ int talitos_register_common(struct device *dev,
switch (t_alg->algt.type) {
case CRYPTO_ALG_TYPE_AHASH:
alg = &t_alg->algt.alg.hash.halg.base;
- talitos_alg_set_common(priv, alg, t_alg->algt.priority,
- t_alg->algt.type);
ret = crypto_register_ahash(&t_alg->algt.alg.hash);
break;
case CRYPTO_ALG_TYPE_SKCIPHER:
alg = &t_alg->algt.alg.skcipher.base;
- talitos_alg_set_common(priv, alg, t_alg->algt.priority,
- t_alg->algt.type);
ret = crypto_register_skcipher(&t_alg->algt.alg.skcipher);
break;
case CRYPTO_ALG_TYPE_AEAD:
alg = &t_alg->algt.alg.aead.base;
- talitos_alg_set_common(priv, alg, t_alg->algt.priority,
- t_alg->algt.type);
ret = crypto_register_aead(&t_alg->algt.alg.aead);
break;
default:
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 11/29] crypto: talitos - Remove unused priority field in struct talitos_alg_template
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (9 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 10/29] crypto: talitos - Remove alg settings in talitos_register_common() Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 12/29] crypto: talitos/hash - Convert to init_tfm/exit_tfm type-specific API Paul Louvel
` (17 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
After algorithm properties are now set at definition time, the priority
field in struct talitos_alg_template is no longer used. Remove it.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 438be8c8f08d..6cf3628c52c2 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -203,7 +203,6 @@ struct talitos_ctx {
struct talitos_alg_template {
u32 type;
- u32 priority;
union {
struct skcipher_alg skcipher;
struct ahash_alg hash;
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 12/29] crypto: talitos/hash - Convert to init_tfm/exit_tfm type-specific API
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (10 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 11/29] crypto: talitos - Remove unused priority field in struct talitos_alg_template Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 13/29] crypto: talitos/skcipher - Convert to init/exit " Paul Louvel
` (16 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Since commit 6eed1e3552fc0 ("crypto: api - Mark cra_init/cra_exit as
deprecated"), both cra_{init,exit} are deprecated.
Switch hash from the deprecated cra_init/cra_exit fields on crypto_alg
to the preferred init_tfm/exit_tfm fields on ahash_alg.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-hash.c | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos/talitos-hash.c
index 3793b6fd5b75..f7f6f01cfddf 100644
--- a/drivers/crypto/talitos/talitos-hash.c
+++ b/drivers/crypto/talitos/talitos-hash.c
@@ -531,22 +531,26 @@ static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
return 0;
}
-static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
+static int talitos_cra_init_ahash(struct crypto_ahash *tfm)
{
- struct crypto_alg *alg = tfm->__crt_alg;
+ struct ahash_alg *alg = crypto_ahash_alg(tfm);
struct talitos_crypto_alg *talitos_alg;
- struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
+ struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
- talitos_alg = container_of(__crypto_ahash_alg(alg),
+ talitos_alg = container_of(alg,
struct talitos_crypto_alg,
algt.alg.hash);
ctx->keylen = 0;
- sizeof(struct talitos_ahash_req_ctx));
return talitos_init_common(ctx, talitos_alg);
}
+static void talitos_cra_exit_ahash(struct crypto_ahash *tfm)
+{
+ talitos_cra_exit(crypto_ahash_tfm(tfm));
+}
+
static struct talitos_alg_template hash_driver_algs[] = {
{ .type = CRYPTO_ALG_TYPE_AHASH,
.alg.hash = {
@@ -842,8 +846,8 @@ int talitos_register_hash(struct device *dev)
ahash_alg = &hash_driver_algs[i].alg.hash;
alg = &ahash_alg->halg.base;
- alg->cra_init = talitos_cra_init_ahash;
- alg->cra_exit = talitos_cra_exit;
+ ahash_alg->init_tfm = talitos_cra_init_ahash;
+ ahash_alg->exit_tfm = talitos_cra_exit_ahash;
ahash_alg->init = ahash_init;
ahash_alg->update = ahash_update;
ahash_alg->final = ahash_final;
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 13/29] crypto: talitos/skcipher - Convert to init/exit type-specific API
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (11 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 12/29] crypto: talitos/hash - Convert to init_tfm/exit_tfm type-specific API Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 14/29] crypto: talitos/aead " Paul Louvel
` (15 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Since commit 6eed1e3552fc0 ("crypto: api - Mark cra_init/cra_exit as
deprecated"), both cra_{init,exit} are deprecated.
Restore the type-specific talitos_cra_exit_skcipher() wrapper and use
skcipher_alg->exit instead of the generic cra_exit field, matching the
pattern used by init.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-skcipher.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/talitos/talitos-skcipher.c
index ff7b8f9344c4..f86a0a9a0ffe 100644
--- a/drivers/crypto/talitos/talitos-skcipher.c
+++ b/drivers/crypto/talitos/talitos-skcipher.c
@@ -232,6 +232,11 @@ static int talitos_cra_init_skcipher(struct crypto_skcipher *tfm)
return talitos_init_common(ctx, talitos_alg);
}
+static void talitos_cra_exit_skcipher(struct crypto_skcipher *tfm)
+{
+ talitos_cra_exit(crypto_skcipher_tfm(tfm));
+}
+
static struct talitos_alg_template skcipher_driver_algs[] = {
{ .type = CRYPTO_ALG_TYPE_SKCIPHER,
.alg.skcipher = {
@@ -410,8 +415,8 @@ int talitos_register_skcipher(struct device *dev)
if (has_ftr_sec1(priv))
alg->cra_alignmask = 3;
- alg->cra_exit = talitos_cra_exit;
skcipher_alg->init = talitos_cra_init_skcipher;
+ skcipher_alg->exit = talitos_cra_exit_skcipher;
skcipher_alg->setkey = skcipher_alg->setkey ?: skcipher_setkey;
skcipher_alg->encrypt = skcipher_encrypt;
skcipher_alg->decrypt = skcipher_decrypt;
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 14/29] crypto: talitos/aead - Convert to init/exit type-specific API
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (12 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 13/29] crypto: talitos/skcipher - Convert to init/exit " Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 15/29] crypto: talitos/hash - Use macro for algorithm definitions Paul Louvel
` (14 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Since commit 6eed1e3552fc0 ("crypto: api - Mark cra_init/cra_exit as
deprecated"), both cra_{init,exit} are deprecated.
Restore the type-specific talitos_cra_exit_aead() wrapper and use
aead_alg->exit instead of the generic cra_exit field, matching the
pattern used by init.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-aead.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos/talitos-aead.c
index c09ed08be2ef..38df616c9b22 100644
--- a/drivers/crypto/talitos/talitos-aead.c
+++ b/drivers/crypto/talitos/talitos-aead.c
@@ -400,6 +400,11 @@ static int talitos_cra_init_aead(struct crypto_aead *tfm)
return talitos_init_common(ctx, talitos_alg);
}
+static void talitos_cra_exit_aead(struct crypto_aead *tfm)
+{
+ talitos_cra_exit(crypto_aead_tfm(tfm));
+}
+
static struct talitos_alg_template aead_driver_algs[] = {
{ .type = CRYPTO_ALG_TYPE_AEAD,
.alg.aead = {
@@ -950,8 +955,8 @@ int talitos_register_aead(struct device *dev)
if (has_ftr_sec1(priv))
alg->cra_alignmask = 3;
- alg->cra_exit = talitos_cra_exit;
aead_alg->init = talitos_cra_init_aead;
+ aead_alg->exit = talitos_cra_exit_aead;
aead_alg->setkey = aead_alg->setkey ?: aead_setkey;
aead_alg->encrypt = aead_encrypt;
aead_alg->decrypt = aead_decrypt;
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 15/29] crypto: talitos/hash - Use macro for algorithm definitions
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (13 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 14/29] crypto: talitos/aead " Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 16/29] crypto: talitos/skcipher " Paul Louvel
` (13 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Replace the repetitive struct initializer entries in hash_driver_algs[]
with preprocessor macros (TALITOS_HASH_ALG, TALITOS_HMAC_HASH_ALG).
Remove the function pointer assignments (init_tfm, exit_tfm, init, update,
final, finup, digest, export, import).
The HMAC setkey assignment, previously done by comparing the algorithm
name at runtime, is now handled by passing ahash_setkey directly through
the TALITOS_HMAC_HASH_ALG macro variant.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-hash.c | 392 +++++++++-------------------------
1 file changed, 104 insertions(+), 288 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos/talitos-hash.c
index f7f6f01cfddf..9e6d849c3123 100644
--- a/drivers/crypto/talitos/talitos-hash.c
+++ b/drivers/crypto/talitos/talitos-hash.c
@@ -551,283 +551,111 @@ static void talitos_cra_exit_ahash(struct crypto_ahash *tfm)
talitos_cra_exit(crypto_ahash_tfm(tfm));
}
-static struct talitos_alg_template hash_driver_algs[] = {
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = MD5_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "md5",
- .cra_driver_name = "md5-talitos",
- .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_MD5,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA1_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha1",
- .cra_driver_name = "sha1-talitos",
- .cra_blocksize = SHA1_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA1,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA224_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha224",
- .cra_driver_name = "sha224-talitos",
- .cra_blocksize = SHA224_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA224,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA256_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha256",
- .cra_driver_name = "sha256-talitos",
- .cra_blocksize = SHA256_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA256,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA384_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha384",
- .cra_driver_name = "sha384-talitos",
- .cra_blocksize = SHA384_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA384,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA512_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "sha512",
- .cra_driver_name = "sha512-talitos",
- .cra_blocksize = SHA512_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA512,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = MD5_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(md5)",
- .cra_driver_name = "hmac-md5-talitos",
- .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_MD5,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA1_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha1)",
- .cra_driver_name = "hmac-sha1-talitos",
- .cra_blocksize = SHA1_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA1,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA224_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha224)",
- .cra_driver_name = "hmac-sha224-talitos",
- .cra_blocksize = SHA224_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA224,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA256_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha256)",
- .cra_driver_name = "hmac-sha256-talitos",
- .cra_blocksize = SHA256_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUA |
- DESC_HDR_MODE0_MDEU_SHA256,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA384_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha384)",
- .cra_driver_name = "hmac-sha384-talitos",
- .cra_blocksize = SHA384_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA384,
- },
- { .type = CRYPTO_ALG_TYPE_AHASH,
- .alg.hash = {
- .halg.digestsize = SHA512_DIGEST_SIZE,
- .halg.statesize = sizeof(struct talitos_export_state),
- .halg.base = {
- .cra_name = "hmac(sha512)",
- .cra_driver_name = "hmac-sha512-talitos",
- .cra_blocksize = SHA512_BLOCK_SIZE,
- .cra_reqsize = sizeof(struct talitos_ahash_req_ctx),
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY |
- CRYPTO_AHASH_ALG_BLOCK_ONLY |
- CRYPTO_AHASH_ALG_FINAL_NONZERO,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- }
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_MDEUB |
- DESC_HDR_MODE0_MDEUB_SHA512,
+#define TALITOS_HASH_ALG_COMMON(name, digest_size, block_size, template, \
+ set_key) \
+ { \
+ .type = CRYPTO_ALG_TYPE_AHASH, \
+ .alg.hash = { \
+ .init_tfm = talitos_cra_init_ahash, \
+ .exit_tfm = talitos_cra_exit_ahash, \
+ .init = ahash_init, \
+ .update = ahash_update, \
+ .final = ahash_final, \
+ .finup = ahash_finup, \
+ .digest = ahash_digest, \
+ .setkey = set_key, \
+ .import = ahash_import, \
+ .export = ahash_export, \
+ .halg.digestsize = digest_size, \
+ .halg.statesize = sizeof(struct talitos_export_state), \
+ .halg.base = { \
+ .cra_name = name, \
+ .cra_driver_name = name"-talitos", \
+ .cra_blocksize = block_size, \
+ .cra_reqsize = sizeof(struct talitos_ahash_req_ctx), \
+ .cra_flags = CRYPTO_ALG_ASYNC | \
+ CRYPTO_ALG_ALLOCATES_MEMORY | \
+ CRYPTO_ALG_KERN_DRIVER_ONLY | \
+ CRYPTO_AHASH_ALG_BLOCK_ONLY | \
+ CRYPTO_AHASH_ALG_FINAL_NONZERO, \
+ .cra_priority = TALITOS_CRA_PRIORITY, \
+ .cra_ctxsize = sizeof(struct talitos_ctx), \
+ .cra_module = THIS_MODULE, \
+ }, \
+ }, \
+ .desc_hdr_template = template, \
}
+
+#define TALITOS_HASH_ALG(name, digest_size, block_size, desc_hdr_template) \
+ TALITOS_HASH_ALG_COMMON(name, digest_size, block_size, \
+ desc_hdr_template, NULL)
+
+#define TALITOS_HMAC_HASH_ALG(name, digest_size, block_size, \
+ desc_hdr_template) \
+ TALITOS_HASH_ALG_COMMON("hmac(" name ")", digest_size, block_size, \
+ desc_hdr_template, ahash_setkey)
+
+static struct talitos_alg_template hash_driver_algs[] = {
+ TALITOS_HASH_ALG("md5", MD5_DIGEST_SIZE, MD5_HMAC_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA | DESC_HDR_MODE0_MDEU_MD5),
+
+ TALITOS_HASH_ALG("sha1", SHA1_DIGEST_SIZE, SHA1_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA1),
+
+ TALITOS_HASH_ALG("sha224", SHA224_DIGEST_SIZE, SHA224_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA224),
+
+ TALITOS_HASH_ALG("sha256", SHA256_DIGEST_SIZE, SHA256_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA256),
+
+ TALITOS_HASH_ALG("sha384", SHA384_DIGEST_SIZE, SHA384_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA384),
+
+ TALITOS_HASH_ALG("sha512", SHA512_DIGEST_SIZE, SHA512_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA512),
+
+ /* HMAC */
+
+ TALITOS_HMAC_HASH_ALG("md5", MD5_DIGEST_SIZE, MD5_HMAC_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_MD5),
+
+ TALITOS_HMAC_HASH_ALG("sha1", SHA1_DIGEST_SIZE, SHA1_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA1),
+
+ TALITOS_HMAC_HASH_ALG("sha224", SHA224_DIGEST_SIZE, SHA224_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA224),
+
+ TALITOS_HMAC_HASH_ALG("sha256", SHA256_DIGEST_SIZE, SHA256_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUA |
+ DESC_HDR_MODE0_MDEU_SHA256),
+
+ TALITOS_HMAC_HASH_ALG("sha384", SHA384_DIGEST_SIZE, SHA384_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA384),
+
+ TALITOS_HMAC_HASH_ALG("sha512", SHA512_DIGEST_SIZE, SHA512_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_MDEUB |
+ DESC_HDR_MODE0_MDEUB_SHA512),
};
int talitos_register_hash(struct device *dev)
@@ -846,18 +674,6 @@ int talitos_register_hash(struct device *dev)
ahash_alg = &hash_driver_algs[i].alg.hash;
alg = &ahash_alg->halg.base;
- ahash_alg->init_tfm = talitos_cra_init_ahash;
- ahash_alg->exit_tfm = talitos_cra_exit_ahash;
- ahash_alg->init = ahash_init;
- ahash_alg->update = ahash_update;
- ahash_alg->final = ahash_final;
- ahash_alg->finup = ahash_finup;
- ahash_alg->digest = ahash_digest;
- if (!strncmp(alg->cra_name, "hmac", 4))
- ahash_alg->setkey = ahash_setkey;
- ahash_alg->import = ahash_import;
- ahash_alg->export = ahash_export;
-
if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
!strncmp(alg->cra_name, "hmac", 4)) {
/* not supported */
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 16/29] crypto: talitos/skcipher - Use macro for algorithm definitions
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (14 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 15/29] crypto: talitos/hash - Use macro for algorithm definitions Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 17/29] crypto: talitos/aead " Paul Louvel
` (12 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Replace the repetitive struct initializer entries in
skcipher_driver_algs[] with preprocessor macros
(TALITOS_SKCIPHER_ALG_AES, TALITOS_SKCIPHER_ALG_DES,
TALITOS_SKCIPHER_ALG_DES3).
Move the function pointer assignments (init, exit, encrypt, decrypt)
from the registration loop into the static initializer, since they are
identical for all algorithms.
The fallback setkey assignment (skcipher_alg->setkey ?: skcipher_setkey)
is no longer needed because each macro specifies the correct setkey
handler directly.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-skcipher.c | 244 ++++++++++--------------------
1 file changed, 82 insertions(+), 162 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/talitos/talitos-skcipher.c
index f86a0a9a0ffe..b12191243aae 100644
--- a/drivers/crypto/talitos/talitos-skcipher.c
+++ b/drivers/crypto/talitos/talitos-skcipher.c
@@ -237,163 +237,89 @@ static void talitos_cra_exit_skcipher(struct crypto_skcipher *tfm)
talitos_cra_exit(crypto_skcipher_tfm(tfm));
}
+#define TALITOS_SKCIPHER_ALG_COMMON(name, blk_sz, iv_sz, min_ksz, max_ksz, \
+ set_key, desc_template) \
+ { \
+ .type = CRYPTO_ALG_TYPE_SKCIPHER, \
+ .alg.skcipher = { \
+ .base.cra_name = name, \
+ .base.cra_driver_name = name"-talitos", \
+ .base.cra_blocksize = blk_sz, \
+ .base.cra_flags = CRYPTO_ALG_ASYNC | \
+ CRYPTO_ALG_ALLOCATES_MEMORY | \
+ CRYPTO_ALG_KERN_DRIVER_ONLY, \
+ .base.cra_priority = TALITOS_CRA_PRIORITY, \
+ .base.cra_ctxsize = sizeof(struct talitos_ctx), \
+ .base.cra_module = THIS_MODULE, \
+ .min_keysize = min_ksz, \
+ .max_keysize = max_ksz, \
+ .ivsize = iv_sz, \
+ .setkey = set_key, \
+ .init = talitos_cra_init_skcipher, \
+ .exit = talitos_cra_exit_skcipher, \
+ .encrypt = skcipher_encrypt, \
+ .decrypt = skcipher_decrypt, \
+ }, \
+ .desc_hdr_template = desc_template, \
+ }
+
+#define TALITOS_SKCIPHER_ALG_AES(name, blk_sz, iv_sz, desc_template) \
+ TALITOS_SKCIPHER_ALG_COMMON(name, blk_sz, iv_sz, AES_MIN_KEY_SIZE, \
+ AES_MAX_KEY_SIZE, skcipher_aes_setkey, \
+ desc_template)
+
+#define TALITOS_SKCIPHER_ALG_DES(name, blk_sz, iv_sz, desc_template) \
+ TALITOS_SKCIPHER_ALG_COMMON(name, blk_sz, iv_sz, DES_KEY_SIZE, \
+ DES_KEY_SIZE, skcipher_des_setkey, \
+ desc_template)
+
+#define TALITOS_SKCIPHER_ALG_DES3(name, blk_sz, iv_sz, desc_template) \
+ TALITOS_SKCIPHER_ALG_COMMON(name, blk_sz, iv_sz, DES3_EDE_KEY_SIZE, \
+ DES3_EDE_KEY_SIZE, skcipher_des3_setkey, \
+ desc_template)
+
static struct talitos_alg_template skcipher_driver_algs[] = {
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(aes)",
- .base.cra_driver_name = "ecb-aes-talitos",
- .base.cra_blocksize = AES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .base.cra_priority = TALITOS_CRA_PRIORITY,
- .base.cra_ctxsize = sizeof(struct talitos_ctx),
- .base.cra_module = THIS_MODULE,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(aes)",
- .base.cra_driver_name = "cbc-aes-talitos",
- .base.cra_blocksize = AES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .base.cra_priority = TALITOS_CRA_PRIORITY,
- .base.cra_ctxsize = sizeof(struct talitos_ctx),
- .base.cra_module = THIS_MODULE,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ctr(aes)",
- .base.cra_driver_name = "ctr-aes-talitos",
- .base.cra_blocksize = 1,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .base.cra_priority = TALITOS_CRA_PRIORITY,
- .base.cra_ctxsize = sizeof(struct talitos_ctx),
- .base.cra_module = THIS_MODULE,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_AESU_CTR_NONSNOOP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CTR,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ctr(aes)",
- .base.cra_driver_name = "ctr-aes-talitos",
- .base.cra_blocksize = 1,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .base.cra_priority = TALITOS_CRA_PRIORITY,
- .base.cra_ctxsize = sizeof(struct talitos_ctx),
- .base.cra_module = THIS_MODULE,
- .min_keysize = AES_MIN_KEY_SIZE,
- .max_keysize = AES_MAX_KEY_SIZE,
- .ivsize = AES_BLOCK_SIZE,
- .setkey = skcipher_aes_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CTR,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(des)",
- .base.cra_driver_name = "ecb-des-talitos",
- .base.cra_blocksize = DES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .base.cra_priority = TALITOS_CRA_PRIORITY,
- .base.cra_ctxsize = sizeof(struct talitos_ctx),
- .base.cra_module = THIS_MODULE,
- .min_keysize = DES_KEY_SIZE,
- .max_keysize = DES_KEY_SIZE,
- .setkey = skcipher_des_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(des)",
- .base.cra_driver_name = "cbc-des-talitos",
- .base.cra_blocksize = DES_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .base.cra_priority = TALITOS_CRA_PRIORITY,
- .base.cra_ctxsize = sizeof(struct talitos_ctx),
- .base.cra_module = THIS_MODULE,
- .min_keysize = DES_KEY_SIZE,
- .max_keysize = DES_KEY_SIZE,
- .ivsize = DES_BLOCK_SIZE,
- .setkey = skcipher_des_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "ecb(des3_ede)",
- .base.cra_driver_name = "ecb-3des-talitos",
- .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .base.cra_priority = TALITOS_CRA_PRIORITY,
- .base.cra_ctxsize = sizeof(struct talitos_ctx),
- .base.cra_module = THIS_MODULE,
- .min_keysize = DES3_EDE_KEY_SIZE,
- .max_keysize = DES3_EDE_KEY_SIZE,
- .setkey = skcipher_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_3DES,
- },
- { .type = CRYPTO_ALG_TYPE_SKCIPHER,
- .alg.skcipher = {
- .base.cra_name = "cbc(des3_ede)",
- .base.cra_driver_name = "cbc-3des-talitos",
- .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .base.cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .base.cra_priority = TALITOS_CRA_PRIORITY,
- .base.cra_ctxsize = sizeof(struct talitos_ctx),
- .base.cra_module = THIS_MODULE,
- .min_keysize = DES3_EDE_KEY_SIZE,
- .max_keysize = DES3_EDE_KEY_SIZE,
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .setkey = skcipher_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES,
- },
+ /* AES */
+
+ TALITOS_SKCIPHER_ALG_AES("ecb(aes)", AES_BLOCK_SIZE, 0,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU),
+
+ TALITOS_SKCIPHER_ALG_AES("cbc(aes)", AES_BLOCK_SIZE, AES_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC),
+
+ TALITOS_SKCIPHER_ALG_AES("ctr(aes)", 1, AES_BLOCK_SIZE,
+ DESC_HDR_TYPE_AESU_CTR_NONSNOOP |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CTR),
+
+ TALITOS_SKCIPHER_ALG_AES("ctr(aes)", 1, AES_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CTR),
+ /* DES */
+
+ TALITOS_SKCIPHER_ALG_DES("ecb(des)", DES_BLOCK_SIZE, 0,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU),
+
+ TALITOS_SKCIPHER_ALG_DES("cbc(des)", DES_BLOCK_SIZE, DES_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC),
+ /* DES3 */
+
+ TALITOS_SKCIPHER_ALG_DES3("ecb(des3_ede)", DES3_EDE_BLOCK_SIZE, 0,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
+ DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_3DES),
+
+ TALITOS_SKCIPHER_ALG_DES3(
+ "cbc(des3_ede)", DES3_EDE_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE,
+ DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES),
};
int talitos_register_skcipher(struct device *dev)
@@ -415,12 +341,6 @@ int talitos_register_skcipher(struct device *dev)
if (has_ftr_sec1(priv))
alg->cra_alignmask = 3;
- skcipher_alg->init = talitos_cra_init_skcipher;
- skcipher_alg->exit = talitos_cra_exit_skcipher;
- skcipher_alg->setkey = skcipher_alg->setkey ?: skcipher_setkey;
- skcipher_alg->encrypt = skcipher_encrypt;
- skcipher_alg->decrypt = skcipher_decrypt;
-
if (!strcmp(alg->cra_name, "ctr(aes)") && !has_ftr_sec1(priv) &&
DESC_TYPE(skcipher_driver_algs[i].desc_hdr_template) !=
DESC_TYPE(DESC_HDR_TYPE_AESU_CTR_NONSNOOP)) {
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 17/29] crypto: talitos/aead - Use macro for algorithm definitions
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (15 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 16/29] crypto: talitos/skcipher " Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 18/29] crypto: talitos - Split SEC1/SEC2 code into separate function variants Paul Louvel
` (11 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Replace the repetitive struct initializer entries in aead_driver_algs[]
with preprocessor macros (TALITOS_AEAD_ALG, TALITOS_AEAD_ALG_HSNA).
Move the function pointer assignments (init, exit, encrypt, decrypt)
from the registration loop into the static initializer, since they are
identical for all algorithms.
The fallback setkey assignment (aead_alg->setkey ?: aead_setkey) is
replaced by specifying the correct setkey handler directly in each macro
invocation.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-aead.c | 751 ++++++++++------------------------
1 file changed, 218 insertions(+), 533 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos/talitos-aead.c
index 38df616c9b22..cd1b8e6d371b 100644
--- a/drivers/crypto/talitos/talitos-aead.c
+++ b/drivers/crypto/talitos/talitos-aead.c
@@ -405,535 +405,225 @@ static void talitos_cra_exit_aead(struct crypto_aead *tfm)
talitos_cra_exit(crypto_aead_tfm(tfm));
}
+#define TALITOS_AEAD_ALG_COMMON(name, name_prefix, set_key, block_size, \
+ max_auth_size, template, priority) \
+ { \
+ .type = CRYPTO_ALG_TYPE_AEAD, \
+ .alg.aead = { \
+ .base = { \
+ .cra_name = name, \
+ .cra_driver_name = name"-talitos"name_prefix, \
+ .cra_blocksize = block_size, \
+ .cra_flags = CRYPTO_ALG_ASYNC | \
+ CRYPTO_ALG_ALLOCATES_MEMORY | \
+ CRYPTO_ALG_KERN_DRIVER_ONLY, \
+ .cra_priority = (priority), \
+ .cra_ctxsize = sizeof(struct talitos_ctx), \
+ .cra_module = THIS_MODULE, \
+ }, \
+ .ivsize = block_size, \
+ .maxauthsize = max_auth_size, \
+ .setkey = set_key, \
+ .init = talitos_cra_init_aead, \
+ .exit = talitos_cra_exit_aead, \
+ .encrypt = aead_encrypt, \
+ .decrypt = aead_decrypt, \
+ }, \
+ .desc_hdr_template = template, \
+ }
+
+#define TALITOS_AEAD_ALG(name, set_key, block_size, max_auth_size, template) \
+ TALITOS_AEAD_ALG_COMMON(name, "", set_key, block_size, max_auth_size, \
+ template, TALITOS_CRA_PRIORITY)
+
+#define TALITOS_AEAD_ALG_HSNA(name, set_key, block_size, max_auth_size, \
+ template) \
+ TALITOS_AEAD_ALG_COMMON(name, "-hsna", set_key, block_size, \
+ max_auth_size, template, \
+ TALITOS_CRA_PRIORITY_AEAD_HSNA)
+
static struct talitos_alg_template aead_driver_algs[] = {
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha1),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha1-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA1_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA1_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha224),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha224-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA224_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA224_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha256),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha256-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA256_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_SHA256_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha384),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha384-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA384_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha384),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha384-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA384_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha512),cbc(aes))",
- .cra_driver_name = "authenc-hmac-sha512-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = SHA512_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(sha512),"
- "cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-sha512-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = SHA512_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUB |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(aes))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-aes-talitos",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(aes))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-aes-talitos-hsna",
- .cra_blocksize = AES_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = AES_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_AESU |
- DESC_HDR_MODE0_AESU_CBC |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-3des-talitos",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
- { .type = CRYPTO_ALG_TYPE_AEAD,
- .alg.aead = {
- .base = {
- .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
- .cra_driver_name = "authenc-hmac-md5-"
- "cbc-3des-talitos-hsna",
- .cra_blocksize = DES3_EDE_BLOCK_SIZE,
- .cra_flags = CRYPTO_ALG_ASYNC |
- CRYPTO_ALG_ALLOCATES_MEMORY |
- CRYPTO_ALG_KERN_DRIVER_ONLY,
- .cra_priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
- .cra_ctxsize = sizeof(struct talitos_ctx),
- .cra_module = THIS_MODULE,
- },
- .ivsize = DES3_EDE_BLOCK_SIZE,
- .maxauthsize = MD5_DIGEST_SIZE,
- .setkey = aead_des3_setkey,
- },
- .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
- DESC_HDR_SEL0_DEU |
- DESC_HDR_MODE0_DEU_CBC |
- DESC_HDR_MODE0_DEU_3DES |
- DESC_HDR_SEL1_MDEUA |
- DESC_HDR_MODE1_MDEU_INIT |
- DESC_HDR_MODE1_MDEU_PAD |
- DESC_HDR_MODE1_MDEU_MD5_HMAC,
- },
+ /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
+
+ /* sha1 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha1),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, SHA1_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha1),cbc(aes))", aead_setkey, AES_BLOCK_SIZE,
+ SHA1_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC),
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha1),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA1_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC |
+ DESC_HDR_MODE0_DEU_3DES | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha1),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA1_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA1_HMAC),
+
+ /* sha224 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha224),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, SHA224_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha224),cbc(aes))", aead_setkey, AES_BLOCK_SIZE,
+ SHA224_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC),
+
+ TALITOS_AEAD_ALG(
+ "authenc(hmac(sha224),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA224_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha224),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA224_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA224_HMAC),
+
+ /* sha256 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha256),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, SHA256_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha256),cbc(aes))", aead_setkey, AES_BLOCK_SIZE,
+ SHA256_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC),
+
+ TALITOS_AEAD_ALG(
+ "authenc(hmac(sha256),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA256_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(sha256),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA256_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_SHA256_HMAC),
+
+ /* sha384 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha384),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, SHA384_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA384_HMAC),
+
+ TALITOS_AEAD_ALG(
+ "authenc(hmac(sha384),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA384_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUB | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA384_HMAC),
+
+ /* sha512 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(sha512),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, SHA512_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUB |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA512_HMAC),
+
+ TALITOS_AEAD_ALG(
+ "authenc(hmac(sha512),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, SHA512_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUB | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEUB_SHA512_HMAC),
+
+ /* md5 auth */
+
+ TALITOS_AEAD_ALG("authenc(hmac(md5),cbc(aes))", aead_setkey,
+ AES_BLOCK_SIZE, MD5_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(md5),cbc(aes))", aead_setkey, AES_BLOCK_SIZE,
+ MD5_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_AESU |
+ DESC_HDR_MODE0_AESU_CBC | DESC_HDR_SEL1_MDEUA |
+ DESC_HDR_MODE1_MDEU_INIT | DESC_HDR_MODE1_MDEU_PAD |
+ DESC_HDR_MODE1_MDEU_MD5_HMAC),
+
+ TALITOS_AEAD_ALG(
+ "authenc(hmac(md5),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, MD5_DIGEST_SIZE,
+ DESC_HDR_TYPE_IPSEC_ESP | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD | DESC_HDR_MODE1_MDEU_MD5_HMAC),
+
+ TALITOS_AEAD_ALG_HSNA(
+ "authenc(hmac(md5),cbc(des3_ede))", aead_des3_setkey,
+ DES3_EDE_BLOCK_SIZE, MD5_DIGEST_SIZE,
+ DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU | DESC_HDR_SEL0_DEU |
+ DESC_HDR_MODE0_DEU_CBC | DESC_HDR_MODE0_DEU_3DES |
+ DESC_HDR_SEL1_MDEUA | DESC_HDR_MODE1_MDEU_INIT |
+ DESC_HDR_MODE1_MDEU_PAD | DESC_HDR_MODE1_MDEU_MD5_HMAC),
};
int talitos_register_aead(struct device *dev)
@@ -955,11 +645,6 @@ int talitos_register_aead(struct device *dev)
if (has_ftr_sec1(priv))
alg->cra_alignmask = 3;
- aead_alg->init = talitos_cra_init_aead;
- aead_alg->exit = talitos_cra_exit_aead;
- aead_alg->setkey = aead_alg->setkey ?: aead_setkey;
- aead_alg->encrypt = aead_encrypt;
- aead_alg->decrypt = aead_decrypt;
if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
!strncmp(alg->cra_name, "authenc(hmac(sha224)", 20)) {
continue;
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 18/29] crypto: talitos - Split SEC1/SEC2 code into separate function variants
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (16 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 17/29] crypto: talitos/aead " Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 19/29] crypto: talitos - Introduce struct talitos_ops Paul Louvel
` (10 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Split the functions that have SEC1/SEC2-specific behavior into
separate sec1_ and sec2_ function variants, removing the runtime
is_sec1 checks from within each function body.
The callers still dispatch between the two variants using local
is_sec1 variables and if/else checks.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 524 +++++++++++++++++++++++++--------------
drivers/crypto/talitos/talitos.h | 36 ++-
2 files changed, 357 insertions(+), 203 deletions(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index f38a156a0459..b6793d97735e 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -133,75 +133,124 @@ void unmap_single_talitos_ptr(struct device *dev,
from_talitos_ptr_len(ptr, is_sec1), dir);
}
-static int reset_channel(struct device *dev, int ch)
+static int sec1_reset_channel(struct device *dev, int ch)
{
struct talitos_private *priv = dev_get_drvdata(dev);
unsigned int timeout = TALITOS_TIMEOUT;
- bool is_sec1 = has_ftr_sec1(priv);
- if (is_sec1) {
- setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
- TALITOS1_CCCR_LO_RESET);
+ setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS1_CCCR_LO_RESET);
- while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR_LO) &
- TALITOS1_CCCR_LO_RESET) && --timeout)
- cpu_relax();
- } else {
- setbits32(priv->chan[ch].reg + TALITOS_CCCR,
- TALITOS2_CCCR_RESET);
+ while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR_LO) &
+ TALITOS1_CCCR_LO_RESET) &&
+ --timeout)
+ cpu_relax();
- while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
- TALITOS2_CCCR_RESET) && --timeout)
- cpu_relax();
+ if (timeout == 0) {
+ dev_err(dev, "failed to reset sec1 channel %d\n", ch);
+ return -EIO;
}
+ setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
+ TALITOS_CCCR_LO_NE | TALITOS_CCCR_LO_CDIE |
+ TALITOS_CCCR_LO_CDWE);
+
+ return 0;
+}
+
+static int sec2_reset_channel(struct device *dev, int ch)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ unsigned int timeout = TALITOS_TIMEOUT;
+
+ setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS2_CCCR_RESET);
+
+ while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
+ TALITOS2_CCCR_RESET) &&
+ --timeout)
+ cpu_relax();
+
if (timeout == 0) {
- dev_err(dev, "failed to reset channel %d\n", ch);
+ dev_err(dev, "failed to reset sec2 channel %d\n", ch);
return -EIO;
}
- /* set 36-bit addressing, done writeback enable and done IRQ enable */
- setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
- TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
- /* enable chaining descriptors */
- if (is_sec1)
- setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
- TALITOS_CCCR_LO_NE);
+ setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
+ TALITOS_CCCR_LO_EAE | TALITOS_CCCR_LO_CDWE |
+ TALITOS_CCCR_LO_CDIE);
- /* and ICCR writeback, if available */
+ /* ICCR writeback, if available */
if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
- TALITOS_CCCR_LO_IWSE);
+ TALITOS_CCCR_LO_IWSE);
return 0;
}
-static int reset_device(struct device *dev)
+static int sec1_reset_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
unsigned int timeout = TALITOS_TIMEOUT;
- bool is_sec1 = has_ftr_sec1(priv);
- u32 mcr = is_sec1 ? TALITOS1_MCR_SWR : TALITOS2_MCR_SWR;
- setbits32(priv->reg + TALITOS_MCR, mcr);
+ setbits32(priv->reg + TALITOS_MCR, TALITOS1_MCR_SWR);
- while ((in_be32(priv->reg + TALITOS_MCR) & mcr)
- && --timeout)
+ while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS1_MCR_SWR) &&
+ --timeout)
cpu_relax();
- if (priv->irq[1]) {
- mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
- setbits32(priv->reg + TALITOS_MCR, mcr);
+ if (timeout == 0) {
+ dev_err(dev, "failed to reset sec1 device\n");
+ return -EIO;
}
+ return 0;
+}
+
+static int sec2_reset_device(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ unsigned int timeout = TALITOS_TIMEOUT;
+
+ setbits32(priv->reg + TALITOS_MCR, TALITOS2_MCR_SWR);
+
+ while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS2_MCR_SWR) &&
+ --timeout)
+ cpu_relax();
+
+ if (priv->irq[1])
+ setbits32(priv->reg + TALITOS_MCR,
+ TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3);
+
if (timeout == 0) {
- dev_err(dev, "failed to reset device\n");
+ dev_err(dev, "failed to reset sec2 device\n");
return -EIO;
}
return 0;
}
+static void sec1_configure_device(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ clrbits32(priv->reg + TALITOS_IMR, TALITOS1_IMR_INIT);
+ clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);
+ /* disable parity error check in DEU (erroneous? test vect.) */
+ setbits32(priv->reg_deu + TALITOS_EUICR, TALITOS1_DEUICR_KPE);
+}
+
+static void sec2_configure_device(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ setbits32(priv->reg + TALITOS_IMR, TALITOS2_IMR_INIT);
+ setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT);
+
+ /* disable integrity check error interrupts (use writeback instead) */
+ if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
+ setbits32(priv->reg_mdeu + TALITOS_EUICR_LO,
+ TALITOS_MDEUICR_LO_ICE);
+}
+
/*
* Reset and initialize the device
*/
@@ -217,80 +266,81 @@ static int init_device(struct device *dev)
* are not fully cleared by writing the MCR:SWR bit,
* set bit twice to completely reset
*/
- err = reset_device(dev);
+ if (is_sec1)
+ err = sec1_reset_device(dev);
+ else
+ err = sec2_reset_device(dev);
+
if (err)
return err;
- err = reset_device(dev);
+ if (is_sec1)
+ err = sec1_reset_device(dev);
+ else
+ err = sec2_reset_device(dev);
if (err)
return err;
/* reset channels */
for (ch = 0; ch < priv->num_channels; ch++) {
- err = reset_channel(dev, ch);
+ if (is_sec1)
+ err = sec1_reset_channel(dev, ch);
+ else
+ err = sec2_reset_channel(dev, ch);
if (err)
return err;
}
- /* enable channel done and error interrupts */
- if (is_sec1) {
- clrbits32(priv->reg + TALITOS_IMR, TALITOS1_IMR_INIT);
- clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);
- /* disable parity error check in DEU (erroneous? test vect.) */
- setbits32(priv->reg_deu + TALITOS_EUICR, TALITOS1_DEUICR_KPE);
- } else {
- setbits32(priv->reg + TALITOS_IMR, TALITOS2_IMR_INIT);
- setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT);
- }
-
- /* disable integrity check error interrupts (use writeback instead) */
- if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
- setbits32(priv->reg_mdeu + TALITOS_EUICR_LO,
- TALITOS_MDEUICR_LO_ICE);
+ if (is_sec1)
+ sec1_configure_device(dev);
+ else
+ sec2_configure_device(dev);
return 0;
}
-static void dma_map_request(struct device *dev, struct talitos_request *request,
- struct talitos_desc *desc, bool is_sec1)
+static void sec1_dma_map_request(struct device *dev,
+ struct talitos_request *request,
+ struct talitos_desc *desc)
{
struct talitos_edesc *edesc =
container_of(desc, struct talitos_edesc, desc);
dma_addr_t dma_desc, prev_dma_desc;
struct talitos_edesc *prev_edesc = NULL;
- if (is_sec1) {
- while (edesc) {
- edesc->desc.hdr1 = edesc->desc.hdr;
+ while (edesc) {
+ edesc->desc.hdr1 = edesc->desc.hdr;
- dma_desc = dma_map_single(dev, &edesc->desc.hdr1,
- TALITOS_DESC_SIZE,
- DMA_BIDIRECTIONAL);
+ dma_desc = dma_map_single(dev, &edesc->desc.hdr1,
+ TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
- if (!prev_edesc) {
- request->dma_desc = dma_desc;
- goto next;
- }
+ if (!prev_edesc) {
+ request->dma_desc = dma_desc;
+ goto next;
+ }
- /* Chain in any previous descriptors. */
+ /* Chain in any previous descriptors. */
- prev_edesc->desc.next_desc = cpu_to_be32(dma_desc);
+ prev_edesc->desc.next_desc = cpu_to_be32(dma_desc);
- dma_sync_single_for_device(dev, prev_dma_desc,
- TALITOS_DESC_SIZE,
- DMA_TO_DEVICE);
+ dma_sync_single_for_device(dev, prev_dma_desc,
+ TALITOS_DESC_SIZE, DMA_TO_DEVICE);
next:
- prev_edesc = edesc;
- prev_dma_desc = dma_desc;
- edesc = edesc->next_desc;
- }
- } else {
- request->dma_desc = dma_map_single(dev, desc, TALITOS_DESC_SIZE,
- DMA_BIDIRECTIONAL);
+ prev_edesc = edesc;
+ prev_dma_desc = dma_desc;
+ edesc = edesc->next_desc;
}
}
+static void sec2_dma_map_request(struct device *dev,
+ struct talitos_request *request,
+ struct talitos_desc *desc)
+{
+ request->dma_desc =
+ dma_map_single(dev, desc, TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
+}
+
/**
* talitos_submit - submits a descriptor to the device for processing
* @dev: the SEC device to be used
@@ -327,7 +377,10 @@ int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
request = &priv->chan[ch].fifo[head];
/* map descriptor and save caller data */
- dma_map_request(dev, request, desc, is_sec1);
+ if (is_sec1)
+ sec1_dma_map_request(dev, request, desc);
+ else
+ sec2_dma_map_request(dev, request, desc);
request->callback = callback;
request->context = context;
@@ -349,19 +402,12 @@ int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
return -EINPROGRESS;
}
-static __be32 get_request_hdr(struct device *dev,
- struct talitos_request *request, bool is_sec1)
+static __be32 sec1_get_request_hdr(struct device *dev,
+ struct talitos_request *request)
{
struct talitos_edesc *edesc;
dma_addr_t dma_desc;
- if (!is_sec1) {
- dma_sync_single_for_cpu(dev, request->dma_desc,
- TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
-
- return request->desc->hdr;
- }
-
edesc = container_of(request->desc, struct talitos_edesc, desc);
dma_desc = request->dma_desc;
while (edesc->next_desc) {
@@ -375,27 +421,37 @@ static __be32 get_request_hdr(struct device *dev,
return edesc->desc.hdr1;
}
-static void dma_unmap_request(struct device *dev,
- struct talitos_request *request, bool is_sec1)
+static __be32 sec2_get_request_hdr(struct device *dev,
+ struct talitos_request *request)
+{
+ dma_sync_single_for_cpu(dev, request->dma_desc, TALITOS_DESC_SIZE,
+ DMA_BIDIRECTIONAL);
+
+ return request->desc->hdr;
+}
+
+static void sec1_dma_unmap_request(struct device *dev,
+ struct talitos_request *request)
{
struct talitos_edesc *edesc;
- if (is_sec1) {
- dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
- DMA_BIDIRECTIONAL);
- edesc = container_of(request->desc, struct talitos_edesc, desc);
- while (edesc->next_desc) {
- dma_unmap_single(dev,
- be32_to_cpu(edesc->desc.next_desc),
- TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
- edesc = edesc->next_desc;
- }
- } else {
- dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
- DMA_BIDIRECTIONAL);
+ dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
+ DMA_BIDIRECTIONAL);
+ edesc = container_of(request->desc, struct talitos_edesc, desc);
+ while (edesc->next_desc) {
+ dma_unmap_single(dev, be32_to_cpu(edesc->desc.next_desc),
+ TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
+ edesc = edesc->next_desc;
}
}
+static void sec2_dma_unmap_request(struct device *dev,
+ struct talitos_request *request)
+{
+ dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
+ DMA_BIDIRECTIONAL);
+}
+
/*
* process what was done, notify callback of error if not
*/
@@ -417,7 +473,10 @@ static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
/* descriptors with their done bits set don't get the error */
rmb();
- hdr = get_request_hdr(dev, request, is_sec1);
+ if (is_sec1)
+ hdr = sec1_get_request_hdr(dev, request);
+ else
+ hdr = sec2_get_request_hdr(dev, request);
if ((hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
status = 0;
@@ -427,7 +486,10 @@ static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
else
status = error;
- dma_unmap_request(dev, request, is_sec1);
+ if (is_sec1)
+ sec1_dma_unmap_request(dev, request);
+ else
+ sec2_dma_unmap_request(dev, request);
/* copy entries so we can call callback outside lock */
saved_req.desc = request->desc;
@@ -516,21 +578,30 @@ DEF_TALITOS2_DONE(ch0, TALITOS2_ISR_CH_0_DONE)
DEF_TALITOS2_DONE(ch0_2, TALITOS2_ISR_CH_0_2_DONE)
DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE)
-static __be32 search_desc_hdr_in_request(struct talitos_request *request,
- dma_addr_t cur_desc, bool is_sec1)
+static __be32 sec1_search_desc_hdr_in_request(struct talitos_request *request,
+ dma_addr_t cur_desc)
{
struct talitos_edesc *edesc;
- if (request->dma_desc == cur_desc) {
+
+ if (request->dma_desc == cur_desc)
return request->desc->hdr;
- } else if (is_sec1) {
- edesc = container_of(request->desc, struct talitos_edesc, desc);
- while (edesc->next_desc) {
- if (edesc->desc.next_desc == cpu_to_be32(cur_desc))
- return edesc->next_desc->desc.hdr1;
- edesc = edesc->next_desc;
- }
+
+ edesc = container_of(request->desc, struct talitos_edesc, desc);
+ while (edesc->next_desc) {
+ if (edesc->desc.next_desc == cpu_to_be32(cur_desc))
+ return edesc->next_desc->desc.hdr1;
+ edesc = edesc->next_desc;
}
+
+ return 0;
+}
+
+static __be32 sec2_search_desc_hdr_in_request(struct talitos_request *request,
+ dma_addr_t cur_desc)
+{
+ if (request->dma_desc == cur_desc)
+ return request->desc->hdr;
return 0;
}
@@ -559,7 +630,10 @@ static __be32 current_desc_hdr(struct device *dev, int ch)
do {
request = &priv->chan[ch].fifo[iter];
- hdr = search_desc_hdr_in_request(request, cur_desc, is_sec1);
+ if (is_sec1)
+ hdr = sec1_search_desc_hdr_in_request(request, cur_desc);
+ else
+ hdr = sec2_search_desc_hdr_in_request(request, cur_desc);
if (hdr)
break;
@@ -647,79 +721,100 @@ static void report_eu_error(struct device *dev, int ch, __be32 desc_hdr)
in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
}
-/*
- * recover from error interrupts
- */
-static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
+static int sec1_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ int ch, error;
+ u32 v_lo;
+
+ for (ch = 0; ch < priv->num_channels; ch++) {
+ if (!TALITOS1_CH_HAS_ERROR(isr, ch))
+ continue;
+
+ v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
+
+ error = -EINVAL;
+
+ if (v_lo & TALITOS1_CCPSR_LO_TEA)
+ dev_err(dev, "transfer error acknowledge\n");
+ if (v_lo & TALITOS1_CCPSR_LO_PTRNC)
+ dev_err(dev, "pointer not complete error\n");
+ if (v_lo & TALITOS1_CCPSR_LO_PE)
+ dev_err(dev, "parity error\n");
+ if (v_lo & TALITOS1_CCPSR_LO_IDH)
+ dev_err(dev, "illegal descriptor header error\n");
+ if (v_lo & TALITOS1_CCPSR_LO_SA)
+ dev_err(dev, "static assignment error\n");
+ if (v_lo & TALITOS1_CCPSR_LO_EU)
+ report_eu_error(dev, ch, current_desc_hdr(dev, ch));
+
+ flush_channel(dev, ch, error, 1);
+ priv->ops->reset_channel(dev, ch);
+ }
+
+ if (isr_lo & TALITOS1_ISR_TEA_ERR)
+ dev_err(dev, "TEA error: ISR 0x%08x_%08x\n", isr, isr_lo);
+
+ return (isr & ~TALITOS1_ISR_4CHERR) || isr_lo;
+}
+
+static int sec2_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
{
struct talitos_private *priv = dev_get_drvdata(dev);
unsigned int timeout = TALITOS_TIMEOUT;
int ch, error, reset_dev = 0;
u32 v_lo;
- bool is_sec1 = has_ftr_sec1(priv);
- int reset_ch = is_sec1 ? 1 : 0; /* only SEC2 supports continuation */
+ int reset_ch = 0;
for (ch = 0; ch < priv->num_channels; ch++) {
- /* skip channels without errors */
- if (is_sec1) {
- /* bits 29, 31, 17, 19 */
- if (!(isr & (1 << (29 + (ch & 1) * 2 - (ch & 2) * 6))))
- continue;
- } else {
- if (!(isr & (1 << (ch * 2 + 1))))
- continue;
- }
+ if (!TALITOS2_CH_HAS_ERROR(isr, ch))
+ continue;
error = -EINVAL;
v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
- if (v_lo & TALITOS_CCPSR_LO_DOF) {
+ if (v_lo & TALITOS2_CCPSR_LO_DOF) {
dev_err(dev, "double fetch fifo overflow error\n");
error = -EAGAIN;
reset_ch = 1;
}
- if (v_lo & TALITOS_CCPSR_LO_SOF) {
+ if (v_lo & TALITOS2_CCPSR_LO_SOF) {
/* h/w dropped descriptor */
dev_err(dev, "single fetch fifo overflow error\n");
error = -EAGAIN;
}
- if (v_lo & TALITOS_CCPSR_LO_MDTE)
+ if (v_lo & TALITOS2_CCPSR_LO_MDTE)
dev_err(dev, "master data transfer error\n");
- if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
- dev_err(dev, is_sec1 ? "pointer not complete error\n"
- : "s/g data length zero error\n");
- if (v_lo & TALITOS_CCPSR_LO_FPZ)
- dev_err(dev, is_sec1 ? "parity error\n"
- : "fetch pointer zero error\n");
- if (v_lo & TALITOS_CCPSR_LO_IDH)
+ if (v_lo & TALITOS2_CCPSR_LO_SGDLZ)
+ dev_err(dev, "s/g data length zero error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_FPZ)
+ dev_err(dev, "fetch pointer zero error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_IDH)
dev_err(dev, "illegal descriptor header error\n");
- if (v_lo & TALITOS_CCPSR_LO_IEU)
- dev_err(dev, is_sec1 ? "static assignment error\n"
- : "invalid exec unit error\n");
- if (v_lo & TALITOS_CCPSR_LO_EU)
+ if (v_lo & TALITOS2_CCPSR_LO_IEU)
+ dev_err(dev, "invalid exec unit error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_EU)
report_eu_error(dev, ch, current_desc_hdr(dev, ch));
- if (!is_sec1) {
- if (v_lo & TALITOS_CCPSR_LO_GB)
- dev_err(dev, "gather boundary error\n");
- if (v_lo & TALITOS_CCPSR_LO_GRL)
- dev_err(dev, "gather return/length error\n");
- if (v_lo & TALITOS_CCPSR_LO_SB)
- dev_err(dev, "scatter boundary error\n");
- if (v_lo & TALITOS_CCPSR_LO_SRL)
- dev_err(dev, "scatter return/length error\n");
- }
+ if (v_lo & TALITOS2_CCPSR_LO_GB)
+ dev_err(dev, "gather boundary error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_GRL)
+ dev_err(dev, "gather return/length error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_SB)
+ dev_err(dev, "scatter boundary error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_SRL)
+ dev_err(dev, "scatter return/length error\n");
flush_channel(dev, ch, error, reset_ch);
if (reset_ch) {
- reset_channel(dev, ch);
+ priv->ops->reset_channel(dev, ch);
} else {
setbits32(priv->chan[ch].reg + TALITOS_CCCR,
TALITOS2_CCCR_CONT);
setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
- TALITOS2_CCCR_CONT) && --timeout)
+ TALITOS2_CCCR_CONT) && --timeout)
cpu_relax();
if (timeout == 0) {
dev_err(dev, "failed to restart channel %d\n",
@@ -728,14 +823,29 @@ static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
}
}
}
- if (reset_dev || (is_sec1 && isr & ~TALITOS1_ISR_4CHERR) ||
- (!is_sec1 && isr & ~TALITOS2_ISR_4CHERR) || isr_lo) {
- if (is_sec1 && (isr_lo & TALITOS1_ISR_TEA_ERR))
- dev_err(dev, "TEA error: ISR 0x%08x_%08x\n",
- isr, isr_lo);
- else
- dev_err(dev, "done overflow, internal time out, or "
- "rngu error: ISR 0x%08x_%08x\n", isr, isr_lo);
+
+ return reset_dev || (isr & ~TALITOS2_ISR_4CHERR) || isr_lo;
+}
+
+/*
+ * recover from error interrupts
+ */
+static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+ int ch, reset_dev;
+
+ if (is_sec1)
+ reset_dev = sec1_talitos_handle_error(dev, isr, isr_lo);
+ else
+ reset_dev = sec2_talitos_handle_error(dev, isr, isr_lo);
+
+ if (reset_dev) {
+ dev_err(dev,
+ "done overflow, internal time out, or "
+ "rngu error: ISR 0x%08x_%08x\n",
+ isr, isr_lo);
/* purge request queues */
for (ch = 0; ch < priv->num_channels; ch++)
@@ -1181,25 +1291,41 @@ int talitos_register_common(struct device *dev,
return 0;
}
-static int talitos_probe_irq(struct platform_device *ofdev)
+static int sec1_talitos_probe_irq(struct platform_device *ofdev)
{
struct device *dev = &ofdev->dev;
struct device_node *np = ofdev->dev.of_node;
struct talitos_private *priv = dev_get_drvdata(dev);
int err;
- bool is_sec1 = has_ftr_sec1(priv);
priv->irq[0] = irq_of_parse_and_map(np, 0);
if (!priv->irq[0]) {
dev_err(dev, "failed to map irq\n");
return -EINVAL;
}
- if (is_sec1) {
- err = request_irq(priv->irq[0], talitos1_interrupt_4ch, 0,
- dev_driver_string(dev), dev);
- goto primary_out;
+ err = request_irq(priv->irq[0], talitos1_interrupt_4ch, 0,
+ dev_driver_string(dev), dev);
+ if (err) {
+ dev_err(dev, "failed to request primary irq\n");
+ irq_dispose_mapping(priv->irq[0]);
+ priv->irq[0] = 0;
}
+ return err;
+}
+
+static int sec2_talitos_probe_irq(struct platform_device *ofdev)
+{
+ struct device *dev = &ofdev->dev;
+ struct device_node *np = ofdev->dev.of_node;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ int err;
+
+ priv->irq[0] = irq_of_parse_and_map(np, 0);
+ if (!priv->irq[0]) {
+ dev_err(dev, "failed to map irq\n");
+ return -EINVAL;
+ }
priv->irq[1] = irq_of_parse_and_map(np, 1);
/* get the primary irq line */
@@ -1235,6 +1361,36 @@ static int talitos_probe_irq(struct platform_device *ofdev)
return err;
}
+static void sec1_init_task(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ if (priv->num_channels == 1)
+ tasklet_init(&priv->done_task[0], talitos1_done_ch0,
+ (unsigned long)dev);
+ else
+ tasklet_init(&priv->done_task[0], talitos1_done_4ch,
+ (unsigned long)dev);
+}
+
+static void sec2_init_task(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ if (priv->irq[1]) {
+ tasklet_init(&priv->done_task[0], talitos2_done_ch0_2,
+ (unsigned long)dev);
+ tasklet_init(&priv->done_task[1], talitos2_done_ch1_3,
+ (unsigned long)dev);
+ } else if (priv->num_channels == 1) {
+ tasklet_init(&priv->done_task[0], talitos2_done_ch0,
+ (unsigned long)dev);
+ } else {
+ tasklet_init(&priv->done_task[0], talitos2_done_4ch,
+ (unsigned long)dev);
+ }
+}
+
static int talitos_probe(struct platform_device *ofdev)
{
struct device *dev = &ofdev->dev;
@@ -1317,31 +1473,17 @@ static int talitos_probe(struct platform_device *ofdev)
stride = TALITOS2_CH_STRIDE;
}
- err = talitos_probe_irq(ofdev);
+ if (has_ftr_sec1(priv))
+ err = sec1_talitos_probe_irq(ofdev);
+ else
+ err = sec2_talitos_probe_irq(ofdev);
if (err)
goto err_out;
- if (has_ftr_sec1(priv)) {
- if (priv->num_channels == 1)
- tasklet_init(&priv->done_task[0], talitos1_done_ch0,
- (unsigned long)dev);
- else
- tasklet_init(&priv->done_task[0], talitos1_done_4ch,
- (unsigned long)dev);
- } else {
- if (priv->irq[1]) {
- tasklet_init(&priv->done_task[0], talitos2_done_ch0_2,
- (unsigned long)dev);
- tasklet_init(&priv->done_task[1], talitos2_done_ch1_3,
- (unsigned long)dev);
- } else if (priv->num_channels == 1) {
- tasklet_init(&priv->done_task[0], talitos2_done_ch0,
- (unsigned long)dev);
- } else {
- tasklet_init(&priv->done_task[0], talitos2_done_4ch,
- (unsigned long)dev);
- }
- }
+ if (has_ftr_sec1(priv))
+ sec1_init_task(dev);
+ else
+ sec2_init_task(dev);
priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 6cf3628c52c2..904fdc9dec80 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -301,20 +301,32 @@ static inline bool has_ftr_sec1(struct talitos_private *priv)
#define TALITOS1_CCCR_LO_RESET 0x1 /* channel reset on SEC1 */
/* CCPSR: channel pointer status register */
+
+/* bits 29, 31, 17, 19 */
+#define TALITOS1_CH_HAS_ERROR(isr, ch) \
+ ((isr) & (1 << (29 + ((ch) & 1) * 2 - ((ch) & 2) * 6)))
+#define TALITOS2_CH_HAS_ERROR(isr, ch) ((isr) & (1 << ((ch) * 2 + 1)))
+
#define TALITOS_CCPSR 0x10
#define TALITOS_CCPSR_LO 0x14
-#define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
-#define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
-#define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
-#define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
-#define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
-#define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
-#define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
-#define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
-#define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
-#define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
-#define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
-#define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
+#define TALITOS1_CCPSR_LO_TEA 0x2000 /* transfer error acknowledge */
+#define TALITOS1_CCPSR_LO_PTRNC 0x1000 /* pointer not complete error */
+#define TALITOS1_CCPSR_LO_PE 0x0800 /* parity error */
+#define TALITOS1_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
+#define TALITOS1_CCPSR_LO_SA 0x0200 /* static assignment error */
+#define TALITOS1_CCPSR_LO_EU 0x0100 /* EU error detected */
+#define TALITOS2_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
+#define TALITOS2_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
+#define TALITOS2_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
+#define TALITOS2_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
+#define TALITOS2_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
+#define TALITOS2_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
+#define TALITOS2_CCPSR_LO_IEU 0x0200 /* invalid EU error */
+#define TALITOS2_CCPSR_LO_EU 0x0100 /* EU error detected */
+#define TALITOS2_CCPSR_LO_GB 0x0080 /* gather boundary error */
+#define TALITOS2_CCPSR_LO_GRL 0x0040 /* gather return/length error */
+#define TALITOS2_CCPSR_LO_SB 0x0020 /* scatter boundary error */
+#define TALITOS2_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
/* channel fetch fifo register */
#define TALITOS_FF 0x48
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 19/29] crypto: talitos - Introduce struct talitos_ops
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (17 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 18/29] crypto: talitos - Split SEC1/SEC2 code into separate function variants Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 20/29] crypto: talitos - Replace SEC1/SEC2 conditionals with ops dispatch Paul Louvel
` (9 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Add struct talitos_ops containing function pointers for IRQ probing,
tasklet initialization, device and channel reset, device configuration,
descriptor DMA mapping, request header retrieval and error handling.
Add an ops pointer to struct talitos_private. The ops pointer will be
initialized at probe time based on the detected hardware and used to
dispatch SEC1/SEC2-specific behaviour.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 904fdc9dec80..46de1bf1ef27 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -14,6 +14,7 @@
#include <linux/dma-mapping.h>
#include <linux/hw_random.h>
#include <linux/interrupt.h>
+#include <linux/platform_device.h>
#include <linux/scatterlist.h>
#include <linux/types.h>
@@ -139,6 +140,25 @@ struct talitos_channel {
int tail;
};
+struct talitos_ops {
+ int (*probe_irq)(struct platform_device *ofdev);
+ void (*init_task)(struct device *dev);
+ int (*reset_device)(struct device *dev);
+ int (*reset_channel)(struct device *dev, int ch);
+ void (*configure_device)(struct device *dev);
+
+ void (*dma_map_request)(struct device *dev,
+ struct talitos_request *request,
+ struct talitos_desc *desc);
+ void (*dma_unmap_request)(struct device *dev,
+ struct talitos_request *request);
+ __be32 (*get_request_hdr)(struct device *dev,
+ struct talitos_request *request);
+ __be32 (*search_desc_hdr_in_request)(struct talitos_request *request,
+ dma_addr_t cpdr);
+ int (*handle_error)(struct device *dev, u32 isr, u32 isr_lo);
+};
+
struct talitos_private {
struct device *dev;
struct platform_device *ofdev;
@@ -162,6 +182,8 @@ struct talitos_private {
unsigned int exec_units;
unsigned int desc_types;
+ const struct talitos_ops *ops;
+
/* SEC Compatibility info */
unsigned long features;
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 20/29] crypto: talitos - Replace SEC1/SEC2 conditionals with ops dispatch
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (18 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 19/29] crypto: talitos - Introduce struct talitos_ops Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 21/29] crypto: talitos - Export common channel and error handling routines Paul Louvel
` (8 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Replace the if/else is_sec1 dispatches in callers with indirect calls
through priv->ops. Add static const sec1_ops and sec2_ops structs
populated with the SEC1 and SEC2 function variants, and set priv->ops
at probe time based on the detected hardware.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 88 +++++++++++++++++++---------------------
1 file changed, 41 insertions(+), 47 deletions(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index b6793d97735e..c4a311a8e7fd 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -258,7 +258,6 @@ static int init_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
int ch, err;
- bool is_sec1 = has_ftr_sec1(priv);
/*
* Master reset
@@ -266,35 +265,23 @@ static int init_device(struct device *dev)
* are not fully cleared by writing the MCR:SWR bit,
* set bit twice to completely reset
*/
- if (is_sec1)
- err = sec1_reset_device(dev);
- else
- err = sec2_reset_device(dev);
+ err = priv->ops->reset_device(dev);
if (err)
return err;
- if (is_sec1)
- err = sec1_reset_device(dev);
- else
- err = sec2_reset_device(dev);
+ err = priv->ops->reset_device(dev);
if (err)
return err;
/* reset channels */
for (ch = 0; ch < priv->num_channels; ch++) {
- if (is_sec1)
- err = sec1_reset_channel(dev, ch);
- else
- err = sec2_reset_channel(dev, ch);
+ err = priv->ops->reset_channel(dev, ch);
if (err)
return err;
}
- if (is_sec1)
- sec1_configure_device(dev);
- else
- sec2_configure_device(dev);
+ priv->ops->configure_device(dev);
return 0;
}
@@ -363,7 +350,6 @@ int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
struct talitos_request *request;
unsigned long flags;
int head;
- bool is_sec1 = has_ftr_sec1(priv);
spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
@@ -377,10 +363,8 @@ int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
request = &priv->chan[ch].fifo[head];
/* map descriptor and save caller data */
- if (is_sec1)
- sec1_dma_map_request(dev, request, desc);
- else
- sec2_dma_map_request(dev, request, desc);
+ priv->ops->dma_map_request(dev, request, desc);
+
request->callback = callback;
request->context = context;
@@ -461,7 +445,6 @@ static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
struct talitos_request *request, saved_req;
unsigned long flags;
int tail, status;
- bool is_sec1 = has_ftr_sec1(priv);
spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
@@ -473,10 +456,7 @@ static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
/* descriptors with their done bits set don't get the error */
rmb();
- if (is_sec1)
- hdr = sec1_get_request_hdr(dev, request);
- else
- hdr = sec2_get_request_hdr(dev, request);
+ hdr = priv->ops->get_request_hdr(dev, request);
if ((hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
status = 0;
@@ -486,10 +466,7 @@ static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
else
status = error;
- if (is_sec1)
- sec1_dma_unmap_request(dev, request);
- else
- sec2_dma_unmap_request(dev, request);
+ priv->ops->dma_unmap_request(dev, request);
/* copy entries so we can call callback outside lock */
saved_req.desc = request->desc;
@@ -611,7 +588,6 @@ static __be32 sec2_search_desc_hdr_in_request(struct talitos_request *request,
static __be32 current_desc_hdr(struct device *dev, int ch)
{
struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
struct talitos_request *request;
int tail, iter;
dma_addr_t cur_desc;
@@ -630,10 +606,7 @@ static __be32 current_desc_hdr(struct device *dev, int ch)
do {
request = &priv->chan[ch].fifo[iter];
- if (is_sec1)
- hdr = sec1_search_desc_hdr_in_request(request, cur_desc);
- else
- hdr = sec2_search_desc_hdr_in_request(request, cur_desc);
+ hdr = priv->ops->search_desc_hdr_in_request(request, cur_desc);
if (hdr)
break;
@@ -833,13 +806,9 @@ static int sec2_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
{
struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
int ch, reset_dev;
- if (is_sec1)
- reset_dev = sec1_talitos_handle_error(dev, isr, isr_lo);
- else
- reset_dev = sec2_talitos_handle_error(dev, isr, isr_lo);
+ reset_dev = priv->ops->handle_error(dev, isr, isr_lo);
if (reset_dev) {
dev_err(dev,
@@ -1391,6 +1360,32 @@ static void sec2_init_task(struct device *dev)
}
}
+static const struct talitos_ops sec1_ops = {
+ .probe_irq = sec1_talitos_probe_irq,
+ .init_task = sec1_init_task,
+ .reset_device = sec1_reset_device,
+ .reset_channel = sec1_reset_channel,
+ .configure_device = sec1_configure_device,
+ .dma_map_request = sec1_dma_map_request,
+ .dma_unmap_request = sec1_dma_unmap_request,
+ .get_request_hdr = sec1_get_request_hdr,
+ .search_desc_hdr_in_request = sec1_search_desc_hdr_in_request,
+ .handle_error = sec1_talitos_handle_error,
+};
+
+static const struct talitos_ops sec2_ops = {
+ .probe_irq = sec2_talitos_probe_irq,
+ .init_task = sec2_init_task,
+ .reset_device = sec2_reset_device,
+ .reset_channel = sec2_reset_channel,
+ .configure_device = sec2_configure_device,
+ .dma_map_request = sec2_dma_map_request,
+ .dma_unmap_request = sec2_dma_unmap_request,
+ .get_request_hdr = sec2_get_request_hdr,
+ .search_desc_hdr_in_request = sec2_search_desc_hdr_in_request,
+ .handle_error = sec2_talitos_handle_error,
+};
+
static int talitos_probe(struct platform_device *ofdev)
{
struct device *dev = &ofdev->dev;
@@ -1474,16 +1469,15 @@ static int talitos_probe(struct platform_device *ofdev)
}
if (has_ftr_sec1(priv))
- err = sec1_talitos_probe_irq(ofdev);
+ priv->ops = &sec1_ops;
else
- err = sec2_talitos_probe_irq(ofdev);
+ priv->ops = &sec2_ops;
+
+ err = priv->ops->probe_irq(ofdev);
if (err)
goto err_out;
- if (has_ftr_sec1(priv))
- sec1_init_task(dev);
- else
- sec2_init_task(dev);
+ priv->ops->init_task(dev);
priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 21/29] crypto: talitos - Export common channel and error handling routines
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (19 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 20/29] crypto: talitos - Replace SEC1/SEC2 conditionals with ops dispatch Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 22/29] crypto: talitos - Move SEC1 ops into talitos-sec1.c Paul Louvel
` (7 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Remove the static qualifier from flush_channel(), current_desc_hdr(),
report_eu_error(), and talitos_error(); add the talitos_ prefix where
missing; and declare them in talitos.h.
These routines will be called from the upcoming SEC1/SEC2 compilation
units, so they need to be externally visible.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 36 +++++++++++++++++++-----------------
drivers/crypto/talitos/talitos.h | 5 +++++
2 files changed, 24 insertions(+), 17 deletions(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index c4a311a8e7fd..827d075ecfaa 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -439,7 +439,7 @@ static void sec2_dma_unmap_request(struct device *dev,
/*
* process what was done, notify callback of error if not
*/
-static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
+void talitos_flush_channel(struct device *dev, int ch, int error, int reset_ch)
{
struct talitos_private *priv = dev_get_drvdata(dev);
struct talitos_request *request, saved_req;
@@ -507,13 +507,13 @@ static void talitos1_done_##name(unsigned long data) \
unsigned long flags; \
\
if (ch_done_mask & 0x10000000) \
- flush_channel(dev, 0, 0, 0); \
+ talitos_flush_channel(dev, 0, 0, 0); \
if (ch_done_mask & 0x40000000) \
- flush_channel(dev, 1, 0, 0); \
+ talitos_flush_channel(dev, 1, 0, 0); \
if (ch_done_mask & 0x00010000) \
- flush_channel(dev, 2, 0, 0); \
+ talitos_flush_channel(dev, 2, 0, 0); \
if (ch_done_mask & 0x00040000) \
- flush_channel(dev, 3, 0, 0); \
+ talitos_flush_channel(dev, 3, 0, 0); \
\
/* At this point, all completed channels have been processed */ \
/* Unmask done interrupts for channels completed later on. */ \
@@ -534,13 +534,13 @@ static void talitos2_done_##name(unsigned long data) \
unsigned long flags; \
\
if (ch_done_mask & 1) \
- flush_channel(dev, 0, 0, 0); \
+ talitos_flush_channel(dev, 0, 0, 0); \
if (ch_done_mask & (1 << 2)) \
- flush_channel(dev, 1, 0, 0); \
+ talitos_flush_channel(dev, 1, 0, 0); \
if (ch_done_mask & (1 << 4)) \
- flush_channel(dev, 2, 0, 0); \
+ talitos_flush_channel(dev, 2, 0, 0); \
if (ch_done_mask & (1 << 6)) \
- flush_channel(dev, 3, 0, 0); \
+ talitos_flush_channel(dev, 3, 0, 0); \
\
/* At this point, all completed channels have been processed */ \
/* Unmask done interrupts for channels completed later on. */ \
@@ -585,7 +585,7 @@ static __be32 sec2_search_desc_hdr_in_request(struct talitos_request *request,
/*
* locate current (offending) descriptor
*/
-static __be32 current_desc_hdr(struct device *dev, int ch)
+__be32 talitos_current_desc_hdr(struct device *dev, int ch)
{
struct talitos_private *priv = dev_get_drvdata(dev);
struct talitos_request *request;
@@ -622,7 +622,7 @@ static __be32 current_desc_hdr(struct device *dev, int ch)
/*
* user diagnostics; report root cause of error based on execution unit status
*/
-static void report_eu_error(struct device *dev, int ch, __be32 desc_hdr)
+void talitos_report_eu_error(struct device *dev, int ch, __be32 desc_hdr)
{
struct talitos_private *priv = dev_get_drvdata(dev);
int i;
@@ -719,9 +719,10 @@ static int sec1_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
if (v_lo & TALITOS1_CCPSR_LO_SA)
dev_err(dev, "static assignment error\n");
if (v_lo & TALITOS1_CCPSR_LO_EU)
- report_eu_error(dev, ch, current_desc_hdr(dev, ch));
+ talitos_report_eu_error(
+ dev, ch, talitos_current_desc_hdr(dev, ch));
- flush_channel(dev, ch, error, 1);
+ talitos_flush_channel(dev, ch, error, 1);
priv->ops->reset_channel(dev, ch);
}
@@ -768,7 +769,8 @@ static int sec2_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
if (v_lo & TALITOS2_CCPSR_LO_IEU)
dev_err(dev, "invalid exec unit error\n");
if (v_lo & TALITOS2_CCPSR_LO_EU)
- report_eu_error(dev, ch, current_desc_hdr(dev, ch));
+ talitos_report_eu_error(
+ dev, ch, talitos_current_desc_hdr(dev, ch));
if (v_lo & TALITOS2_CCPSR_LO_GB)
dev_err(dev, "gather boundary error\n");
if (v_lo & TALITOS2_CCPSR_LO_GRL)
@@ -778,7 +780,7 @@ static int sec2_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
if (v_lo & TALITOS2_CCPSR_LO_SRL)
dev_err(dev, "scatter return/length error\n");
- flush_channel(dev, ch, error, reset_ch);
+ talitos_flush_channel(dev, ch, error, reset_ch);
if (reset_ch) {
priv->ops->reset_channel(dev, ch);
@@ -803,7 +805,7 @@ static int sec2_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
/*
* recover from error interrupts
*/
-static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
+void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
{
struct talitos_private *priv = dev_get_drvdata(dev);
int ch, reset_dev;
@@ -818,7 +820,7 @@ static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
/* purge request queues */
for (ch = 0; ch < priv->num_channels; ch++)
- flush_channel(dev, ch, -EIO, 1);
+ talitos_flush_channel(dev, ch, -EIO, 1);
/* reset and reinitialize the device */
init_device(dev);
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 46de1bf1ef27..98b2cb5115f8 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -561,6 +561,11 @@ void talitos_cra_exit(struct crypto_tfm *tfm);
int talitos_register_common(struct device *dev,
struct talitos_alg_template *template);
+void talitos_flush_channel(struct device *dev, int ch, int error, int reset_ch);
+__be32 talitos_current_desc_hdr(struct device *dev, int ch);
+void talitos_error(struct device *dev, u32 isr, u32 isr_lo);
+void talitos_report_eu_error(struct device *dev, int ch, __be32 desc_hdr);
+
/* Hardware RNG */
int talitos_register_rng(struct device *dev);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 22/29] crypto: talitos - Move SEC1 ops into talitos-sec1.c
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (20 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 21/29] crypto: talitos - Export common channel and error handling routines Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 23/29] crypto: talitos - Move SEC2 ops into talitos-sec2.c Paul Louvel
` (6 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Relocate all SEC1-specific functions and the sec1_ops /
talitos_register_sec1() definitions from talitos.c into a new
talitos-sec1.c compilation unit.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/Makefile | 2 +
drivers/crypto/talitos/talitos-sec1.c | 305 ++++++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.c | 289 +-------------------------------
drivers/crypto/talitos/talitos.h | 8 +
4 files changed, 316 insertions(+), 288 deletions(-)
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
index 9e80bb094507..5f3bc89ad7ea 100644
--- a/drivers/crypto/talitos/Makefile
+++ b/drivers/crypto/talitos/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
talitos-y := talitos.o talitos-rng.o talitos-hash.o talitos-skcipher.o talitos-aead.o
+
+talitos-$(CONFIG_CRYPTO_DEV_TALITOS1) += talitos-sec1.o
diff --git a/drivers/crypto/talitos/talitos-sec1.c b/drivers/crypto/talitos/talitos-sec1.c
new file mode 100644
index 000000000000..695d531aa7f4
--- /dev/null
+++ b/drivers/crypto/talitos/talitos-sec1.c
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Freescale SEC (talitos) SEC1 specific driver code
+ *
+ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <linux/io.h>
+#include <linux/of_irq.h>
+
+#include "talitos.h"
+
+#define DEF_TALITOS1_DONE(name, ch_done_mask) \
+static void talitos1_done_##name(unsigned long data) \
+{ \
+ struct device *dev = (struct device *)data; \
+ struct talitos_private *priv = dev_get_drvdata(dev); \
+ unsigned long flags; \
+ \
+ if (ch_done_mask & 0x10000000) \
+ talitos_flush_channel(dev, 0, 0, 0); \
+ if (ch_done_mask & 0x40000000) \
+ talitos_flush_channel(dev, 1, 0, 0); \
+ if (ch_done_mask & 0x00010000) \
+ talitos_flush_channel(dev, 2, 0, 0); \
+ if (ch_done_mask & 0x00040000) \
+ talitos_flush_channel(dev, 3, 0, 0); \
+ \
+ /* At this point, all completed channels have been processed */ \
+ /* Unmask done interrupts for channels completed later on. */ \
+ spin_lock_irqsave(&priv->reg_lock, flags); \
+ clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
+ clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT); \
+ spin_unlock_irqrestore(&priv->reg_lock, flags); \
+}
+
+DEF_TALITOS1_DONE(4ch, TALITOS1_ISR_4CHDONE)
+DEF_TALITOS1_DONE(ch0, TALITOS1_ISR_CH_0_DONE)
+
+#define DEF_TALITOS1_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
+static irqreturn_t talitos1_interrupt_##name(int irq, void *data) \
+{ \
+ struct device *dev = data; \
+ struct talitos_private *priv = dev_get_drvdata(dev); \
+ u32 isr, isr_lo; \
+ unsigned long flags; \
+ \
+ spin_lock_irqsave(&priv->reg_lock, flags); \
+ isr = in_be32(priv->reg + TALITOS_ISR); \
+ isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
+ /* Acknowledge interrupt */ \
+ out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
+ out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
+ \
+ if (unlikely(isr & ch_err_mask || isr_lo & TALITOS1_IMR_LO_INIT)) { \
+ spin_unlock_irqrestore(&priv->reg_lock, flags); \
+ talitos_error(dev, isr & ch_err_mask, isr_lo); \
+ } \
+ else { \
+ if (likely(isr & ch_done_mask)) { \
+ /* mask further done interrupts. */ \
+ setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
+ /* done_task will unmask done interrupts at exit */ \
+ tasklet_schedule(&priv->done_task[tlet]); \
+ } \
+ spin_unlock_irqrestore(&priv->reg_lock, flags); \
+ } \
+ \
+ return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
+ IRQ_NONE; \
+}
+
+DEF_TALITOS1_INTERRUPT(4ch, TALITOS1_ISR_4CHDONE, TALITOS1_ISR_4CHERR, 0)
+
+static int sec1_reset_device(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ unsigned int timeout = TALITOS_TIMEOUT;
+
+ setbits32(priv->reg + TALITOS_MCR, TALITOS1_MCR_SWR);
+
+ while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS1_MCR_SWR) &&
+ --timeout)
+ cpu_relax();
+
+ if (timeout == 0) {
+ dev_err(dev, "failed to reset sec1 device\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int sec1_reset_channel(struct device *dev, int ch)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ unsigned int timeout = TALITOS_TIMEOUT;
+
+ setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS1_CCCR_LO_RESET);
+
+ while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR_LO) &
+ TALITOS1_CCCR_LO_RESET) &&
+ --timeout)
+ cpu_relax();
+
+ if (timeout == 0) {
+ dev_err(dev, "failed to reset sec1 channel %d\n", ch);
+ return -EIO;
+ }
+
+ setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
+ TALITOS_CCCR_LO_NE | TALITOS_CCCR_LO_CDIE |
+ TALITOS_CCCR_LO_CDWE);
+
+ return 0;
+}
+
+static void sec1_configure_device(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ clrbits32(priv->reg + TALITOS_IMR, TALITOS1_IMR_INIT);
+ clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);
+ /* disable parity error check in DEU (erroneous? test vect.) */
+ setbits32(priv->reg_deu + TALITOS_EUICR, TALITOS1_DEUICR_KPE);
+}
+
+static void sec1_dma_map_request(struct device *dev,
+ struct talitos_request *request,
+ struct talitos_desc *desc)
+{
+ struct talitos_edesc *edesc =
+ container_of(desc, struct talitos_edesc, desc);
+ dma_addr_t dma_desc, prev_dma_desc;
+ struct talitos_edesc *prev_edesc = NULL;
+
+ while (edesc) {
+ edesc->desc.hdr1 = edesc->desc.hdr;
+
+ dma_desc = dma_map_single(dev, &edesc->desc.hdr1,
+ TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
+
+ if (!prev_edesc) {
+ request->dma_desc = dma_desc;
+ goto next;
+ }
+
+ /* Chain in any previous descriptors. */
+
+ prev_edesc->desc.next_desc = cpu_to_be32(dma_desc);
+
+ dma_sync_single_for_device(dev, prev_dma_desc,
+ TALITOS_DESC_SIZE, DMA_TO_DEVICE);
+
+next:
+ prev_edesc = edesc;
+ prev_dma_desc = dma_desc;
+ edesc = edesc->next_desc;
+ }
+}
+
+static void sec1_dma_unmap_request(struct device *dev,
+ struct talitos_request *request)
+{
+ struct talitos_edesc *edesc;
+
+ dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
+ DMA_BIDIRECTIONAL);
+ edesc = container_of(request->desc, struct talitos_edesc, desc);
+ while (edesc->next_desc) {
+ dma_unmap_single(dev, be32_to_cpu(edesc->desc.next_desc),
+ TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
+ edesc = edesc->next_desc;
+ }
+}
+
+static __be32 sec1_get_request_hdr(struct device *dev,
+ struct talitos_request *request)
+{
+ struct talitos_edesc *edesc;
+ dma_addr_t dma_desc;
+
+ edesc = container_of(request->desc, struct talitos_edesc, desc);
+ dma_desc = request->dma_desc;
+ while (edesc->next_desc) {
+ dma_desc = be32_to_cpu(edesc->desc.next_desc);
+ edesc = edesc->next_desc;
+ }
+
+ dma_sync_single_for_cpu(dev, dma_desc, TALITOS_DESC_SIZE,
+ DMA_BIDIRECTIONAL);
+
+ return edesc->desc.hdr1;
+}
+
+static __be32 sec1_search_desc_hdr_in_request(struct talitos_request *request,
+ dma_addr_t cur_desc)
+{
+ struct talitos_edesc *edesc;
+
+
+ if (request->dma_desc == cur_desc)
+ return request->desc->hdr;
+
+ edesc = container_of(request->desc, struct talitos_edesc, desc);
+ while (edesc->next_desc) {
+ if (edesc->desc.next_desc == cpu_to_be32(cur_desc))
+ return edesc->next_desc->desc.hdr1;
+ edesc = edesc->next_desc;
+ }
+
+ return 0;
+}
+
+static int sec1_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ int ch, error;
+ u32 v_lo;
+
+ for (ch = 0; ch < priv->num_channels; ch++) {
+ if (!TALITOS1_CH_HAS_ERROR(isr, ch))
+ continue;
+
+ v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
+
+ error = -EINVAL;
+
+ if (v_lo & TALITOS1_CCPSR_LO_TEA)
+ dev_err(dev, "transfer error acknowledge\n");
+ if (v_lo & TALITOS1_CCPSR_LO_PTRNC)
+ dev_err(dev, "pointer not complete error\n");
+ if (v_lo & TALITOS1_CCPSR_LO_PE)
+ dev_err(dev, "parity error\n");
+ if (v_lo & TALITOS1_CCPSR_LO_IDH)
+ dev_err(dev, "illegal descriptor header error\n");
+ if (v_lo & TALITOS1_CCPSR_LO_SA)
+ dev_err(dev, "static assignment error\n");
+ if (v_lo & TALITOS1_CCPSR_LO_EU)
+ talitos_report_eu_error(
+ dev, ch, talitos_current_desc_hdr(dev, ch));
+
+ talitos_flush_channel(dev, ch, error, 1);
+ priv->ops->reset_channel(dev, ch);
+ }
+
+ if (isr_lo & TALITOS1_ISR_TEA_ERR)
+ dev_err(dev, "TEA error: ISR 0x%08x_%08x\n", isr, isr_lo);
+
+ return (isr & ~TALITOS1_ISR_4CHERR) || isr_lo;
+}
+
+static int sec1_talitos_probe_irq(struct platform_device *ofdev)
+{
+ struct device *dev = &ofdev->dev;
+ struct device_node *np = ofdev->dev.of_node;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ int err;
+
+ priv->irq[0] = irq_of_parse_and_map(np, 0);
+ if (!priv->irq[0]) {
+ dev_err(dev, "failed to map irq\n");
+ return -EINVAL;
+ }
+ err = request_irq(priv->irq[0], talitos1_interrupt_4ch, 0,
+ dev_driver_string(dev), dev);
+ if (err) {
+ dev_err(dev, "failed to request primary irq\n");
+ irq_dispose_mapping(priv->irq[0]);
+ priv->irq[0] = 0;
+ }
+
+ return err;
+}
+
+static void sec1_init_task(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ if (priv->num_channels == 1)
+ tasklet_init(&priv->done_task[0], talitos1_done_ch0,
+ (unsigned long)dev);
+ else
+ tasklet_init(&priv->done_task[0], talitos1_done_4ch,
+ (unsigned long)dev);
+}
+
+static const struct talitos_ops sec1_ops = {
+ .probe_irq = sec1_talitos_probe_irq,
+ .init_task = sec1_init_task,
+ .reset_device = sec1_reset_device,
+ .reset_channel = sec1_reset_channel,
+ .configure_device = sec1_configure_device,
+ .dma_map_request = sec1_dma_map_request,
+ .dma_unmap_request = sec1_dma_unmap_request,
+ .get_request_hdr = sec1_get_request_hdr,
+ .search_desc_hdr_in_request = sec1_search_desc_hdr_in_request,
+ .handle_error = sec1_talitos_handle_error,
+};
+
+void talitos_register_sec1(struct talitos_private *priv)
+{
+ priv->ops = &sec1_ops;
+}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 827d075ecfaa..a4fd14c8bef5 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -133,30 +133,6 @@ void unmap_single_talitos_ptr(struct device *dev,
from_talitos_ptr_len(ptr, is_sec1), dir);
}
-static int sec1_reset_channel(struct device *dev, int ch)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
- unsigned int timeout = TALITOS_TIMEOUT;
-
- setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS1_CCCR_LO_RESET);
-
- while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR_LO) &
- TALITOS1_CCCR_LO_RESET) &&
- --timeout)
- cpu_relax();
-
- if (timeout == 0) {
- dev_err(dev, "failed to reset sec1 channel %d\n", ch);
- return -EIO;
- }
-
- setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
- TALITOS_CCCR_LO_NE | TALITOS_CCCR_LO_CDIE |
- TALITOS_CCCR_LO_CDWE);
-
- return 0;
-}
-
static int sec2_reset_channel(struct device *dev, int ch)
{
struct talitos_private *priv = dev_get_drvdata(dev);
@@ -186,25 +162,6 @@ static int sec2_reset_channel(struct device *dev, int ch)
return 0;
}
-static int sec1_reset_device(struct device *dev)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
- unsigned int timeout = TALITOS_TIMEOUT;
-
- setbits32(priv->reg + TALITOS_MCR, TALITOS1_MCR_SWR);
-
- while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS1_MCR_SWR) &&
- --timeout)
- cpu_relax();
-
- if (timeout == 0) {
- dev_err(dev, "failed to reset sec1 device\n");
- return -EIO;
- }
-
- return 0;
-}
-
static int sec2_reset_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
@@ -228,16 +185,6 @@ static int sec2_reset_device(struct device *dev)
return 0;
}
-static void sec1_configure_device(struct device *dev)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
-
- clrbits32(priv->reg + TALITOS_IMR, TALITOS1_IMR_INIT);
- clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);
- /* disable parity error check in DEU (erroneous? test vect.) */
- setbits32(priv->reg_deu + TALITOS_EUICR, TALITOS1_DEUICR_KPE);
-}
-
static void sec2_configure_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
@@ -286,40 +233,6 @@ static int init_device(struct device *dev)
return 0;
}
-static void sec1_dma_map_request(struct device *dev,
- struct talitos_request *request,
- struct talitos_desc *desc)
-{
- struct talitos_edesc *edesc =
- container_of(desc, struct talitos_edesc, desc);
- dma_addr_t dma_desc, prev_dma_desc;
- struct talitos_edesc *prev_edesc = NULL;
-
- while (edesc) {
- edesc->desc.hdr1 = edesc->desc.hdr;
-
- dma_desc = dma_map_single(dev, &edesc->desc.hdr1,
- TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
-
- if (!prev_edesc) {
- request->dma_desc = dma_desc;
- goto next;
- }
-
- /* Chain in any previous descriptors. */
-
- prev_edesc->desc.next_desc = cpu_to_be32(dma_desc);
-
- dma_sync_single_for_device(dev, prev_dma_desc,
- TALITOS_DESC_SIZE, DMA_TO_DEVICE);
-
-next:
- prev_edesc = edesc;
- prev_dma_desc = dma_desc;
- edesc = edesc->next_desc;
- }
-}
-
static void sec2_dma_map_request(struct device *dev,
struct talitos_request *request,
struct talitos_desc *desc)
@@ -386,25 +299,6 @@ int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
return -EINPROGRESS;
}
-static __be32 sec1_get_request_hdr(struct device *dev,
- struct talitos_request *request)
-{
- struct talitos_edesc *edesc;
- dma_addr_t dma_desc;
-
- edesc = container_of(request->desc, struct talitos_edesc, desc);
- dma_desc = request->dma_desc;
- while (edesc->next_desc) {
- dma_desc = be32_to_cpu(edesc->desc.next_desc);
- edesc = edesc->next_desc;
- }
-
- dma_sync_single_for_cpu(dev, dma_desc, TALITOS_DESC_SIZE,
- DMA_BIDIRECTIONAL);
-
- return edesc->desc.hdr1;
-}
-
static __be32 sec2_get_request_hdr(struct device *dev,
struct talitos_request *request)
{
@@ -414,21 +308,6 @@ static __be32 sec2_get_request_hdr(struct device *dev,
return request->desc->hdr;
}
-static void sec1_dma_unmap_request(struct device *dev,
- struct talitos_request *request)
-{
- struct talitos_edesc *edesc;
-
- dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
- DMA_BIDIRECTIONAL);
- edesc = container_of(request->desc, struct talitos_edesc, desc);
- while (edesc->next_desc) {
- dma_unmap_single(dev, be32_to_cpu(edesc->desc.next_desc),
- TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
- edesc = edesc->next_desc;
- }
-}
-
static void sec2_dma_unmap_request(struct device *dev,
struct talitos_request *request)
{
@@ -499,32 +378,6 @@ void talitos_flush_channel(struct device *dev, int ch, int error, int reset_ch)
/*
* process completed requests for channels that have done status
*/
-#define DEF_TALITOS1_DONE(name, ch_done_mask) \
-static void talitos1_done_##name(unsigned long data) \
-{ \
- struct device *dev = (struct device *)data; \
- struct talitos_private *priv = dev_get_drvdata(dev); \
- unsigned long flags; \
- \
- if (ch_done_mask & 0x10000000) \
- talitos_flush_channel(dev, 0, 0, 0); \
- if (ch_done_mask & 0x40000000) \
- talitos_flush_channel(dev, 1, 0, 0); \
- if (ch_done_mask & 0x00010000) \
- talitos_flush_channel(dev, 2, 0, 0); \
- if (ch_done_mask & 0x00040000) \
- talitos_flush_channel(dev, 3, 0, 0); \
- \
- /* At this point, all completed channels have been processed */ \
- /* Unmask done interrupts for channels completed later on. */ \
- spin_lock_irqsave(&priv->reg_lock, flags); \
- clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
- clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT); \
- spin_unlock_irqrestore(&priv->reg_lock, flags); \
-}
-
-DEF_TALITOS1_DONE(4ch, TALITOS1_ISR_4CHDONE)
-DEF_TALITOS1_DONE(ch0, TALITOS1_ISR_CH_0_DONE)
#define DEF_TALITOS2_DONE(name, ch_done_mask) \
static void talitos2_done_##name(unsigned long data) \
@@ -555,25 +408,6 @@ DEF_TALITOS2_DONE(ch0, TALITOS2_ISR_CH_0_DONE)
DEF_TALITOS2_DONE(ch0_2, TALITOS2_ISR_CH_0_2_DONE)
DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE)
-static __be32 sec1_search_desc_hdr_in_request(struct talitos_request *request,
- dma_addr_t cur_desc)
-{
- struct talitos_edesc *edesc;
-
-
- if (request->dma_desc == cur_desc)
- return request->desc->hdr;
-
- edesc = container_of(request->desc, struct talitos_edesc, desc);
- while (edesc->next_desc) {
- if (edesc->desc.next_desc == cpu_to_be32(cur_desc))
- return edesc->next_desc->desc.hdr1;
- edesc = edesc->next_desc;
- }
-
- return 0;
-}
-
static __be32 sec2_search_desc_hdr_in_request(struct talitos_request *request,
dma_addr_t cur_desc)
{
@@ -694,44 +528,6 @@ void talitos_report_eu_error(struct device *dev, int ch, __be32 desc_hdr)
in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
}
-static int sec1_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
- int ch, error;
- u32 v_lo;
-
- for (ch = 0; ch < priv->num_channels; ch++) {
- if (!TALITOS1_CH_HAS_ERROR(isr, ch))
- continue;
-
- v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
-
- error = -EINVAL;
-
- if (v_lo & TALITOS1_CCPSR_LO_TEA)
- dev_err(dev, "transfer error acknowledge\n");
- if (v_lo & TALITOS1_CCPSR_LO_PTRNC)
- dev_err(dev, "pointer not complete error\n");
- if (v_lo & TALITOS1_CCPSR_LO_PE)
- dev_err(dev, "parity error\n");
- if (v_lo & TALITOS1_CCPSR_LO_IDH)
- dev_err(dev, "illegal descriptor header error\n");
- if (v_lo & TALITOS1_CCPSR_LO_SA)
- dev_err(dev, "static assignment error\n");
- if (v_lo & TALITOS1_CCPSR_LO_EU)
- talitos_report_eu_error(
- dev, ch, talitos_current_desc_hdr(dev, ch));
-
- talitos_flush_channel(dev, ch, error, 1);
- priv->ops->reset_channel(dev, ch);
- }
-
- if (isr_lo & TALITOS1_ISR_TEA_ERR)
- dev_err(dev, "TEA error: ISR 0x%08x_%08x\n", isr, isr_lo);
-
- return (isr & ~TALITOS1_ISR_4CHERR) || isr_lo;
-}
-
static int sec2_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
{
struct talitos_private *priv = dev_get_drvdata(dev);
@@ -827,41 +623,6 @@ void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
}
}
-#define DEF_TALITOS1_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
-static irqreturn_t talitos1_interrupt_##name(int irq, void *data) \
-{ \
- struct device *dev = data; \
- struct talitos_private *priv = dev_get_drvdata(dev); \
- u32 isr, isr_lo; \
- unsigned long flags; \
- \
- spin_lock_irqsave(&priv->reg_lock, flags); \
- isr = in_be32(priv->reg + TALITOS_ISR); \
- isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
- /* Acknowledge interrupt */ \
- out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
- out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
- \
- if (unlikely(isr & ch_err_mask || isr_lo & TALITOS1_IMR_LO_INIT)) { \
- spin_unlock_irqrestore(&priv->reg_lock, flags); \
- talitos_error(dev, isr & ch_err_mask, isr_lo); \
- } \
- else { \
- if (likely(isr & ch_done_mask)) { \
- /* mask further done interrupts. */ \
- setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
- /* done_task will unmask done interrupts at exit */ \
- tasklet_schedule(&priv->done_task[tlet]); \
- } \
- spin_unlock_irqrestore(&priv->reg_lock, flags); \
- } \
- \
- return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
- IRQ_NONE; \
-}
-
-DEF_TALITOS1_INTERRUPT(4ch, TALITOS1_ISR_4CHDONE, TALITOS1_ISR_4CHERR, 0)
-
#define DEF_TALITOS2_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
static irqreturn_t talitos2_interrupt_##name(int irq, void *data) \
{ \
@@ -1262,29 +1023,6 @@ int talitos_register_common(struct device *dev,
return 0;
}
-static int sec1_talitos_probe_irq(struct platform_device *ofdev)
-{
- struct device *dev = &ofdev->dev;
- struct device_node *np = ofdev->dev.of_node;
- struct talitos_private *priv = dev_get_drvdata(dev);
- int err;
-
- priv->irq[0] = irq_of_parse_and_map(np, 0);
- if (!priv->irq[0]) {
- dev_err(dev, "failed to map irq\n");
- return -EINVAL;
- }
- err = request_irq(priv->irq[0], talitos1_interrupt_4ch, 0,
- dev_driver_string(dev), dev);
- if (err) {
- dev_err(dev, "failed to request primary irq\n");
- irq_dispose_mapping(priv->irq[0]);
- priv->irq[0] = 0;
- }
-
- return err;
-}
-
static int sec2_talitos_probe_irq(struct platform_device *ofdev)
{
struct device *dev = &ofdev->dev;
@@ -1332,18 +1070,6 @@ static int sec2_talitos_probe_irq(struct platform_device *ofdev)
return err;
}
-static void sec1_init_task(struct device *dev)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
-
- if (priv->num_channels == 1)
- tasklet_init(&priv->done_task[0], talitos1_done_ch0,
- (unsigned long)dev);
- else
- tasklet_init(&priv->done_task[0], talitos1_done_4ch,
- (unsigned long)dev);
-}
-
static void sec2_init_task(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
@@ -1362,19 +1088,6 @@ static void sec2_init_task(struct device *dev)
}
}
-static const struct talitos_ops sec1_ops = {
- .probe_irq = sec1_talitos_probe_irq,
- .init_task = sec1_init_task,
- .reset_device = sec1_reset_device,
- .reset_channel = sec1_reset_channel,
- .configure_device = sec1_configure_device,
- .dma_map_request = sec1_dma_map_request,
- .dma_unmap_request = sec1_dma_unmap_request,
- .get_request_hdr = sec1_get_request_hdr,
- .search_desc_hdr_in_request = sec1_search_desc_hdr_in_request,
- .handle_error = sec1_talitos_handle_error,
-};
-
static const struct talitos_ops sec2_ops = {
.probe_irq = sec2_talitos_probe_irq,
.init_task = sec2_init_task,
@@ -1471,7 +1184,7 @@ static int talitos_probe(struct platform_device *ofdev)
}
if (has_ftr_sec1(priv))
- priv->ops = &sec1_ops;
+ talitos_register_sec1(priv);
else
priv->ops = &sec2_ops;
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 98b2cb5115f8..f5e98050c4cb 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -566,6 +566,14 @@ __be32 talitos_current_desc_hdr(struct device *dev, int ch);
void talitos_error(struct device *dev, u32 isr, u32 isr_lo);
void talitos_report_eu_error(struct device *dev, int ch, __be32 desc_hdr);
+#ifdef CONFIG_CRYPTO_DEV_TALITOS1
+void talitos_register_sec1(struct talitos_private *priv);
+#else
+static inline void talitos_register_sec1(struct talitos_private *priv)
+{
+}
+#endif
+
/* Hardware RNG */
int talitos_register_rng(struct device *dev);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 23/29] crypto: talitos - Move SEC2 ops into talitos-sec2.c
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (21 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 22/29] crypto: talitos - Move SEC1 ops into talitos-sec1.c Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 24/29] crypto: talitos - Introduce per-SEC-version pointer helper ops Paul Louvel
` (5 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Relocate all SEC2-specific functions and the sec2_ops /
talitos_register_sec2() definitions from talitos.c into a new
talitos-sec2.c compilation unit.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/Makefile | 1 +
drivers/crypto/talitos/talitos-sec2.c | 330 ++++++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.c | 319 +-------------------------------
drivers/crypto/talitos/talitos.h | 8 +
4 files changed, 340 insertions(+), 318 deletions(-)
diff --git a/drivers/crypto/talitos/Makefile b/drivers/crypto/talitos/Makefile
index 5f3bc89ad7ea..3d9fa2570f2c 100644
--- a/drivers/crypto/talitos/Makefile
+++ b/drivers/crypto/talitos/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
talitos-y := talitos.o talitos-rng.o talitos-hash.o talitos-skcipher.o talitos-aead.o
talitos-$(CONFIG_CRYPTO_DEV_TALITOS1) += talitos-sec1.o
+talitos-$(CONFIG_CRYPTO_DEV_TALITOS2) += talitos-sec2.o
diff --git a/drivers/crypto/talitos/talitos-sec2.c b/drivers/crypto/talitos/talitos-sec2.c
new file mode 100644
index 000000000000..962e7cd43631
--- /dev/null
+++ b/drivers/crypto/talitos/talitos-sec2.c
@@ -0,0 +1,330 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Freescale SEC (talitos) SEC2 specific driver code
+ *
+ * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
+ */
+
+#include <linux/io.h>
+#include <linux/of_irq.h>
+
+#include "talitos.h"
+
+#define DEF_TALITOS2_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
+static irqreturn_t talitos2_interrupt_##name(int irq, void *data) \
+{ \
+ struct device *dev = data; \
+ struct talitos_private *priv = dev_get_drvdata(dev); \
+ u32 isr, isr_lo; \
+ unsigned long flags; \
+ \
+ spin_lock_irqsave(&priv->reg_lock, flags); \
+ isr = in_be32(priv->reg + TALITOS_ISR); \
+ isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
+ /* Acknowledge interrupt */ \
+ out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
+ out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
+ \
+ if (unlikely(isr & ch_err_mask || isr_lo)) { \
+ spin_unlock_irqrestore(&priv->reg_lock, flags); \
+ talitos_error(dev, isr & ch_err_mask, isr_lo); \
+ } \
+ else { \
+ if (likely(isr & ch_done_mask)) { \
+ /* mask further done interrupts. */ \
+ clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
+ /* done_task will unmask done interrupts at exit */ \
+ tasklet_schedule(&priv->done_task[tlet]); \
+ } \
+ spin_unlock_irqrestore(&priv->reg_lock, flags); \
+ } \
+ \
+ return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
+ IRQ_NONE; \
+}
+
+DEF_TALITOS2_INTERRUPT(4ch, TALITOS2_ISR_4CHDONE, TALITOS2_ISR_4CHERR, 0)
+DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE, TALITOS2_ISR_CH_0_2_ERR,
+ 0)
+DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
+ 1)
+
+#define DEF_TALITOS2_DONE(name, ch_done_mask) \
+static void talitos2_done_##name(unsigned long data) \
+{ \
+ struct device *dev = (struct device *)data; \
+ struct talitos_private *priv = dev_get_drvdata(dev); \
+ unsigned long flags; \
+ \
+ if (ch_done_mask & 1) \
+ talitos_flush_channel(dev, 0, 0, 0); \
+ if (ch_done_mask & (1 << 2)) \
+ talitos_flush_channel(dev, 1, 0, 0); \
+ if (ch_done_mask & (1 << 4)) \
+ talitos_flush_channel(dev, 2, 0, 0); \
+ if (ch_done_mask & (1 << 6)) \
+ talitos_flush_channel(dev, 3, 0, 0); \
+ \
+ /* At this point, all completed channels have been processed */ \
+ /* Unmask done interrupts for channels completed later on. */ \
+ spin_lock_irqsave(&priv->reg_lock, flags); \
+ setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
+ setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT); \
+ spin_unlock_irqrestore(&priv->reg_lock, flags); \
+}
+
+DEF_TALITOS2_DONE(4ch, TALITOS2_ISR_4CHDONE)
+DEF_TALITOS2_DONE(ch0, TALITOS2_ISR_CH_0_DONE)
+DEF_TALITOS2_DONE(ch0_2, TALITOS2_ISR_CH_0_2_DONE)
+DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE)
+
+static int sec2_reset_channel(struct device *dev, int ch)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ unsigned int timeout = TALITOS_TIMEOUT;
+
+ setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS2_CCCR_RESET);
+
+ while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
+ TALITOS2_CCCR_RESET) &&
+ --timeout)
+ cpu_relax();
+
+ if (timeout == 0) {
+ dev_err(dev, "failed to reset sec2 channel %d\n", ch);
+ return -EIO;
+ }
+
+ setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
+ TALITOS_CCCR_LO_EAE | TALITOS_CCCR_LO_CDWE |
+ TALITOS_CCCR_LO_CDIE);
+
+ /* ICCR writeback, if available */
+ if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
+ setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
+ TALITOS_CCCR_LO_IWSE);
+
+ return 0;
+}
+
+static int sec2_reset_device(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ unsigned int timeout = TALITOS_TIMEOUT;
+
+ setbits32(priv->reg + TALITOS_MCR, TALITOS2_MCR_SWR);
+
+ while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS2_MCR_SWR) &&
+ --timeout)
+ cpu_relax();
+
+ if (priv->irq[1])
+ setbits32(priv->reg + TALITOS_MCR,
+ TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3);
+
+ if (timeout == 0) {
+ dev_err(dev, "failed to reset sec2 device\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void sec2_configure_device(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ setbits32(priv->reg + TALITOS_IMR, TALITOS2_IMR_INIT);
+ setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT);
+
+ /* disable integrity check error interrupts (use writeback instead) */
+ if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
+ setbits32(priv->reg_mdeu + TALITOS_EUICR_LO,
+ TALITOS_MDEUICR_LO_ICE);
+}
+
+static void sec2_dma_map_request(struct device *dev,
+ struct talitos_request *request,
+ struct talitos_desc *desc)
+{
+ request->dma_desc =
+ dma_map_single(dev, desc, TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
+}
+
+static int sec2_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ unsigned int timeout = TALITOS_TIMEOUT;
+ int ch, error, reset_dev = 0;
+ u32 v_lo;
+ int reset_ch = 0;
+
+ for (ch = 0; ch < priv->num_channels; ch++) {
+ if (!TALITOS2_CH_HAS_ERROR(isr, ch))
+ continue;
+
+ error = -EINVAL;
+
+ v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
+
+ if (v_lo & TALITOS2_CCPSR_LO_DOF) {
+ dev_err(dev, "double fetch fifo overflow error\n");
+ error = -EAGAIN;
+ reset_ch = 1;
+ }
+ if (v_lo & TALITOS2_CCPSR_LO_SOF) {
+ /* h/w dropped descriptor */
+ dev_err(dev, "single fetch fifo overflow error\n");
+ error = -EAGAIN;
+ }
+ if (v_lo & TALITOS2_CCPSR_LO_MDTE)
+ dev_err(dev, "master data transfer error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_SGDLZ)
+ dev_err(dev, "s/g data length zero error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_FPZ)
+ dev_err(dev, "fetch pointer zero error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_IDH)
+ dev_err(dev, "illegal descriptor header error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_IEU)
+ dev_err(dev, "invalid exec unit error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_EU)
+ talitos_report_eu_error(
+ dev, ch, talitos_current_desc_hdr(dev, ch));
+ if (v_lo & TALITOS2_CCPSR_LO_GB)
+ dev_err(dev, "gather boundary error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_GRL)
+ dev_err(dev, "gather return/length error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_SB)
+ dev_err(dev, "scatter boundary error\n");
+ if (v_lo & TALITOS2_CCPSR_LO_SRL)
+ dev_err(dev, "scatter return/length error\n");
+
+ talitos_flush_channel(dev, ch, error, reset_ch);
+
+ if (reset_ch) {
+ priv->ops->reset_channel(dev, ch);
+ } else {
+ setbits32(priv->chan[ch].reg + TALITOS_CCCR,
+ TALITOS2_CCCR_CONT);
+ setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
+ while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
+ TALITOS2_CCCR_CONT) && --timeout)
+ cpu_relax();
+ if (timeout == 0) {
+ dev_err(dev, "failed to restart channel %d\n",
+ ch);
+ reset_dev = 1;
+ }
+ }
+ }
+
+ return reset_dev || (isr & ~TALITOS2_ISR_4CHERR) || isr_lo;
+}
+
+static int sec2_talitos_probe_irq(struct platform_device *ofdev)
+{
+ struct device *dev = &ofdev->dev;
+ struct device_node *np = ofdev->dev.of_node;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ int err;
+
+ priv->irq[0] = irq_of_parse_and_map(np, 0);
+ if (!priv->irq[0]) {
+ dev_err(dev, "failed to map irq\n");
+ return -EINVAL;
+ }
+ priv->irq[1] = irq_of_parse_and_map(np, 1);
+
+ /* get the primary irq line */
+ if (!priv->irq[1]) {
+ err = request_irq(priv->irq[0], talitos2_interrupt_4ch, 0,
+ dev_driver_string(dev), dev);
+ goto primary_out;
+ }
+
+ err = request_irq(priv->irq[0], talitos2_interrupt_ch0_2, 0,
+ dev_driver_string(dev), dev);
+ if (err)
+ goto primary_out;
+
+ /* get the secondary irq line */
+ err = request_irq(priv->irq[1], talitos2_interrupt_ch1_3, 0,
+ dev_driver_string(dev), dev);
+ if (err) {
+ dev_err(dev, "failed to request secondary irq\n");
+ irq_dispose_mapping(priv->irq[1]);
+ priv->irq[1] = 0;
+ }
+
+ return err;
+
+primary_out:
+ if (err) {
+ dev_err(dev, "failed to request primary irq\n");
+ irq_dispose_mapping(priv->irq[0]);
+ priv->irq[0] = 0;
+ }
+
+ return err;
+}
+
+static void sec2_init_task(struct device *dev)
+{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ if (priv->irq[1]) {
+ tasklet_init(&priv->done_task[0], talitos2_done_ch0_2,
+ (unsigned long)dev);
+ tasklet_init(&priv->done_task[1], talitos2_done_ch1_3,
+ (unsigned long)dev);
+ } else if (priv->num_channels == 1) {
+ tasklet_init(&priv->done_task[0], talitos2_done_ch0,
+ (unsigned long)dev);
+ } else {
+ tasklet_init(&priv->done_task[0], talitos2_done_4ch,
+ (unsigned long)dev);
+ }
+}
+
+static void sec2_dma_unmap_request(struct device *dev,
+ struct talitos_request *request)
+{
+ dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
+ DMA_BIDIRECTIONAL);
+}
+
+static __be32 sec2_get_request_hdr(struct device *dev,
+ struct talitos_request *request)
+{
+ dma_sync_single_for_cpu(dev, request->dma_desc, TALITOS_DESC_SIZE,
+ DMA_BIDIRECTIONAL);
+
+ return request->desc->hdr;
+}
+
+static __be32 sec2_search_desc_hdr_in_request(struct talitos_request *request,
+ dma_addr_t cur_desc)
+{
+ if (request->dma_desc == cur_desc)
+ return request->desc->hdr;
+ return 0;
+}
+
+static const struct talitos_ops sec2_ops = {
+ .probe_irq = sec2_talitos_probe_irq,
+ .init_task = sec2_init_task,
+ .reset_device = sec2_reset_device,
+ .reset_channel = sec2_reset_channel,
+ .configure_device = sec2_configure_device,
+ .dma_map_request = sec2_dma_map_request,
+ .dma_unmap_request = sec2_dma_unmap_request,
+ .get_request_hdr = sec2_get_request_hdr,
+ .search_desc_hdr_in_request = sec2_search_desc_hdr_in_request,
+ .handle_error = sec2_talitos_handle_error,
+};
+
+void talitos_register_sec2(struct talitos_private *priv)
+{
+ priv->ops = &sec2_ops;
+}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index a4fd14c8bef5..152618998819 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -133,71 +133,6 @@ void unmap_single_talitos_ptr(struct device *dev,
from_talitos_ptr_len(ptr, is_sec1), dir);
}
-static int sec2_reset_channel(struct device *dev, int ch)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
- unsigned int timeout = TALITOS_TIMEOUT;
-
- setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS2_CCCR_RESET);
-
- while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
- TALITOS2_CCCR_RESET) &&
- --timeout)
- cpu_relax();
-
- if (timeout == 0) {
- dev_err(dev, "failed to reset sec2 channel %d\n", ch);
- return -EIO;
- }
-
- setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
- TALITOS_CCCR_LO_EAE | TALITOS_CCCR_LO_CDWE |
- TALITOS_CCCR_LO_CDIE);
-
- /* ICCR writeback, if available */
- if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
- setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
- TALITOS_CCCR_LO_IWSE);
-
- return 0;
-}
-
-static int sec2_reset_device(struct device *dev)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
- unsigned int timeout = TALITOS_TIMEOUT;
-
- setbits32(priv->reg + TALITOS_MCR, TALITOS2_MCR_SWR);
-
- while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS2_MCR_SWR) &&
- --timeout)
- cpu_relax();
-
- if (priv->irq[1])
- setbits32(priv->reg + TALITOS_MCR,
- TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3);
-
- if (timeout == 0) {
- dev_err(dev, "failed to reset sec2 device\n");
- return -EIO;
- }
-
- return 0;
-}
-
-static void sec2_configure_device(struct device *dev)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
-
- setbits32(priv->reg + TALITOS_IMR, TALITOS2_IMR_INIT);
- setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT);
-
- /* disable integrity check error interrupts (use writeback instead) */
- if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
- setbits32(priv->reg_mdeu + TALITOS_EUICR_LO,
- TALITOS_MDEUICR_LO_ICE);
-}
-
/*
* Reset and initialize the device
*/
@@ -233,14 +168,6 @@ static int init_device(struct device *dev)
return 0;
}
-static void sec2_dma_map_request(struct device *dev,
- struct talitos_request *request,
- struct talitos_desc *desc)
-{
- request->dma_desc =
- dma_map_single(dev, desc, TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
-}
-
/**
* talitos_submit - submits a descriptor to the device for processing
* @dev: the SEC device to be used
@@ -299,22 +226,6 @@ int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
return -EINPROGRESS;
}
-static __be32 sec2_get_request_hdr(struct device *dev,
- struct talitos_request *request)
-{
- dma_sync_single_for_cpu(dev, request->dma_desc, TALITOS_DESC_SIZE,
- DMA_BIDIRECTIONAL);
-
- return request->desc->hdr;
-}
-
-static void sec2_dma_unmap_request(struct device *dev,
- struct talitos_request *request)
-{
- dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
- DMA_BIDIRECTIONAL);
-}
-
/*
* process what was done, notify callback of error if not
*/
@@ -375,47 +286,6 @@ void talitos_flush_channel(struct device *dev, int ch, int error, int reset_ch)
spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
}
-/*
- * process completed requests for channels that have done status
- */
-
-#define DEF_TALITOS2_DONE(name, ch_done_mask) \
-static void talitos2_done_##name(unsigned long data) \
-{ \
- struct device *dev = (struct device *)data; \
- struct talitos_private *priv = dev_get_drvdata(dev); \
- unsigned long flags; \
- \
- if (ch_done_mask & 1) \
- talitos_flush_channel(dev, 0, 0, 0); \
- if (ch_done_mask & (1 << 2)) \
- talitos_flush_channel(dev, 1, 0, 0); \
- if (ch_done_mask & (1 << 4)) \
- talitos_flush_channel(dev, 2, 0, 0); \
- if (ch_done_mask & (1 << 6)) \
- talitos_flush_channel(dev, 3, 0, 0); \
- \
- /* At this point, all completed channels have been processed */ \
- /* Unmask done interrupts for channels completed later on. */ \
- spin_lock_irqsave(&priv->reg_lock, flags); \
- setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
- setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT); \
- spin_unlock_irqrestore(&priv->reg_lock, flags); \
-}
-
-DEF_TALITOS2_DONE(4ch, TALITOS2_ISR_4CHDONE)
-DEF_TALITOS2_DONE(ch0, TALITOS2_ISR_CH_0_DONE)
-DEF_TALITOS2_DONE(ch0_2, TALITOS2_ISR_CH_0_2_DONE)
-DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE)
-
-static __be32 sec2_search_desc_hdr_in_request(struct talitos_request *request,
- dma_addr_t cur_desc)
-{
- if (request->dma_desc == cur_desc)
- return request->desc->hdr;
- return 0;
-}
-
/*
* locate current (offending) descriptor
*/
@@ -528,76 +398,6 @@ void talitos_report_eu_error(struct device *dev, int ch, __be32 desc_hdr)
in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
}
-static int sec2_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
- unsigned int timeout = TALITOS_TIMEOUT;
- int ch, error, reset_dev = 0;
- u32 v_lo;
- int reset_ch = 0;
-
- for (ch = 0; ch < priv->num_channels; ch++) {
- if (!TALITOS2_CH_HAS_ERROR(isr, ch))
- continue;
-
- error = -EINVAL;
-
- v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
-
- if (v_lo & TALITOS2_CCPSR_LO_DOF) {
- dev_err(dev, "double fetch fifo overflow error\n");
- error = -EAGAIN;
- reset_ch = 1;
- }
- if (v_lo & TALITOS2_CCPSR_LO_SOF) {
- /* h/w dropped descriptor */
- dev_err(dev, "single fetch fifo overflow error\n");
- error = -EAGAIN;
- }
- if (v_lo & TALITOS2_CCPSR_LO_MDTE)
- dev_err(dev, "master data transfer error\n");
- if (v_lo & TALITOS2_CCPSR_LO_SGDLZ)
- dev_err(dev, "s/g data length zero error\n");
- if (v_lo & TALITOS2_CCPSR_LO_FPZ)
- dev_err(dev, "fetch pointer zero error\n");
- if (v_lo & TALITOS2_CCPSR_LO_IDH)
- dev_err(dev, "illegal descriptor header error\n");
- if (v_lo & TALITOS2_CCPSR_LO_IEU)
- dev_err(dev, "invalid exec unit error\n");
- if (v_lo & TALITOS2_CCPSR_LO_EU)
- talitos_report_eu_error(
- dev, ch, talitos_current_desc_hdr(dev, ch));
- if (v_lo & TALITOS2_CCPSR_LO_GB)
- dev_err(dev, "gather boundary error\n");
- if (v_lo & TALITOS2_CCPSR_LO_GRL)
- dev_err(dev, "gather return/length error\n");
- if (v_lo & TALITOS2_CCPSR_LO_SB)
- dev_err(dev, "scatter boundary error\n");
- if (v_lo & TALITOS2_CCPSR_LO_SRL)
- dev_err(dev, "scatter return/length error\n");
-
- talitos_flush_channel(dev, ch, error, reset_ch);
-
- if (reset_ch) {
- priv->ops->reset_channel(dev, ch);
- } else {
- setbits32(priv->chan[ch].reg + TALITOS_CCCR,
- TALITOS2_CCCR_CONT);
- setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
- while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
- TALITOS2_CCCR_CONT) && --timeout)
- cpu_relax();
- if (timeout == 0) {
- dev_err(dev, "failed to restart channel %d\n",
- ch);
- reset_dev = 1;
- }
- }
- }
-
- return reset_dev || (isr & ~TALITOS2_ISR_4CHERR) || isr_lo;
-}
-
/*
* recover from error interrupts
*/
@@ -623,45 +423,6 @@ void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
}
}
-#define DEF_TALITOS2_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
-static irqreturn_t talitos2_interrupt_##name(int irq, void *data) \
-{ \
- struct device *dev = data; \
- struct talitos_private *priv = dev_get_drvdata(dev); \
- u32 isr, isr_lo; \
- unsigned long flags; \
- \
- spin_lock_irqsave(&priv->reg_lock, flags); \
- isr = in_be32(priv->reg + TALITOS_ISR); \
- isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
- /* Acknowledge interrupt */ \
- out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
- out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
- \
- if (unlikely(isr & ch_err_mask || isr_lo)) { \
- spin_unlock_irqrestore(&priv->reg_lock, flags); \
- talitos_error(dev, isr & ch_err_mask, isr_lo); \
- } \
- else { \
- if (likely(isr & ch_done_mask)) { \
- /* mask further done interrupts. */ \
- clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
- /* done_task will unmask done interrupts at exit */ \
- tasklet_schedule(&priv->done_task[tlet]); \
- } \
- spin_unlock_irqrestore(&priv->reg_lock, flags); \
- } \
- \
- return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
- IRQ_NONE; \
-}
-
-DEF_TALITOS2_INTERRUPT(4ch, TALITOS2_ISR_4CHDONE, TALITOS2_ISR_4CHERR, 0)
-DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE, TALITOS2_ISR_CH_0_2_ERR,
- 0)
-DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
- 1)
-
void talitos_sg_unmap(struct device *dev,
struct talitos_edesc *edesc,
struct scatterlist *src,
@@ -1023,84 +784,6 @@ int talitos_register_common(struct device *dev,
return 0;
}
-static int sec2_talitos_probe_irq(struct platform_device *ofdev)
-{
- struct device *dev = &ofdev->dev;
- struct device_node *np = ofdev->dev.of_node;
- struct talitos_private *priv = dev_get_drvdata(dev);
- int err;
-
- priv->irq[0] = irq_of_parse_and_map(np, 0);
- if (!priv->irq[0]) {
- dev_err(dev, "failed to map irq\n");
- return -EINVAL;
- }
- priv->irq[1] = irq_of_parse_and_map(np, 1);
-
- /* get the primary irq line */
- if (!priv->irq[1]) {
- err = request_irq(priv->irq[0], talitos2_interrupt_4ch, 0,
- dev_driver_string(dev), dev);
- goto primary_out;
- }
-
- err = request_irq(priv->irq[0], talitos2_interrupt_ch0_2, 0,
- dev_driver_string(dev), dev);
- if (err)
- goto primary_out;
-
- /* get the secondary irq line */
- err = request_irq(priv->irq[1], talitos2_interrupt_ch1_3, 0,
- dev_driver_string(dev), dev);
- if (err) {
- dev_err(dev, "failed to request secondary irq\n");
- irq_dispose_mapping(priv->irq[1]);
- priv->irq[1] = 0;
- }
-
- return err;
-
-primary_out:
- if (err) {
- dev_err(dev, "failed to request primary irq\n");
- irq_dispose_mapping(priv->irq[0]);
- priv->irq[0] = 0;
- }
-
- return err;
-}
-
-static void sec2_init_task(struct device *dev)
-{
- struct talitos_private *priv = dev_get_drvdata(dev);
-
- if (priv->irq[1]) {
- tasklet_init(&priv->done_task[0], talitos2_done_ch0_2,
- (unsigned long)dev);
- tasklet_init(&priv->done_task[1], talitos2_done_ch1_3,
- (unsigned long)dev);
- } else if (priv->num_channels == 1) {
- tasklet_init(&priv->done_task[0], talitos2_done_ch0,
- (unsigned long)dev);
- } else {
- tasklet_init(&priv->done_task[0], talitos2_done_4ch,
- (unsigned long)dev);
- }
-}
-
-static const struct talitos_ops sec2_ops = {
- .probe_irq = sec2_talitos_probe_irq,
- .init_task = sec2_init_task,
- .reset_device = sec2_reset_device,
- .reset_channel = sec2_reset_channel,
- .configure_device = sec2_configure_device,
- .dma_map_request = sec2_dma_map_request,
- .dma_unmap_request = sec2_dma_unmap_request,
- .get_request_hdr = sec2_get_request_hdr,
- .search_desc_hdr_in_request = sec2_search_desc_hdr_in_request,
- .handle_error = sec2_talitos_handle_error,
-};
-
static int talitos_probe(struct platform_device *ofdev)
{
struct device *dev = &ofdev->dev;
@@ -1186,7 +869,7 @@ static int talitos_probe(struct platform_device *ofdev)
if (has_ftr_sec1(priv))
talitos_register_sec1(priv);
else
- priv->ops = &sec2_ops;
+ talitos_register_sec2(priv);
err = priv->ops->probe_irq(ofdev);
if (err)
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index f5e98050c4cb..ae0bdb2ea78e 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -574,6 +574,14 @@ static inline void talitos_register_sec1(struct talitos_private *priv)
}
#endif
+#ifdef CONFIG_CRYPTO_DEV_TALITOS2
+void talitos_register_sec2(struct talitos_private *priv);
+#else
+static inline void talitos_register_sec2(struct talitos_private *priv)
+{
+}
+#endif
+
/* Hardware RNG */
int talitos_register_rng(struct device *dev);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 24/29] crypto: talitos - Introduce per-SEC-version pointer helper ops
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (22 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 23/29] crypto: talitos - Move SEC2 ops into talitos-sec2.c Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 25/29] crypto: talitos - Dispatch pointer helpers through ptr_ops Paul Louvel
` (4 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Introduce struct talitos_ptr_ops to abstract SEC1/SEC2 differences
in pointer handling behind per-SEC-version ops. Add ptr_ops to
struct talitos_private and struct talitos_ctx, and register the
appropriate SEC1 or SEC2 implementation at probe time.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-sec1.c | 36 +++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos-sec2.c | 40 +++++++++++++++++++++++++++++++++++
drivers/crypto/talitos/talitos.c | 2 ++
drivers/crypto/talitos/talitos.h | 12 +++++++++++
4 files changed, 90 insertions(+)
diff --git a/drivers/crypto/talitos/talitos-sec1.c b/drivers/crypto/talitos/talitos-sec1.c
index 695d531aa7f4..ef1bd19b6772 100644
--- a/drivers/crypto/talitos/talitos-sec1.c
+++ b/drivers/crypto/talitos/talitos-sec1.c
@@ -73,6 +73,33 @@ static irqreturn_t talitos1_interrupt_##name(int irq, void *data) \
DEF_TALITOS1_INTERRUPT(4ch, TALITOS1_ISR_4CHDONE, TALITOS1_ISR_4CHERR, 0)
+static void sec1_to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
+ unsigned int len)
+{
+ ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
+ ptr->len1 = cpu_to_be16(len);
+}
+
+static void sec1_copy_talitos_ptr(struct talitos_ptr *dst_ptr,
+ struct talitos_ptr *src_ptr)
+{
+ dst_ptr->ptr = src_ptr->ptr;
+ dst_ptr->len1 = src_ptr->len1;
+}
+
+static unsigned short sec1_from_talitos_ptr_len(struct talitos_ptr *ptr)
+{
+ return be16_to_cpu(ptr->len1);
+}
+
+static void sec1_to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val)
+{
+}
+
+static void sec1_to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val)
+{
+}
+
static int sec1_reset_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
@@ -286,6 +313,14 @@ static void sec1_init_task(struct device *dev)
(unsigned long)dev);
}
+static const struct talitos_ptr_ops sec1_ptr_ops = {
+ .to_talitos_ptr = sec1_to_talitos_ptr,
+ .copy_talitos_ptr = sec1_copy_talitos_ptr,
+ .from_talitos_ptr_len = sec1_from_talitos_ptr_len,
+ .to_talitos_ptr_ext_set = sec1_to_talitos_ptr_ext_set,
+ .to_talitos_ptr_ext_or = sec1_to_talitos_ptr_ext_or,
+};
+
static const struct talitos_ops sec1_ops = {
.probe_irq = sec1_talitos_probe_irq,
.init_task = sec1_init_task,
@@ -302,4 +337,5 @@ static const struct talitos_ops sec1_ops = {
void talitos_register_sec1(struct talitos_private *priv)
{
priv->ops = &sec1_ops;
+ priv->ptr_ops = &sec1_ptr_ops;
}
diff --git a/drivers/crypto/talitos/talitos-sec2.c b/drivers/crypto/talitos/talitos-sec2.c
index 962e7cd43631..14f0ca13e6e5 100644
--- a/drivers/crypto/talitos/talitos-sec2.c
+++ b/drivers/crypto/talitos/talitos-sec2.c
@@ -79,6 +79,37 @@ DEF_TALITOS2_DONE(ch0, TALITOS2_ISR_CH_0_DONE)
DEF_TALITOS2_DONE(ch0_2, TALITOS2_ISR_CH_0_2_DONE)
DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE)
+static void sec2_to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
+ unsigned int len)
+{
+ ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
+ ptr->len = cpu_to_be16(len);
+ ptr->eptr = upper_32_bits(dma_addr);
+}
+
+static void sec2_copy_talitos_ptr(struct talitos_ptr *dst_ptr,
+ struct talitos_ptr *src_ptr)
+{
+ dst_ptr->ptr = src_ptr->ptr;
+ dst_ptr->len = src_ptr->len;
+ dst_ptr->eptr = src_ptr->eptr;
+}
+
+static unsigned short sec2_from_talitos_ptr_len(struct talitos_ptr *ptr)
+{
+ return be16_to_cpu(ptr->len);
+}
+
+static void sec2_to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val)
+{
+ ptr->j_extent = val;
+}
+
+static void sec2_to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val)
+{
+ ptr->j_extent |= val;
+}
+
static int sec2_reset_channel(struct device *dev, int ch)
{
struct talitos_private *priv = dev_get_drvdata(dev);
@@ -311,6 +342,14 @@ static __be32 sec2_search_desc_hdr_in_request(struct talitos_request *request,
return 0;
}
+static const struct talitos_ptr_ops sec2_ptr_ops = {
+ .to_talitos_ptr = sec2_to_talitos_ptr,
+ .copy_talitos_ptr = sec2_copy_talitos_ptr,
+ .from_talitos_ptr_len = sec2_from_talitos_ptr_len,
+ .to_talitos_ptr_ext_set = sec2_to_talitos_ptr_ext_set,
+ .to_talitos_ptr_ext_or = sec2_to_talitos_ptr_ext_or,
+};
+
static const struct talitos_ops sec2_ops = {
.probe_irq = sec2_talitos_probe_irq,
.init_task = sec2_init_task,
@@ -327,4 +366,5 @@ static const struct talitos_ops sec2_ops = {
void talitos_register_sec2(struct talitos_private *priv)
{
priv->ops = &sec2_ops;
+ priv->ptr_ops = &sec2_ptr_ops;
}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 152618998819..0e4bd130ac6d 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -668,6 +668,8 @@ int talitos_init_common(struct talitos_ctx *ctx,
/* select done notification */
ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
+ ctx->ptr_ops = priv->ptr_ops;
+
return 0;
}
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index ae0bdb2ea78e..09d4e8fb0e62 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -140,6 +140,16 @@ struct talitos_channel {
int tail;
};
+struct talitos_ptr_ops {
+ void (*to_talitos_ptr)(struct talitos_ptr *ptr, dma_addr_t addr,
+ unsigned int len);
+ void (*copy_talitos_ptr)(struct talitos_ptr *dst_ptr,
+ struct talitos_ptr *src_ptr);
+ unsigned short (*from_talitos_ptr_len)(struct talitos_ptr *ptr);
+ void (*to_talitos_ptr_ext_set)(struct talitos_ptr *ptr, u8 val);
+ void (*to_talitos_ptr_ext_or)(struct talitos_ptr *ptr, u8 val);
+};
+
struct talitos_ops {
int (*probe_irq)(struct platform_device *ofdev);
void (*init_task)(struct device *dev);
@@ -183,6 +193,7 @@ struct talitos_private {
unsigned int desc_types;
const struct talitos_ops *ops;
+ const struct talitos_ptr_ops *ptr_ops;
/* SEC Compatibility info */
unsigned long features;
@@ -213,6 +224,7 @@ struct talitos_private {
struct talitos_ctx {
struct device *dev;
+ const struct talitos_ptr_ops *ptr_ops;
int ch;
__be32 desc_hdr_template;
u8 key[TALITOS_MAX_KEY_SIZE];
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 25/29] crypto: talitos - Dispatch pointer helpers through ptr_ops
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (23 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 24/29] crypto: talitos - Introduce per-SEC-version pointer helper ops Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 26/29] crypto: talitos - Remove now-unused global pointer helpers Paul Louvel
` (3 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Replace all direct calls to to_talitos_ptr(), copy_talitos_ptr(),
from_talitos_ptr_len(), to_talitos_ptr_ext_set() and
to_talitos_ptr_ext_or() with indirect calls through ctx->ptr_ops
or priv->ptr_ops.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-aead.c | 18 ++++++------
drivers/crypto/talitos/talitos-hash.c | 24 ++++++++--------
drivers/crypto/talitos/talitos-skcipher.c | 4 +--
drivers/crypto/talitos/talitos.c | 47 ++++++++++++++++---------------
4 files changed, 46 insertions(+), 47 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos/talitos-aead.c
index cd1b8e6d371b..b585abdd2275 100644
--- a/drivers/crypto/talitos/talitos-aead.c
+++ b/drivers/crypto/talitos/talitos-aead.c
@@ -216,7 +216,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
dma_addr_t dma_icv = edesc->dma_link_tbl + edesc->dma_len - authsize;
/* hmac key */
- to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen, is_sec1);
+ ctx->ptr_ops->to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen);
sg_count = edesc->src_nents ?: 1;
if (is_sec1 && sg_count > 1)
@@ -237,11 +237,11 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
}
/* cipher iv */
- to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize, is_sec1);
+ ctx->ptr_ops->to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize);
/* cipher key */
- to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen,
- ctx->enckeylen, is_sec1);
+ ctx->ptr_ops->to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen,
+ ctx->enckeylen);
/*
* cipher in
@@ -281,15 +281,15 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
/* Add an entry to the link table for ICV data */
- to_talitos_ptr_ext_set(tbl_ptr - 1, 0, is_sec1);
- to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET, is_sec1);
+ ctx->ptr_ops->to_talitos_ptr_ext_set(tbl_ptr - 1, 0);
+ ctx->ptr_ops->to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET);
/* icv data follows link tables */
- to_talitos_ptr(tbl_ptr, dma_icv, authsize, is_sec1);
- to_talitos_ptr_ext_or(&desc->ptr[5], authsize, is_sec1);
+ ctx->ptr_ops->to_talitos_ptr(tbl_ptr, dma_icv, authsize);
+ ctx->ptr_ops->to_talitos_ptr_ext_or(&desc->ptr[5], authsize);
sync_needed = true;
} else if (!encrypt) {
- to_talitos_ptr(&desc->ptr[6], dma_icv, authsize, is_sec1);
+ ctx->ptr_ops->to_talitos_ptr(&desc->ptr[6], dma_icv, authsize);
sync_needed = true;
} else if (!is_ipsec_esp) {
talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6],
diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos/talitos-hash.c
index 9e6d849c3123..026eebf037f5 100644
--- a/drivers/crypto/talitos/talitos-hash.c
+++ b/drivers/crypto/talitos/talitos-hash.c
@@ -36,32 +36,30 @@ struct talitos_export_state {
unsigned int to_hash_later;
};
-static void common_nonsnoop_hash_unmap(struct device *dev,
+static void common_nonsnoop_hash_unmap(struct talitos_ctx *ctx,
struct talitos_edesc *edesc,
struct ahash_request *areq)
{
struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
- struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
struct talitos_desc *desc = &edesc->desc;
- unmap_single_talitos_ptr(dev, &desc->ptr[5], DMA_FROM_DEVICE);
+ unmap_single_talitos_ptr(ctx->dev, &desc->ptr[5], DMA_FROM_DEVICE);
if (edesc->last && req_ctx->last_request)
memcpy(areq->result, req_ctx->hw_context,
crypto_ahash_digestsize(tfm));
if (edesc->src)
- talitos_sg_unmap(dev, edesc, edesc->src, NULL, 0, 0);
+ talitos_sg_unmap(ctx->dev, edesc, edesc->src, NULL, 0, 0);
/* When using hashctx-in, must unmap it. */
- if (from_talitos_ptr_len(&desc->ptr[1], is_sec1))
- unmap_single_talitos_ptr(dev, &desc->ptr[1],
+ if (ctx->ptr_ops->from_talitos_ptr_len(&desc->ptr[1]))
+ unmap_single_talitos_ptr(ctx->dev, &desc->ptr[1],
DMA_TO_DEVICE);
if (edesc->dma_len)
- dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
+ dma_unmap_single(ctx->dev, edesc->dma_link_tbl, edesc->dma_len,
DMA_BIDIRECTIONAL);
}
@@ -72,7 +70,7 @@ static void free_edesc_list_from(struct ahash_request *areq, struct talitos_edes
while (edesc) {
next = edesc->next_desc;
- common_nonsnoop_hash_unmap(ctx->dev, edesc, areq);
+ common_nonsnoop_hash_unmap(ctx, edesc, areq);
kfree(edesc);
edesc = next;
}
@@ -97,7 +95,7 @@ static void ahash_done(struct device *dev,
} else {
next = edesc->next_desc;
- common_nonsnoop_hash_unmap(dev, edesc, areq);
+ common_nonsnoop_hash_unmap(ctx, edesc, areq);
kfree(edesc);
if (err)
@@ -167,8 +165,8 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/* HMAC key */
if (ctx->keylen)
- to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen,
- is_sec1);
+ ctx->ptr_ops->to_talitos_ptr(&desc->ptr[2], ctx->dma_key,
+ ctx->keylen);
sg_count = edesc->src_nents ?: 1;
if (is_sec1 && sg_count > 1)
@@ -199,7 +197,7 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/* last DWORD empty */
- if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) == 0)
+ if (is_sec1 && ctx->ptr_ops->from_talitos_ptr_len(&desc->ptr[3]) == 0)
talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
if (sync_needed)
diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/talitos/talitos-skcipher.c
index b12191243aae..a96f827c7b93 100644
--- a/drivers/crypto/talitos/talitos-skcipher.c
+++ b/drivers/crypto/talitos/talitos-skcipher.c
@@ -67,10 +67,10 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/* first DWORD empty */
/* cipher iv */
- to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize, is_sec1);
+ ctx->ptr_ops->to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize);
/* cipher key */
- to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, is_sec1);
+ ctx->ptr_ops->to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen);
sg_count = edesc->src_nents ?: 1;
if (is_sec1 && sg_count > 1)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 0e4bd130ac6d..ff88f3dc3869 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -97,9 +97,8 @@ static void __map_single_talitos_ptr(struct device *dev,
{
dma_addr_t dma_addr = dma_map_single_attrs(dev, data, len, dir, attrs);
struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
- to_talitos_ptr(ptr, dma_addr, len, is_sec1);
+ priv->ptr_ops->to_talitos_ptr(ptr, dma_addr, len);
}
void map_single_talitos_ptr(struct device *dev,
@@ -127,10 +126,9 @@ void unmap_single_talitos_ptr(struct device *dev,
enum dma_data_direction dir)
{
struct talitos_private *priv = dev_get_drvdata(dev);
- bool is_sec1 = has_ftr_sec1(priv);
dma_unmap_single(dev, be32_to_cpu(ptr->ptr),
- from_talitos_ptr_len(ptr, is_sec1), dir);
+ priv->ptr_ops->from_talitos_ptr_len(ptr), dir);
}
/*
@@ -455,7 +453,8 @@ void talitos_sg_unmap(struct device *dev,
* convert scatterlist to SEC h/w link table format
* stop at cryptlen bytes
*/
-static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
+static int sg_to_link_tbl_offset(const struct talitos_ptr_ops *ptr_ops,
+ struct scatterlist *sg, int sg_count,
unsigned int offset, int datalen, int elen,
struct talitos_ptr *link_tbl_ptr, int align)
{
@@ -478,16 +477,16 @@ static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
len = cryptlen;
if (datalen > 0 && len > datalen) {
- to_talitos_ptr(link_tbl_ptr + count,
- sg_dma_address(sg) + offset, datalen, 0);
- to_talitos_ptr_ext_set(link_tbl_ptr + count, 0, 0);
+ ptr_ops->to_talitos_ptr(link_tbl_ptr + count,
+ sg_dma_address(sg) + offset, datalen);
+ ptr_ops->to_talitos_ptr_ext_set(link_tbl_ptr + count, 0);
count++;
len -= datalen;
offset += datalen;
}
- to_talitos_ptr(link_tbl_ptr + count,
- sg_dma_address(sg) + offset, sg_next(sg) ? len : len + padding, 0);
- to_talitos_ptr_ext_set(link_tbl_ptr + count, 0, 0);
+ ptr_ops->to_talitos_ptr(link_tbl_ptr + count,
+ sg_dma_address(sg) + offset, sg_next(sg) ? len : len + padding);
+ ptr_ops->to_talitos_ptr_ext_set(link_tbl_ptr + count, 0);
count++;
cryptlen -= len;
datalen -= len;
@@ -499,8 +498,8 @@ static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
/* tag end of link table */
if (count > 0)
- to_talitos_ptr_ext_set(link_tbl_ptr + count - 1,
- DESC_PTR_LNKTBL_RET, 0);
+ ptr_ops->to_talitos_ptr_ext_set(link_tbl_ptr + count - 1,
+ DESC_PTR_LNKTBL_RET);
return count;
}
@@ -512,32 +511,34 @@ int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
bool force, int align)
{
struct talitos_private *priv = dev_get_drvdata(dev);
+ const struct talitos_ptr_ops *ptr_ops = priv->ptr_ops;
bool is_sec1 = has_ftr_sec1(priv);
int aligned_len = ALIGN(len, align);
if (!src) {
- to_talitos_ptr(ptr, 0, 0, is_sec1);
+ ptr_ops->to_talitos_ptr(ptr, 0, 0);
return 1;
}
- to_talitos_ptr_ext_set(ptr, elen, is_sec1);
+ ptr_ops->to_talitos_ptr_ext_set(ptr, elen);
if (sg_count == 1 && !force) {
- to_talitos_ptr(ptr, sg_dma_address(src) + offset, aligned_len, is_sec1);
+ ptr_ops->to_talitos_ptr(ptr, sg_dma_address(src) + offset, aligned_len);
return sg_count;
}
if (is_sec1) {
- to_talitos_ptr(ptr, edesc->dma_link_tbl + offset, aligned_len, is_sec1);
+ ptr_ops->to_talitos_ptr(ptr, edesc->dma_link_tbl + offset, aligned_len);
return sg_count;
}
- sg_count = sg_to_link_tbl_offset(src, sg_count, offset, len, elen,
- &edesc->link_tbl[tbl_off], align);
+ sg_count = sg_to_link_tbl_offset(ptr_ops, src, sg_count, offset,
+ len, elen, &edesc->link_tbl[tbl_off],
+ align);
if (sg_count == 1 && !force) {
/* Only one segment now, so no link tbl needed*/
- copy_talitos_ptr(ptr, &edesc->link_tbl[tbl_off], is_sec1);
+ ptr_ops->copy_talitos_ptr(ptr, &edesc->link_tbl[tbl_off]);
return sg_count;
}
- to_talitos_ptr(ptr, edesc->dma_link_tbl +
- tbl_off * sizeof(struct talitos_ptr), aligned_len, is_sec1);
- to_talitos_ptr_ext_or(ptr, DESC_PTR_LNKTBL_JUMP, is_sec1);
+ ptr_ops->to_talitos_ptr(ptr, edesc->dma_link_tbl +
+ tbl_off * sizeof(struct talitos_ptr), aligned_len);
+ ptr_ops->to_talitos_ptr_ext_or(ptr, DESC_PTR_LNKTBL_JUMP);
return sg_count;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 26/29] crypto: talitos - Remove now-unused global pointer helpers
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (24 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 25/29] crypto: talitos - Dispatch pointer helpers through ptr_ops Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 27/29] crypto: talitos - Introduce per-SEC-version descriptor structures and ops Paul Louvel
` (2 subsequent siblings)
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Remove to_talitos_ptr(), copy_talitos_ptr(), from_talitos_ptr_len(),
to_talitos_ptr_ext_set() and to_talitos_ptr_ext_or() from talitos.c
and their declarations from talitos.h, now that all callers dispatch
through the per-SEC-version ptr_ops.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos.c | 46 ----------------------------------------
drivers/crypto/talitos/talitos.h | 8 -------
2 files changed, 54 deletions(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index ff88f3dc3869..19e63ce6cc3e 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -40,52 +40,6 @@
#include "talitos.h"
-void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
- unsigned int len, bool is_sec1)
-{
- ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
- if (is_sec1) {
- ptr->len1 = cpu_to_be16(len);
- } else {
- ptr->len = cpu_to_be16(len);
- ptr->eptr = upper_32_bits(dma_addr);
- }
-}
-
-void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
- struct talitos_ptr *src_ptr, bool is_sec1)
-{
- dst_ptr->ptr = src_ptr->ptr;
- if (is_sec1) {
- dst_ptr->len1 = src_ptr->len1;
- } else {
- dst_ptr->len = src_ptr->len;
- dst_ptr->eptr = src_ptr->eptr;
- }
-}
-
-unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
- bool is_sec1)
-{
- if (is_sec1)
- return be16_to_cpu(ptr->len1);
- else
- return be16_to_cpu(ptr->len);
-}
-
-void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
- bool is_sec1)
-{
- if (!is_sec1)
- ptr->j_extent = val;
-}
-
-void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1)
-{
- if (!is_sec1)
- ptr->j_extent |= val;
-}
-
/*
* map virtual single (contiguous) pointer to h/w descriptor pointer
*/
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 09d4e8fb0e62..54e33da03fd0 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -521,14 +521,6 @@ static inline bool has_ftr_sec1(struct talitos_private *priv)
#define DESC_PTR_LNKTBL_RET 0x02
#define DESC_PTR_LNKTBL_NEXT 0x01
-void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
- unsigned int len, bool is_sec1);
-void copy_talitos_ptr(struct talitos_ptr *dst_ptr, struct talitos_ptr *src_ptr,
- bool is_sec1);
-unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr, bool is_sec1);
-void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val, bool is_sec1);
-void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1);
-
void map_single_talitos_ptr(struct device *dev, struct talitos_ptr *ptr,
unsigned int len, void *data,
enum dma_data_direction dir);
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 27/29] crypto: talitos - Introduce per-SEC-version descriptor structures and ops
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (25 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 26/29] crypto: talitos - Remove now-unused global pointer helpers Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 28/29] crypto: talitos - Clean up includes in core driver file Paul Louvel
2026-05-28 9:08 ` [PATCH 29/29] crypto: talitos - Remove TALITOS_DESC_SIZE macro Paul Louvel
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
The driver used a single shared talitos_desc with overlapping union
members and a SEC1-specific "hdr1" hack to handle differences between
SEC1 and SEC2 descriptor layouts.
Introduce distinct sec1_talitos_desc/sec2_talitos_desc and
sec1_talitos_ptr/sec2_talitos_ptr structures, nested inside a union
in talitos_desc/talitos_ptr.
Mark them packed to reflect that these structures are used directly by
the hardware, even if the structure is naturally aligned.
Abstract descriptor field access through a new talitos_desc_ops
structure (set_hdr, get_hdr, get_hdr_lo, get_ptr), and add get_ptr_value
to the existing talitos_ptr_ops.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-aead.c | 76 +++++++++++++++++++------------
drivers/crypto/talitos/talitos-hash.c | 51 +++++++++++++--------
drivers/crypto/talitos/talitos-sec1.c | 61 +++++++++++++++++++------
drivers/crypto/talitos/talitos-sec2.c | 56 ++++++++++++++++++-----
drivers/crypto/talitos/talitos-skcipher.c | 46 +++++++++++--------
drivers/crypto/talitos/talitos.c | 4 +-
drivers/crypto/talitos/talitos.h | 60 +++++++++++++++++-------
7 files changed, 244 insertions(+), 110 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-aead.c b/drivers/crypto/talitos/talitos-aead.c
index b585abdd2275..d1cec7e4dd3f 100644
--- a/drivers/crypto/talitos/talitos-aead.c
+++ b/drivers/crypto/talitos/talitos-aead.c
@@ -94,12 +94,15 @@ static void ipsec_esp_unmap(struct device *dev,
unsigned int ivsize = crypto_aead_ivsize(aead);
unsigned int authsize = crypto_aead_authsize(aead);
unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
- bool is_ipsec_esp = edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP;
- struct talitos_ptr *civ_ptr = &edesc->desc.ptr[is_ipsec_esp ? 2 : 3];
+ bool is_ipsec_esp = ctx->desc_ops->get_hdr(&edesc->desc) &
+ DESC_HDR_TYPE_IPSEC_ESP;
+ struct talitos_ptr *civ_ptr =
+ ctx->desc_ops->get_ptr(&edesc->desc, is_ipsec_esp ? 2 : 3);
if (is_ipsec_esp)
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6],
- DMA_FROM_DEVICE);
+ unmap_single_talitos_ptr(
+ dev, ctx->desc_ops->get_ptr(&edesc->desc, 6),
+ DMA_FROM_DEVICE);
unmap_single_talitos_ptr(dev, civ_ptr, DMA_TO_DEVICE);
talitos_sg_unmap(dev, edesc, areq->src, areq->dst,
@@ -171,6 +174,7 @@ static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
struct talitos_desc *desc,
void *context, int err)
{
+ struct talitos_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(context));
struct aead_request *req = context;
struct talitos_edesc *edesc;
@@ -179,8 +183,8 @@ static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
ipsec_esp_unmap(dev, edesc, req, false);
/* check ICV auth status */
- if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
- DESC_HDR_LO_ICCR1_PASS))
+ if (!err && ((ctx->desc_ops->get_hdr_lo(desc) &
+ DESC_HDR_LO_ICCR1_MASK) != DESC_HDR_LO_ICCR1_PASS))
err = -EBADMSG;
kfree(edesc);
@@ -210,13 +214,17 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
bool sync_needed = false;
struct talitos_private *priv = dev_get_drvdata(dev);
bool is_sec1 = has_ftr_sec1(priv);
- bool is_ipsec_esp = desc->hdr & DESC_HDR_TYPE_IPSEC_ESP;
- struct talitos_ptr *civ_ptr = &desc->ptr[is_ipsec_esp ? 2 : 3];
- struct talitos_ptr *ckey_ptr = &desc->ptr[is_ipsec_esp ? 3 : 2];
+ bool is_ipsec_esp = ctx->desc_ops->get_hdr(desc) &
+ DESC_HDR_TYPE_IPSEC_ESP;
+ struct talitos_ptr *civ_ptr =
+ ctx->desc_ops->get_ptr(desc, is_ipsec_esp ? 2 : 3);
+ struct talitos_ptr *ckey_ptr =
+ ctx->desc_ops->get_ptr(desc, is_ipsec_esp ? 3 : 2);
dma_addr_t dma_icv = edesc->dma_link_tbl + edesc->dma_len - authsize;
/* hmac key */
- ctx->ptr_ops->to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen);
+ ctx->ptr_ops->to_talitos_ptr(ctx->desc_ops->get_ptr(desc, 0),
+ ctx->dma_key, ctx->authkeylen);
sg_count = edesc->src_nents ?: 1;
if (is_sec1 && sg_count > 1)
@@ -229,7 +237,8 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
/* hmac data */
ret = talitos_sg_map(dev, areq->src, areq->assoclen, edesc,
- &desc->ptr[1], sg_count, 0, tbl_off);
+ ctx->desc_ops->get_ptr(desc, 1), sg_count, 0,
+ tbl_off);
if (ret > 1) {
tbl_off += ret;
@@ -249,12 +258,13 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
* extent is bytes of HMAC postpended to ciphertext,
* typically 12 for ipsec
*/
- if (is_ipsec_esp && (desc->hdr & DESC_HDR_MODE1_MDEU_CICV))
+ if (is_ipsec_esp &&
+ (ctx->desc_ops->get_hdr(desc) & DESC_HDR_MODE1_MDEU_CICV))
elen = authsize;
- ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4],
- sg_count, areq->assoclen, tbl_off, elen,
- false, 1);
+ ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc,
+ ctx->desc_ops->get_ptr(desc, 4), sg_count,
+ areq->assoclen, tbl_off, elen, false, 1);
if (ret > 1) {
tbl_off += ret;
@@ -272,8 +282,9 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
elen = authsize;
else
elen = 0;
- ret = talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, &desc->ptr[5],
- sg_count, areq->assoclen, tbl_off, elen,
+ ret = talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc,
+ ctx->desc_ops->get_ptr(desc, 5), sg_count,
+ areq->assoclen, tbl_off, elen,
is_ipsec_esp && !encrypt, 1);
tbl_off += ret;
@@ -286,20 +297,23 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
/* icv data follows link tables */
ctx->ptr_ops->to_talitos_ptr(tbl_ptr, dma_icv, authsize);
- ctx->ptr_ops->to_talitos_ptr_ext_or(&desc->ptr[5], authsize);
+ ctx->ptr_ops->to_talitos_ptr_ext_or(
+ ctx->desc_ops->get_ptr(desc, 5), authsize);
sync_needed = true;
} else if (!encrypt) {
- ctx->ptr_ops->to_talitos_ptr(&desc->ptr[6], dma_icv, authsize);
+ ctx->ptr_ops->to_talitos_ptr(ctx->desc_ops->get_ptr(desc, 6),
+ dma_icv, authsize);
sync_needed = true;
} else if (!is_ipsec_esp) {
- talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6],
- sg_count, areq->assoclen + cryptlen, tbl_off);
+ talitos_sg_map(dev, areq->dst, authsize, edesc,
+ ctx->desc_ops->get_ptr(desc, 6), sg_count,
+ areq->assoclen + cryptlen, tbl_off);
}
/* iv out */
if (is_ipsec_esp)
- map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
- DMA_FROM_DEVICE);
+ map_single_talitos_ptr(dev, ctx->desc_ops->get_ptr(desc, 6),
+ ivsize, ctx->iv, DMA_FROM_DEVICE);
if (sync_needed)
dma_sync_single_for_device(dev, edesc->dma_link_tbl,
@@ -341,7 +355,7 @@ static int aead_encrypt(struct aead_request *req)
return PTR_ERR(edesc);
/* set encrypt */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
+ ctx->desc_ops->set_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT);
return ipsec_esp(edesc, req, true, ipsec_esp_encrypt_done);
}
@@ -354,21 +368,24 @@ static int aead_decrypt(struct aead_request *req)
struct talitos_private *priv = dev_get_drvdata(ctx->dev);
struct talitos_edesc *edesc;
void *icvdata;
+ __be32 hdr;
/* allocate extended descriptor */
edesc = aead_edesc_alloc(req, req->iv, 1, false);
if (IS_ERR(edesc))
return PTR_ERR(edesc);
- if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) &&
+ hdr = ctx->desc_ops->get_hdr(&edesc->desc);
+ if ((hdr & DESC_HDR_TYPE_IPSEC_ESP) &&
(priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
((!edesc->src_nents && !edesc->dst_nents) ||
priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
/* decrypt and check the ICV */
- edesc->desc.hdr = ctx->desc_hdr_template |
- DESC_HDR_DIR_INBOUND |
- DESC_HDR_MODE1_MDEU_CICV;
+ ctx->desc_ops->set_hdr(&edesc->desc,
+ ctx->desc_hdr_template |
+ DESC_HDR_DIR_INBOUND |
+ DESC_HDR_MODE1_MDEU_CICV);
/* reset integrity check result bits */
@@ -377,7 +394,8 @@ static int aead_decrypt(struct aead_request *req)
}
/* Have to check the ICV with software */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
+ ctx->desc_ops->set_hdr(&edesc->desc,
+ ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND);
/* stash incoming ICV for later cmp with ICV generated by the h/w */
icvdata = edesc->buf + edesc->dma_len;
diff --git a/drivers/crypto/talitos/talitos-hash.c b/drivers/crypto/talitos/talitos-hash.c
index 026eebf037f5..fb4d53e2abf8 100644
--- a/drivers/crypto/talitos/talitos-hash.c
+++ b/drivers/crypto/talitos/talitos-hash.c
@@ -44,7 +44,8 @@ static void common_nonsnoop_hash_unmap(struct talitos_ctx *ctx,
struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
struct talitos_desc *desc = &edesc->desc;
- unmap_single_talitos_ptr(ctx->dev, &desc->ptr[5], DMA_FROM_DEVICE);
+ unmap_single_talitos_ptr(ctx->dev, ctx->desc_ops->get_ptr(desc, 5),
+ DMA_FROM_DEVICE);
if (edesc->last && req_ctx->last_request)
memcpy(areq->result, req_ctx->hw_context,
@@ -54,8 +55,9 @@ static void common_nonsnoop_hash_unmap(struct talitos_ctx *ctx,
talitos_sg_unmap(ctx->dev, edesc, edesc->src, NULL, 0, 0);
/* When using hashctx-in, must unmap it. */
- if (ctx->ptr_ops->from_talitos_ptr_len(&desc->ptr[1]))
- unmap_single_talitos_ptr(ctx->dev, &desc->ptr[1],
+ if (ctx->ptr_ops->from_talitos_ptr_len(ctx->desc_ops->get_ptr(desc, 1)))
+ unmap_single_talitos_ptr(ctx->dev,
+ ctx->desc_ops->get_ptr(desc, 1),
DMA_TO_DEVICE);
if (edesc->dma_len)
@@ -131,7 +133,9 @@ static void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
};
pr_err_once("Bug in SEC1, padding ourself\n");
- edesc->desc.hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
+ ctx->desc_ops->set_hdr(&edesc->desc,
+ ctx->desc_ops->get_hdr(&edesc->desc) &
+ ~DESC_HDR_MODE0_MDEU_PAD);
map_single_talitos_ptr(ctx->dev, ptr, sizeof(padded_hash),
(char *)padded_hash, DMA_TO_DEVICE);
}
@@ -154,7 +158,8 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/* hash context in */
if (!edesc->first || !req_ctx->first_request || req_ctx->swinit) {
- map_single_talitos_ptr_nosync(dev, &desc->ptr[1],
+ map_single_talitos_ptr_nosync(dev,
+ ctx->desc_ops->get_ptr(desc, 1),
req_ctx->hw_context_size,
req_ctx->hw_context,
DMA_TO_DEVICE);
@@ -165,8 +170,8 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/* HMAC key */
if (ctx->keylen)
- ctx->ptr_ops->to_talitos_ptr(&desc->ptr[2], ctx->dma_key,
- ctx->keylen);
+ ctx->ptr_ops->to_talitos_ptr(ctx->desc_ops->get_ptr(desc, 2),
+ ctx->dma_key, ctx->keylen);
sg_count = edesc->src_nents ?: 1;
if (is_sec1 && sg_count > 1)
@@ -177,8 +182,10 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/*
* data in
*/
- sg_count = talitos_sg_map(dev, edesc->src, length, edesc, &desc->ptr[3],
- sg_count, 0, 0);
+ sg_count = talitos_sg_map(dev, edesc->src, length, edesc,
+ ctx->desc_ops->get_ptr(desc, 3), sg_count, 0,
+ 0);
+
if (sg_count > 1)
sync_needed = true;
@@ -186,19 +193,22 @@ static void common_nonsnoop_hash(struct talitos_edesc *edesc,
/* hash/HMAC out -or- hash context out */
if (edesc->last && req_ctx->last_request)
- map_single_talitos_ptr(dev, &desc->ptr[5],
+ map_single_talitos_ptr(dev, ctx->desc_ops->get_ptr(desc, 5),
crypto_ahash_digestsize(tfm),
req_ctx->hw_context, DMA_FROM_DEVICE);
else
- map_single_talitos_ptr_nosync(dev, &desc->ptr[5],
+ map_single_talitos_ptr_nosync(dev,
+ ctx->desc_ops->get_ptr(desc, 5),
req_ctx->hw_context_size,
req_ctx->hw_context,
DMA_FROM_DEVICE);
/* last DWORD empty */
- if (is_sec1 && ctx->ptr_ops->from_talitos_ptr_len(&desc->ptr[3]) == 0)
- talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
+ if (is_sec1 && ctx->ptr_ops->from_talitos_ptr_len(
+ ctx->desc_ops->get_ptr(desc, 3)) == 0)
+ talitos_handle_buggy_hash(ctx, edesc,
+ ctx->desc_ops->get_ptr(desc, 3));
if (sync_needed)
dma_sync_single_for_device(dev, edesc->dma_link_tbl,
@@ -229,6 +239,7 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
size_t to_hash_this_desc;
struct scatterlist *src;
size_t offset = 0;
+ __be32 hdr;
do {
src = scatterwalk_ffwd(tmp, areq->src, offset);
@@ -245,19 +256,19 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
}
edesc->src = scatterwalk_ffwd(edesc->bufsl, areq->src, offset);
- edesc->desc.hdr = ctx->desc_hdr_template;
+ hdr = ctx->desc_hdr_template;
edesc->first = offset == 0;
edesc->last = nbytes - to_hash_this_desc == 0;
/* On last one, request SEC to pad; otherwise continue */
if (req_ctx->last_request && edesc->last)
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
+ hdr |= DESC_HDR_MODE0_MDEU_PAD;
else
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
+ hdr |= DESC_HDR_MODE0_MDEU_CONT;
/* request SEC to INIT hash. */
if (req_ctx->first_request && edesc->first && !req_ctx->swinit)
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
+ hdr |= DESC_HDR_MODE0_MDEU_INIT;
/*
* When the tfm context has a keylen, it's an HMAC.
@@ -265,11 +276,13 @@ ahash_process_req_prepare(struct ahash_request *areq, unsigned int nbytes,
*/
if (ctx->keylen && ((req_ctx->first_request && edesc->first) ||
(req_ctx->last_request && edesc->last)))
- edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
+ hdr |= DESC_HDR_MODE0_MDEU_HMAC;
/* clear the DN bit */
if (is_sec1 && !edesc->last)
- edesc->desc.hdr &= ~DESC_HDR_DONE_NOTIFY;
+ hdr &= ~DESC_HDR_DONE_NOTIFY;
+
+ ctx->desc_ops->set_hdr(&edesc->desc, hdr);
common_nonsnoop_hash(edesc, areq, to_hash_this_desc);
diff --git a/drivers/crypto/talitos/talitos-sec1.c b/drivers/crypto/talitos/talitos-sec1.c
index ef1bd19b6772..e4f482520372 100644
--- a/drivers/crypto/talitos/talitos-sec1.c
+++ b/drivers/crypto/talitos/talitos-sec1.c
@@ -76,20 +76,20 @@ DEF_TALITOS1_INTERRUPT(4ch, TALITOS1_ISR_4CHDONE, TALITOS1_ISR_4CHERR, 0)
static void sec1_to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
unsigned int len)
{
- ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
- ptr->len1 = cpu_to_be16(len);
+ ptr->sec1.ptr = cpu_to_be32(lower_32_bits(dma_addr));
+ ptr->sec1.len = cpu_to_be16(len);
}
static void sec1_copy_talitos_ptr(struct talitos_ptr *dst_ptr,
struct talitos_ptr *src_ptr)
{
- dst_ptr->ptr = src_ptr->ptr;
- dst_ptr->len1 = src_ptr->len1;
+ dst_ptr->sec1.ptr = src_ptr->sec1.ptr;
+ dst_ptr->sec1.len = src_ptr->sec1.len;
}
static unsigned short sec1_from_talitos_ptr_len(struct talitos_ptr *ptr)
{
- return be16_to_cpu(ptr->len1);
+ return be16_to_cpu(ptr->sec1.len);
}
static void sec1_to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val)
@@ -100,6 +100,31 @@ static void sec1_to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val)
{
}
+static __be32 sec1_get_ptr_value(struct talitos_ptr *ptr)
+{
+ return ptr->sec1.ptr;
+}
+
+static __be32 sec1_get_hdr(struct talitos_desc *desc)
+{
+ return desc->sec1.hdr;
+}
+
+static __be32 sec1_get_hdr_lo(struct talitos_desc *desc)
+{
+ return 0;
+}
+
+static void sec1_set_hdr(struct talitos_desc *desc, __be32 val)
+{
+ desc->sec1.hdr = val;
+}
+
+static struct talitos_ptr *sec1_get_ptr(struct talitos_desc *desc, size_t idx)
+{
+ return (struct talitos_ptr *)&desc->sec1.ptr[idx];
+}
+
static int sec1_reset_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
@@ -163,9 +188,8 @@ static void sec1_dma_map_request(struct device *dev,
struct talitos_edesc *prev_edesc = NULL;
while (edesc) {
- edesc->desc.hdr1 = edesc->desc.hdr;
- dma_desc = dma_map_single(dev, &edesc->desc.hdr1,
+ dma_desc = dma_map_single(dev, &edesc->desc.sec1.hdr,
TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
if (!prev_edesc) {
@@ -175,7 +199,7 @@ static void sec1_dma_map_request(struct device *dev,
/* Chain in any previous descriptors. */
- prev_edesc->desc.next_desc = cpu_to_be32(dma_desc);
+ prev_edesc->desc.sec1.next_desc = cpu_to_be32(dma_desc);
dma_sync_single_for_device(dev, prev_dma_desc,
TALITOS_DESC_SIZE, DMA_TO_DEVICE);
@@ -196,7 +220,7 @@ static void sec1_dma_unmap_request(struct device *dev,
DMA_BIDIRECTIONAL);
edesc = container_of(request->desc, struct talitos_edesc, desc);
while (edesc->next_desc) {
- dma_unmap_single(dev, be32_to_cpu(edesc->desc.next_desc),
+ dma_unmap_single(dev, be32_to_cpu(edesc->desc.sec1.next_desc),
TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
edesc = edesc->next_desc;
}
@@ -211,14 +235,14 @@ static __be32 sec1_get_request_hdr(struct device *dev,
edesc = container_of(request->desc, struct talitos_edesc, desc);
dma_desc = request->dma_desc;
while (edesc->next_desc) {
- dma_desc = be32_to_cpu(edesc->desc.next_desc);
+ dma_desc = be32_to_cpu(edesc->desc.sec1.next_desc);
edesc = edesc->next_desc;
}
dma_sync_single_for_cpu(dev, dma_desc, TALITOS_DESC_SIZE,
DMA_BIDIRECTIONAL);
- return edesc->desc.hdr1;
+ return edesc->desc.sec1.hdr;
}
static __be32 sec1_search_desc_hdr_in_request(struct talitos_request *request,
@@ -228,12 +252,12 @@ static __be32 sec1_search_desc_hdr_in_request(struct talitos_request *request,
if (request->dma_desc == cur_desc)
- return request->desc->hdr;
+ return request->desc->sec1.hdr;
edesc = container_of(request->desc, struct talitos_edesc, desc);
while (edesc->next_desc) {
- if (edesc->desc.next_desc == cpu_to_be32(cur_desc))
- return edesc->next_desc->desc.hdr1;
+ if (edesc->desc.sec1.next_desc == cpu_to_be32(cur_desc))
+ return edesc->next_desc->desc.sec1.hdr;
edesc = edesc->next_desc;
}
@@ -319,6 +343,14 @@ static const struct talitos_ptr_ops sec1_ptr_ops = {
.from_talitos_ptr_len = sec1_from_talitos_ptr_len,
.to_talitos_ptr_ext_set = sec1_to_talitos_ptr_ext_set,
.to_talitos_ptr_ext_or = sec1_to_talitos_ptr_ext_or,
+ .get_ptr_value = sec1_get_ptr_value,
+};
+
+static const struct talitos_desc_ops sec1_desc_ops = {
+ .set_hdr = sec1_set_hdr,
+ .get_hdr = sec1_get_hdr,
+ .get_hdr_lo = sec1_get_hdr_lo,
+ .get_ptr = sec1_get_ptr,
};
static const struct talitos_ops sec1_ops = {
@@ -337,5 +369,6 @@ static const struct talitos_ops sec1_ops = {
void talitos_register_sec1(struct talitos_private *priv)
{
priv->ops = &sec1_ops;
+ priv->desc_ops = &sec1_desc_ops;
priv->ptr_ops = &sec1_ptr_ops;
}
diff --git a/drivers/crypto/talitos/talitos-sec2.c b/drivers/crypto/talitos/talitos-sec2.c
index 14f0ca13e6e5..52f783ddc8b6 100644
--- a/drivers/crypto/talitos/talitos-sec2.c
+++ b/drivers/crypto/talitos/talitos-sec2.c
@@ -82,32 +82,57 @@ DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE)
static void sec2_to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
unsigned int len)
{
- ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
- ptr->len = cpu_to_be16(len);
- ptr->eptr = upper_32_bits(dma_addr);
+ ptr->sec2.ptr = cpu_to_be32(lower_32_bits(dma_addr));
+ ptr->sec2.len = cpu_to_be16(len);
+ ptr->sec2.eptr = upper_32_bits(dma_addr);
}
static void sec2_copy_talitos_ptr(struct talitos_ptr *dst_ptr,
struct talitos_ptr *src_ptr)
{
- dst_ptr->ptr = src_ptr->ptr;
- dst_ptr->len = src_ptr->len;
- dst_ptr->eptr = src_ptr->eptr;
+ dst_ptr->sec2.ptr = src_ptr->sec2.ptr;
+ dst_ptr->sec2.len = src_ptr->sec2.len;
+ dst_ptr->sec2.eptr = src_ptr->sec2.eptr;
}
static unsigned short sec2_from_talitos_ptr_len(struct talitos_ptr *ptr)
{
- return be16_to_cpu(ptr->len);
+ return be16_to_cpu(ptr->sec2.len);
}
static void sec2_to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val)
{
- ptr->j_extent = val;
+ ptr->sec2.j_extent = val;
}
static void sec2_to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val)
{
- ptr->j_extent |= val;
+ ptr->sec2.j_extent |= val;
+}
+
+static __be32 sec2_get_ptr_value(struct talitos_ptr *ptr)
+{
+ return ptr->sec2.ptr;
+}
+
+static __be32 sec2_get_hdr(struct talitos_desc *desc)
+{
+ return desc->sec2.hdr;
+}
+
+static __be32 sec2_get_hdr_lo(struct talitos_desc *desc)
+{
+ return desc->sec2.hdr_lo;
+}
+
+static void sec2_set_hdr(struct talitos_desc *desc, __be32 val)
+{
+ desc->sec2.hdr = val;
+}
+
+static struct talitos_ptr *sec2_get_ptr(struct talitos_desc *desc, size_t idx)
+{
+ return (struct talitos_ptr *)&desc->sec2.ptr[idx];
}
static int sec2_reset_channel(struct device *dev, int ch)
@@ -331,14 +356,14 @@ static __be32 sec2_get_request_hdr(struct device *dev,
dma_sync_single_for_cpu(dev, request->dma_desc, TALITOS_DESC_SIZE,
DMA_BIDIRECTIONAL);
- return request->desc->hdr;
+ return request->desc->sec2.hdr;
}
static __be32 sec2_search_desc_hdr_in_request(struct talitos_request *request,
dma_addr_t cur_desc)
{
if (request->dma_desc == cur_desc)
- return request->desc->hdr;
+ return request->desc->sec2.hdr;
return 0;
}
@@ -348,6 +373,14 @@ static const struct talitos_ptr_ops sec2_ptr_ops = {
.from_talitos_ptr_len = sec2_from_talitos_ptr_len,
.to_talitos_ptr_ext_set = sec2_to_talitos_ptr_ext_set,
.to_talitos_ptr_ext_or = sec2_to_talitos_ptr_ext_or,
+ .get_ptr_value = sec2_get_ptr_value,
+};
+
+static const struct talitos_desc_ops sec2_desc_ops = {
+ .set_hdr = sec2_set_hdr,
+ .get_hdr = sec2_get_hdr,
+ .get_hdr_lo = sec2_get_hdr_lo,
+ .get_ptr = sec2_get_ptr,
};
static const struct talitos_ops sec2_ops = {
@@ -366,5 +399,6 @@ static const struct talitos_ops sec2_ops = {
void talitos_register_sec2(struct talitos_private *priv)
{
priv->ops = &sec2_ops;
+ priv->desc_ops = &sec2_desc_ops;
priv->ptr_ops = &sec2_ptr_ops;
}
diff --git a/drivers/crypto/talitos/talitos-skcipher.c b/drivers/crypto/talitos/talitos-skcipher.c
index a96f827c7b93..58ad931ff3a4 100644
--- a/drivers/crypto/talitos/talitos-skcipher.c
+++ b/drivers/crypto/talitos/talitos-skcipher.c
@@ -11,17 +11,21 @@
#include "talitos.h"
-static void common_nonsnoop_unmap(struct device *dev,
+static void common_nonsnoop_unmap(struct talitos_ctx *ctx,
struct talitos_edesc *edesc,
struct skcipher_request *areq)
{
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
+ unmap_single_talitos_ptr(ctx->dev,
+ ctx->desc_ops->get_ptr(&edesc->desc, 5),
+ DMA_FROM_DEVICE);
- talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen, 0);
- unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
+ talitos_sg_unmap(ctx->dev, edesc, areq->src, areq->dst, areq->cryptlen, 0);
+ unmap_single_talitos_ptr(ctx->dev,
+ ctx->desc_ops->get_ptr(&edesc->desc, 1),
+ DMA_TO_DEVICE);
if (edesc->dma_len)
- dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
+ dma_unmap_single(ctx->dev, edesc->dma_link_tbl, edesc->dma_len,
DMA_BIDIRECTIONAL);
}
@@ -37,7 +41,7 @@ static void skcipher_done(struct device *dev,
edesc = container_of(desc, struct talitos_edesc, desc);
- common_nonsnoop_unmap(dev, edesc, areq);
+ common_nonsnoop_unmap(ctx, edesc, areq);
memcpy(areq->iv, ctx->iv, ivsize);
kfree(edesc);
@@ -61,16 +65,18 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
bool sync_needed = false;
struct talitos_private *priv = dev_get_drvdata(dev);
bool is_sec1 = has_ftr_sec1(priv);
- bool is_ctr = (desc->hdr & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_AESU &&
- (desc->hdr & DESC_HDR_MODE0_AESU_MASK) == DESC_HDR_MODE0_AESU_CTR;
+ bool is_ctr = (ctx->desc_ops->get_hdr(desc) & DESC_HDR_SEL0_MASK) ==
+ DESC_HDR_SEL0_AESU &&
+ (ctx->desc_ops->get_hdr(desc) &
+ DESC_HDR_MODE0_AESU_MASK) == DESC_HDR_MODE0_AESU_CTR;
/* first DWORD empty */
/* cipher iv */
- ctx->ptr_ops->to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize);
+ ctx->ptr_ops->to_talitos_ptr(ctx->desc_ops->get_ptr(desc, 1), edesc->iv_dma, ivsize);
/* cipher key */
- ctx->ptr_ops->to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen);
+ ctx->ptr_ops->to_talitos_ptr(ctx->desc_ops->get_ptr(desc, 2), ctx->dma_key, ctx->keylen);
sg_count = edesc->src_nents ?: 1;
if (is_sec1 && sg_count > 1)
@@ -83,8 +89,9 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/*
* cipher in
*/
- sg_count = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[3],
- sg_count, 0, 0, 0, false, is_ctr ? 16 : 1);
+ sg_count = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc,
+ ctx->desc_ops->get_ptr(desc, 3), sg_count,
+ 0, 0, 0, false, is_ctr ? 16 : 1);
if (sg_count > 1)
sync_needed = true;
@@ -95,14 +102,15 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
}
- ret = talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[4],
- sg_count, 0, (edesc->src_nents + 1));
+ ret = talitos_sg_map(dev, areq->dst, cryptlen, edesc,
+ ctx->desc_ops->get_ptr(desc, 4), sg_count, 0,
+ (edesc->src_nents + 1));
if (ret > 1)
sync_needed = true;
/* iv out */
- map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv,
- DMA_FROM_DEVICE);
+ map_single_talitos_ptr(dev, ctx->desc_ops->get_ptr(desc, 5), ivsize,
+ ctx->iv, DMA_FROM_DEVICE);
/* last DWORD empty */
@@ -112,7 +120,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
if (ret != -EINPROGRESS) {
- common_nonsnoop_unmap(dev, edesc, areq);
+ common_nonsnoop_unmap(ctx, edesc, areq);
kfree(edesc);
}
return ret;
@@ -191,7 +199,7 @@ static int skcipher_encrypt(struct skcipher_request *areq)
return PTR_ERR(edesc);
/* set encrypt */
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
+ ctx->desc_ops->set_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT);
return common_nonsnoop(edesc, areq, skcipher_done);
}
@@ -215,7 +223,7 @@ static int skcipher_decrypt(struct skcipher_request *areq)
if (IS_ERR(edesc))
return PTR_ERR(edesc);
- edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
+ ctx->desc_ops->set_hdr(&edesc->desc, ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND);
return common_nonsnoop(edesc, areq, skcipher_done);
}
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index 19e63ce6cc3e..a032907e900f 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -81,7 +81,7 @@ void unmap_single_talitos_ptr(struct device *dev,
{
struct talitos_private *priv = dev_get_drvdata(dev);
- dma_unmap_single(dev, be32_to_cpu(ptr->ptr),
+ dma_unmap_single(dev, be32_to_cpu(priv->ptr_ops->get_ptr_value(ptr)),
priv->ptr_ops->from_talitos_ptr_len(ptr), dir);
}
@@ -625,6 +625,8 @@ int talitos_init_common(struct talitos_ctx *ctx,
ctx->ptr_ops = priv->ptr_ops;
+ ctx->desc_ops = priv->desc_ops;
+
return 0;
}
diff --git a/drivers/crypto/talitos/talitos.h b/drivers/crypto/talitos/talitos.h
index 54e33da03fd0..2107fb1ade5d 100644
--- a/drivers/crypto/talitos/talitos.h
+++ b/drivers/crypto/talitos/talitos.h
@@ -36,33 +36,49 @@
#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
/* descriptor pointer entry */
+
+struct sec1_talitos_ptr {
+ __be16 res;
+ __be16 len;
+ __be32 ptr;
+} __packed;
+
+struct sec2_talitos_ptr {
+ __be16 len;
+ u8 j_extent;
+ u8 eptr;
+ __be32 ptr;
+} __packed;
+
struct talitos_ptr {
union {
- struct { /* SEC2 format */
- __be16 len; /* length */
- u8 j_extent; /* jump to sg link table and/or extent*/
- u8 eptr; /* extended address */
- };
- struct { /* SEC1 format */
- __be16 res;
- __be16 len1; /* length */
- };
+ struct sec1_talitos_ptr sec1;
+ struct sec2_talitos_ptr sec2;
};
- __be32 ptr; /* address */
};
-/* descriptor */
+/* descriptor format */
+
+struct sec1_talitos_desc {
+ __be32 hdr;
+ struct sec1_talitos_ptr ptr[7];
+ __be32 next_desc;
+} __packed;
+
+struct sec2_talitos_desc {
+ __be32 hdr;
+ __be32 hdr_lo;
+ struct sec2_talitos_ptr ptr[7];
+} __packed;
+
struct talitos_desc {
- __be32 hdr; /* header high bits */
union {
- __be32 hdr_lo; /* header low bits */
- __be32 hdr1; /* header for SEC1 */
+ struct sec1_talitos_desc sec1;
+ struct sec2_talitos_desc sec2;
};
- struct talitos_ptr ptr[7]; /* ptr/len pair array */
- __be32 next_desc; /* next descriptor (SEC1) */
};
-#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
+#define TALITOS_DESC_SIZE sizeof(struct talitos_desc)
/*
* talitos_edesc - s/w-extended descriptor
@@ -148,6 +164,14 @@ struct talitos_ptr_ops {
unsigned short (*from_talitos_ptr_len)(struct talitos_ptr *ptr);
void (*to_talitos_ptr_ext_set)(struct talitos_ptr *ptr, u8 val);
void (*to_talitos_ptr_ext_or)(struct talitos_ptr *ptr, u8 val);
+ __be32 (*get_ptr_value)(struct talitos_ptr *ptr);
+};
+
+struct talitos_desc_ops {
+ void (*set_hdr)(struct talitos_desc *desc, __be32 val);
+ __be32 (*get_hdr)(struct talitos_desc *desc);
+ __be32 (*get_hdr_lo)(struct talitos_desc *desc);
+ struct talitos_ptr *(*get_ptr)(struct talitos_desc *desc, size_t idx);
};
struct talitos_ops {
@@ -194,6 +218,7 @@ struct talitos_private {
const struct talitos_ops *ops;
const struct talitos_ptr_ops *ptr_ops;
+ const struct talitos_desc_ops *desc_ops;
/* SEC Compatibility info */
unsigned long features;
@@ -225,6 +250,7 @@ struct talitos_private {
struct talitos_ctx {
struct device *dev;
const struct talitos_ptr_ops *ptr_ops;
+ const struct talitos_desc_ops *desc_ops;
int ch;
__be32 desc_hdr_template;
u8 key[TALITOS_MAX_KEY_SIZE];
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 28/29] crypto: talitos - Clean up includes in core driver file
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (26 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 27/29] crypto: talitos - Introduce per-SEC-version descriptor structures and ops Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
2026-05-28 9:08 ` [PATCH 29/29] crypto: talitos - Remove TALITOS_DESC_SIZE macro Paul Louvel
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Now that the crypto implementations have been moved into their own
translation units, the talitos core driver file no longer needs the
includes that were only required by the hash, skcipher, aead, and hwrng
code. Remove them, and drop duplicates already provided by talitos.h.
Also sort the remaining includes alphabetically.
---
drivers/crypto/talitos/talitos.c | 23 +++--------------------
1 file changed, 3 insertions(+), 20 deletions(-)
diff --git a/drivers/crypto/talitos/talitos.c b/drivers/crypto/talitos/talitos.c
index a032907e900f..43939a9cd9ce 100644
--- a/drivers/crypto/talitos/talitos.c
+++ b/drivers/crypto/talitos/talitos.c
@@ -12,32 +12,15 @@
* All rights reserved.
*/
+#include <linux/crypto.h>
+#include <linux/io.h>
#include <linux/kernel.h>
-#include <linux/module.h>
#include <linux/mod_devicetable.h>
-#include <linux/crypto.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-#include <linux/rtnetlink.h>
#include <linux/slab.h>
-#include <crypto/algapi.h>
-#include <crypto/aes.h>
-#include <crypto/internal/des.h>
-#include <crypto/sha1.h>
-#include <crypto/sha2.h>
-#include <crypto/md5.h>
-#include <crypto/internal/aead.h>
-#include <crypto/authenc.h>
-#include <crypto/internal/skcipher.h>
-#include <crypto/hash.h>
-#include <crypto/internal/hash.h>
-#include <crypto/scatterwalk.h>
-
#include "talitos.h"
/*
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 29/29] crypto: talitos - Remove TALITOS_DESC_SIZE macro
2026-05-28 9:08 [PATCH 00/29] crypto: talitos - Driver cleanup Paul Louvel
` (27 preceding siblings ...)
2026-05-28 9:08 ` [PATCH 28/29] crypto: talitos - Clean up includes in core driver file Paul Louvel
@ 2026-05-28 9:08 ` Paul Louvel
28 siblings, 0 replies; 36+ messages in thread
From: Paul Louvel @ 2026-05-28 9:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller
Cc: Thomas Petazzoni, Herve Codina, Christophe Leroy, linux-crypto,
linux-kernel, Paul Louvel
Now that struct talitos_desc no longer has the SEC1-only next_desc field
(it was moved into sec1_talitos_desc), TALITOS_DESC_SIZE is identical to
sizeof(struct talitos_desc) and no longer serves any purpose. Remove it
and use sizeof directly at each macro invocation.
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
---
drivers/crypto/talitos/talitos-sec1.c | 10 +++++-----
drivers/crypto/talitos/talitos-sec2.c | 6 +++---
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/crypto/talitos/talitos-sec1.c b/drivers/crypto/talitos/talitos-sec1.c
index e4f482520372..504ce9e23e59 100644
--- a/drivers/crypto/talitos/talitos-sec1.c
+++ b/drivers/crypto/talitos/talitos-sec1.c
@@ -190,7 +190,7 @@ static void sec1_dma_map_request(struct device *dev,
while (edesc) {
dma_desc = dma_map_single(dev, &edesc->desc.sec1.hdr,
- TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
+ sizeof(struct talitos_desc), DMA_BIDIRECTIONAL);
if (!prev_edesc) {
request->dma_desc = dma_desc;
@@ -202,7 +202,7 @@ static void sec1_dma_map_request(struct device *dev,
prev_edesc->desc.sec1.next_desc = cpu_to_be32(dma_desc);
dma_sync_single_for_device(dev, prev_dma_desc,
- TALITOS_DESC_SIZE, DMA_TO_DEVICE);
+ sizeof(struct talitos_desc), DMA_TO_DEVICE);
next:
prev_edesc = edesc;
@@ -216,12 +216,12 @@ static void sec1_dma_unmap_request(struct device *dev,
{
struct talitos_edesc *edesc;
- dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
+ dma_unmap_single(dev, request->dma_desc, sizeof(struct talitos_desc),
DMA_BIDIRECTIONAL);
edesc = container_of(request->desc, struct talitos_edesc, desc);
while (edesc->next_desc) {
dma_unmap_single(dev, be32_to_cpu(edesc->desc.sec1.next_desc),
- TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
+ sizeof(struct talitos_desc), DMA_BIDIRECTIONAL);
edesc = edesc->next_desc;
}
}
@@ -239,7 +239,7 @@ static __be32 sec1_get_request_hdr(struct device *dev,
edesc = edesc->next_desc;
}
- dma_sync_single_for_cpu(dev, dma_desc, TALITOS_DESC_SIZE,
+ dma_sync_single_for_cpu(dev, dma_desc, sizeof(struct talitos_desc),
DMA_BIDIRECTIONAL);
return edesc->desc.sec1.hdr;
diff --git a/drivers/crypto/talitos/talitos-sec2.c b/drivers/crypto/talitos/talitos-sec2.c
index 52f783ddc8b6..0df3b22510c7 100644
--- a/drivers/crypto/talitos/talitos-sec2.c
+++ b/drivers/crypto/talitos/talitos-sec2.c
@@ -205,7 +205,7 @@ static void sec2_dma_map_request(struct device *dev,
struct talitos_desc *desc)
{
request->dma_desc =
- dma_map_single(dev, desc, TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
+ dma_map_single(dev, desc, sizeof(struct talitos_desc), DMA_BIDIRECTIONAL);
}
static int sec2_talitos_handle_error(struct device *dev, u32 isr, u32 isr_lo)
@@ -346,14 +346,14 @@ static void sec2_init_task(struct device *dev)
static void sec2_dma_unmap_request(struct device *dev,
struct talitos_request *request)
{
- dma_unmap_single(dev, request->dma_desc, TALITOS_DESC_SIZE,
+ dma_unmap_single(dev, request->dma_desc, sizeof(struct talitos_desc),
DMA_BIDIRECTIONAL);
}
static __be32 sec2_get_request_hdr(struct device *dev,
struct talitos_request *request)
{
- dma_sync_single_for_cpu(dev, request->dma_desc, TALITOS_DESC_SIZE,
+ dma_sync_single_for_cpu(dev, request->dma_desc, sizeof(struct talitos_desc),
DMA_BIDIRECTIONAL);
return request->desc->sec2.hdr;
--
2.54.0
^ permalink raw reply related [flat|nested] 36+ messages in thread