From: Dave Jiang <dave.jiang@intel.com>
To: Terry Bowman <terry.bowman@amd.com>,
dave@stgolabs.net, jonathan.cameron@huawei.com,
alison.schofield@intel.com, dan.j.williams@intel.com,
bhelgaas@google.com, shiju.jose@huawei.com, ming.li@zohomail.com,
Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,
dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com,
lukas@wunner.de, Benjamin.Cheatham@amd.com,
sathyanarayanan.kuppuswamy@linux.intel.com,
linux-cxl@vger.kernel.org, vishal.l.verma@intel.com,
alucerop@amd.com, ira.weiny@intel.com
Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v14 20/34] cxl/port: Move dport operations to a driver event
Date: Wed, 14 Jan 2026 14:45:59 -0700 [thread overview]
Message-ID: <0490d2d1-9583-44d6-9a4b-115bdf36f98b@intel.com> (raw)
In-Reply-To: <20260114182055.46029-21-terry.bowman@amd.com>
On 1/14/26 11:20 AM, Terry Bowman wrote:
> From: Dan Williams <dan.j.williams@intel.com>
>
> In preparation for adding more register setup to the cxl_port_add_dport()
> path (for RAS register mapping), move the dport creation event to a driver
> callback. This achieves 2 things it puts driver operations logically where
> they belong, in a driver, and it obviates the gymnastics of
> DECLARE_TESTABLE() which just makes a mess of grepping for CXL symbols.
>
> In other words, a driver callback is less of an ongoing maintenance burden
> than this DECLARE_TESTABLE arrangement that does not scale and diminishes
> the grep-ability of the codebase.
>
> cxl_port_add_dport() moves mostly unmodified from drivers/cxl/core/port.c.
> The only deliberate change is that it now assumes that the device_lock is
> held on entry and the driver is attached (just like cxl_port_probe()).
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> Reviewed-by: Terry Bowman <terry.bowman@amd.com>
Missing sign off
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>
> ---
>
> Changes in v13 -> v14:
> - New patch
> ---
> drivers/cxl/core/hdm.c | 6 +--
> drivers/cxl/core/pci.c | 8 +--
> drivers/cxl/core/port.c | 79 ++++++----------------------
> drivers/cxl/cxl.h | 23 ++------
> drivers/cxl/port.c | 71 +++++++++++++++++++++++++
> tools/testing/cxl/Kbuild | 2 +
> tools/testing/cxl/cxl_core_exports.c | 21 --------
> tools/testing/cxl/exports.h | 13 -----
> tools/testing/cxl/test/mock.c | 23 +++-----
> 9 files changed, 107 insertions(+), 139 deletions(-)
> delete mode 100644 tools/testing/cxl/exports.h
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 1c5d2022c87a..365b02b7a241 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -1219,12 +1219,12 @@ static int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm,
> }
>
> /**
> - * __devm_cxl_switch_port_decoders_setup - allocate and setup switch decoders
> + * devm_cxl_switch_port_decoders_setup - allocate and setup switch decoders
> * @port: CXL port context
> *
> * Return 0 or -errno on error
> */
> -int __devm_cxl_switch_port_decoders_setup(struct cxl_port *port)
> +int devm_cxl_switch_port_decoders_setup(struct cxl_port *port)
> {
> struct cxl_hdm *cxlhdm;
>
> @@ -1248,7 +1248,7 @@ int __devm_cxl_switch_port_decoders_setup(struct cxl_port *port)
> dev_err(&port->dev, "HDM decoder capability not found\n");
> return -ENXIO;
> }
> -EXPORT_SYMBOL_NS_GPL(__devm_cxl_switch_port_decoders_setup, "CXL");
> +EXPORT_SYMBOL_NS_GPL(devm_cxl_switch_port_decoders_setup, "CXL");
>
> /**
> * devm_cxl_endpoint_decoders_setup - allocate and setup endpoint decoders
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 512a3e29a095..8633bfdef38d 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -41,14 +41,14 @@ static int pci_get_port_num(struct pci_dev *pdev)
> }
>
> /**
> - * __cxl_add_dport_by_dev - allocate a dport by dport device
> + * cxl_add_dport_by_dev - allocate a dport by dport device
> * @port: cxl_port that hosts the dport
> * @dport_dev: 'struct device' of the dport
> *
> * Returns the allocated dport on success or ERR_PTR() of -errno on error
> */
> -struct cxl_dport *__cxl_add_dport_by_dev(struct cxl_port *port,
> - struct device *dport_dev)
> +struct cxl_dport *cxl_add_dport_by_dev(struct cxl_port *port,
> + struct device *dport_dev)
> {
> struct cxl_register_map map;
> struct pci_dev *pdev;
> @@ -69,7 +69,7 @@ struct cxl_dport *__cxl_add_dport_by_dev(struct cxl_port *port,
> device_lock_assert(&port->dev);
> return cxl_add_dport(port, dport_dev, port_num, map.resource);
> }
> -EXPORT_SYMBOL_NS_GPL(__cxl_add_dport_by_dev, "CXL");
> +EXPORT_SYMBOL_NS_GPL(cxl_add_dport_by_dev, "CXL");
>
> struct cxl_walk_context {
> struct pci_bus *bus;
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index a05a1812bb6e..2184c20af011 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1603,78 +1603,31 @@ static int update_decoder_targets(struct device *dev, void *data)
> return 0;
> }
>
> -static struct cxl_port *cxl_port_devres_group(struct cxl_port *port)
> +void cxl_port_update_decoder_targets(struct cxl_port *port,
> + struct cxl_dport *dport)
> {
> - if (!devres_open_group(&port->dev, port, GFP_KERNEL))
> - return ERR_PTR(-ENOMEM);
> - return port;
> + device_for_each_child(&port->dev, dport, update_decoder_targets);
> }
> +EXPORT_SYMBOL_NS_GPL(cxl_port_update_decoder_targets, "CXL");
> +
> DEFINE_FREE(cxl_port_group_free, struct cxl_port *,
> if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->dev, _T))
>
> -static void cxl_port_group_close(struct cxl_port *port)
> -{
> - devres_remove_group(&port->dev, port);
> -}
> -
> -static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
> - struct device *dport_dev)
> +static struct cxl_dport *probe_dport(struct cxl_port *port,
> + struct device *dport_dev)
> {
> - struct cxl_dport *new_dport;
> - struct cxl_dport *dport;
> - int rc;
> + struct cxl_driver *drv;
>
> device_lock_assert(&port->dev);
> if (!port->dev.driver)
> return ERR_PTR(-ENXIO);
>
> - dport = cxl_find_dport_by_dev(port, dport_dev);
> - if (dport) {
> - dev_dbg(&port->dev, "dport%d:%s already exists\n",
> - dport->port_id, dev_name(dport_dev));
> - return ERR_PTR(-EBUSY);
> - }
> -
> - /*
> - * With the first dport arrival it is now safe to start looking at
> - * component registers. Be careful to not strand resources if dport
> - * creation ultimately fails.
> - */
> - struct cxl_port *port_group __free(cxl_port_group_free) =
> - cxl_port_devres_group(port);
> - if (IS_ERR(port_group))
> - return ERR_CAST(port_group);
> -
> - if (port->nr_dports == 0) {
> - rc = devm_cxl_switch_port_decoders_setup(port);
> - if (rc)
> - return ERR_PTR(rc);
> - /*
> - * Note, when nr_dports returns to zero the port is unregistered
> - * and triggers cleanup. I.e. no need for open-coded release
> - * action on dport removal. See cxl_detach_ep() for that logic.
> - */
> - }
> -
> - new_dport = cxl_add_dport_by_dev(port, dport_dev);
> - if (IS_ERR(new_dport))
> - return new_dport;
> -
> - rc = cxl_dport_autoremove(new_dport);
> - if (rc)
> - return ERR_PTR(rc);
> -
> - cxl_switch_parse_cdat(new_dport);
> -
> - cxl_port_group_close(no_free_ptr(port_group));
> -
> - dev_dbg(&port->dev, "dport[%d] id:%d dport_dev: %s added\n",
> - port->nr_dports - 1, new_dport->port_id, dev_name(dport_dev));
> -
> - /* New dport added, update the decoder targets */
> - device_for_each_child(&port->dev, new_dport, update_decoder_targets);
> + drv = container_of(port->dev.driver, struct cxl_driver, drv);
> + if (!drv->add_dport)
> + return ERR_PTR(-ENXIO);
>
> - return new_dport;
> + /* see cxl_port_add_dport() */
> + return drv->add_dport(port, dport_dev);
> }
>
> static struct cxl_dport *devm_cxl_create_port(struct device *ep_dev,
> @@ -1721,7 +1674,7 @@ static struct cxl_dport *devm_cxl_create_port(struct device *ep_dev,
> }
>
> guard(device)(&port->dev);
> - return cxl_port_add_dport(port, dport_dev);
> + return probe_dport(port, dport_dev);
> }
>
> static int add_port_attach_ep(struct cxl_memdev *cxlmd,
> @@ -1753,7 +1706,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd,
> scoped_guard(device, &parent_port->dev) {
> parent_dport = cxl_find_dport_by_dev(parent_port, dparent);
> if (!parent_dport) {
> - parent_dport = cxl_port_add_dport(parent_port, dparent);
> + parent_dport = probe_dport(parent_port, dparent);
> if (IS_ERR(parent_dport))
> return PTR_ERR(parent_dport);
> }
> @@ -1789,7 +1742,7 @@ static struct cxl_dport *find_or_add_dport(struct cxl_port *port,
> device_lock_assert(&port->dev);
> dport = cxl_find_dport_by_dev(port, dport_dev);
> if (!dport) {
> - dport = cxl_port_add_dport(port, dport_dev);
> + dport = probe_dport(port, dport_dev);
> if (IS_ERR(dport))
> return dport;
>
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 47ee06c95433..46491046f101 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -841,8 +841,9 @@ struct cxl_endpoint_dvsec_info {
> };
>
> int devm_cxl_switch_port_decoders_setup(struct cxl_port *port);
> -int __devm_cxl_switch_port_decoders_setup(struct cxl_port *port);
> int devm_cxl_endpoint_decoders_setup(struct cxl_port *port);
> +void cxl_port_update_decoder_targets(struct cxl_port *port,
> + struct cxl_dport *dport);
>
> struct cxl_dev_state;
> int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds,
> @@ -856,6 +857,8 @@ struct cxl_driver {
> const char *name;
> int (*probe)(struct device *dev);
> void (*remove)(struct device *dev);
> + struct cxl_dport *(*add_dport)(struct cxl_port *port,
> + struct device *dport_dev);
> struct device_driver drv;
> int id;
> };
> @@ -940,8 +943,6 @@ void cxl_coordinates_combine(struct access_coordinate *out,
> bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port);
> struct cxl_dport *cxl_add_dport_by_dev(struct cxl_port *port,
> struct device *dport_dev);
> -struct cxl_dport *__cxl_add_dport_by_dev(struct cxl_port *port,
> - struct device *dport_dev);
>
> /*
> * Unit test builds overrides this to __weak, find the 'strong' version
> @@ -953,20 +954,4 @@ struct cxl_dport *__cxl_add_dport_by_dev(struct cxl_port *port,
>
> u16 cxl_gpf_get_dvsec(struct device *dev);
>
> -/*
> - * Declaration for functions that are mocked by cxl_test that are called by
> - * cxl_core. The respective functions are defined as __foo() and called by
> - * cxl_core as foo(). The macros below ensures that those functions would
> - * exist as foo(). See tools/testing/cxl/cxl_core_exports.c and
> - * tools/testing/cxl/exports.h for setting up the mock functions. The dance
> - * is done to avoid a circular dependency where cxl_core calls a function that
> - * ends up being a mock function and goes to * cxl_test where it calls a
> - * cxl_core function.
> - */
> -#ifndef CXL_TEST_ENABLE
> -#define DECLARE_TESTABLE(x) __##x
> -#define cxl_add_dport_by_dev DECLARE_TESTABLE(cxl_add_dport_by_dev)
> -#define devm_cxl_switch_port_decoders_setup DECLARE_TESTABLE(devm_cxl_switch_port_decoders_setup)
> -#endif
> -
> #endif /* __CXL_H__ */
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 167cc0a87484..2770bc8520d3 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -155,9 +155,80 @@ static const struct attribute_group *cxl_port_attribute_groups[] = {
> NULL,
> };
>
> +static struct cxl_port *cxl_port_devres_group(struct cxl_port *port)
> +{
> + if (!devres_open_group(&port->dev, port, GFP_KERNEL))
> + return ERR_PTR(-ENOMEM);
> + return port;
> +}
> +DEFINE_FREE(cxl_port_group_free, struct cxl_port *,
> + if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->dev, _T))
> +
> +static void cxl_port_group_close(struct cxl_port *port)
> +{
> + devres_remove_group(&port->dev, port);
> +}
> +
> +static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
> + struct device *dport_dev)
> +{
> + struct cxl_dport *new_dport;
> + struct cxl_dport *dport;
> + int rc;
> +
> + dport = cxl_find_dport_by_dev(port, dport_dev);
> + if (dport) {
> + dev_dbg(&port->dev, "dport%d:%s already exists\n",
> + dport->port_id, dev_name(dport_dev));
> + return ERR_PTR(-EBUSY);
> + }
> +
> + /*
> + * With the first dport arrival it is now safe to start looking at
> + * component registers. Be careful to not strand resources if dport
> + * creation ultimately fails.
> + */
> + struct cxl_port *port_group __free(cxl_port_group_free) =
> + cxl_port_devres_group(port);
> + if (IS_ERR(port_group))
> + return ERR_CAST(port_group);
> +
> + if (port->nr_dports == 0) {
> + rc = devm_cxl_switch_port_decoders_setup(port);
> + if (rc)
> + return ERR_PTR(rc);
> + /*
> + * Note, when nr_dports returns to zero the port is unregistered
> + * and triggers cleanup. I.e. no need for open-coded release
> + * action on dport removal. See cxl_detach_ep() for that logic.
> + */
> + }
> +
> + new_dport = cxl_add_dport_by_dev(port, dport_dev);
> + if (IS_ERR(new_dport))
> + return new_dport;
> +
> + rc = cxl_dport_autoremove(new_dport);
> + if (rc)
> + return ERR_PTR(rc);
> +
> + cxl_switch_parse_cdat(new_dport);
> +
> + cxl_port_group_close(no_free_ptr(port_group));
> +
> + dev_dbg(&port->dev, "dport[%d] id:%d dport_dev: %s added\n",
> + port->nr_dports - 1, new_dport->port_id, dev_name(dport_dev));
> +
> + /* New dport added, update the decoder targets */
> + cxl_port_update_decoder_targets(port, new_dport);
> +
> + return new_dport;
> +}
> +
> static struct cxl_driver cxl_port_driver = {
> .name = "cxl_port",
> .probe = cxl_port_probe,
> + .add_dport = cxl_port_add_dport,
> .id = CXL_DEVICE_PORT,
> .drv = {
> .dev_groups = cxl_port_attribute_groups,
> diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild
> index 4d740392aac5..25516728535e 100644
> --- a/tools/testing/cxl/Kbuild
> +++ b/tools/testing/cxl/Kbuild
> @@ -11,6 +11,8 @@ ldflags-y += --wrap=cxl_endpoint_parse_cdat
> ldflags-y += --wrap=cxl_dport_init_ras_reporting
> ldflags-y += --wrap=devm_cxl_endpoint_decoders_setup
> ldflags-y += --wrap=hmat_get_extended_linear_cache_size
> +ldflags-y += --wrap=cxl_add_dport_by_dev
> +ldflags-y += --wrap=devm_cxl_switch_port_decoders_setup
>
> DRIVERS := ../../../drivers
> CXL_SRC := $(DRIVERS)/cxl
> diff --git a/tools/testing/cxl/cxl_core_exports.c b/tools/testing/cxl/cxl_core_exports.c
> index 02d479867a12..f088792a8925 100644
> --- a/tools/testing/cxl/cxl_core_exports.c
> +++ b/tools/testing/cxl/cxl_core_exports.c
> @@ -2,27 +2,6 @@
> /* Copyright(c) 2022 Intel Corporation. All rights reserved. */
>
> #include "cxl.h"
> -#include "exports.h"
>
> /* Exporting of cxl_core symbols that are only used by cxl_test */
> EXPORT_SYMBOL_NS_GPL(cxl_num_decoders_committed, "CXL");
> -
> -cxl_add_dport_by_dev_fn _cxl_add_dport_by_dev = __cxl_add_dport_by_dev;
> -EXPORT_SYMBOL_NS_GPL(_cxl_add_dport_by_dev, "CXL");
> -
> -struct cxl_dport *cxl_add_dport_by_dev(struct cxl_port *port,
> - struct device *dport_dev)
> -{
> - return _cxl_add_dport_by_dev(port, dport_dev);
> -}
> -EXPORT_SYMBOL_NS_GPL(cxl_add_dport_by_dev, "CXL");
> -
> -cxl_switch_decoders_setup_fn _devm_cxl_switch_port_decoders_setup =
> - __devm_cxl_switch_port_decoders_setup;
> -EXPORT_SYMBOL_NS_GPL(_devm_cxl_switch_port_decoders_setup, "CXL");
> -
> -int devm_cxl_switch_port_decoders_setup(struct cxl_port *port)
> -{
> - return _devm_cxl_switch_port_decoders_setup(port);
> -}
> -EXPORT_SYMBOL_NS_GPL(devm_cxl_switch_port_decoders_setup, "CXL");
> diff --git a/tools/testing/cxl/exports.h b/tools/testing/cxl/exports.h
> deleted file mode 100644
> index cbb16073be18..000000000000
> --- a/tools/testing/cxl/exports.h
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -/* Copyright(c) 2025 Intel Corporation */
> -#ifndef __MOCK_CXL_EXPORTS_H_
> -#define __MOCK_CXL_EXPORTS_H_
> -
> -typedef struct cxl_dport *(*cxl_add_dport_by_dev_fn)(struct cxl_port *port,
> - struct device *dport_dev);
> -extern cxl_add_dport_by_dev_fn _cxl_add_dport_by_dev;
> -
> -typedef int(*cxl_switch_decoders_setup_fn)(struct cxl_port *port);
> -extern cxl_switch_decoders_setup_fn _devm_cxl_switch_port_decoders_setup;
> -
> -#endif
> diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c
> index 660e8402189c..10140a4c5fac 100644
> --- a/tools/testing/cxl/test/mock.c
> +++ b/tools/testing/cxl/test/mock.c
> @@ -10,20 +10,12 @@
> #include <cxlmem.h>
> #include <cxlpci.h>
> #include "mock.h"
> -#include "../exports.h"
>
> static LIST_HEAD(mock);
>
> -static struct cxl_dport *
> -redirect_cxl_add_dport_by_dev(struct cxl_port *port, struct device *dport_dev);
> -static int redirect_devm_cxl_switch_port_decoders_setup(struct cxl_port *port);
> -
> void register_cxl_mock_ops(struct cxl_mock_ops *ops)
> {
> list_add_rcu(&ops->list, &mock);
> - _cxl_add_dport_by_dev = redirect_cxl_add_dport_by_dev;
> - _devm_cxl_switch_port_decoders_setup =
> - redirect_devm_cxl_switch_port_decoders_setup;
> }
> EXPORT_SYMBOL_GPL(register_cxl_mock_ops);
>
> @@ -31,9 +23,6 @@ DEFINE_STATIC_SRCU(cxl_mock_srcu);
>
> void unregister_cxl_mock_ops(struct cxl_mock_ops *ops)
> {
> - _devm_cxl_switch_port_decoders_setup =
> - __devm_cxl_switch_port_decoders_setup;
> - _cxl_add_dport_by_dev = __cxl_add_dport_by_dev;
> list_del_rcu(&ops->list);
> synchronize_srcu(&cxl_mock_srcu);
> }
> @@ -162,7 +151,7 @@ __wrap_nvdimm_bus_register(struct device *dev,
> }
> EXPORT_SYMBOL_GPL(__wrap_nvdimm_bus_register);
>
> -int redirect_devm_cxl_switch_port_decoders_setup(struct cxl_port *port)
> +int __wrap_devm_cxl_switch_port_decoders_setup(struct cxl_port *port)
> {
> int rc, index;
> struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
> @@ -170,11 +159,12 @@ int redirect_devm_cxl_switch_port_decoders_setup(struct cxl_port *port)
> if (ops && ops->is_mock_port(port->uport_dev))
> rc = ops->devm_cxl_switch_port_decoders_setup(port);
> else
> - rc = __devm_cxl_switch_port_decoders_setup(port);
> + rc = devm_cxl_switch_port_decoders_setup(port);
> put_cxl_mock_ops(index);
>
> return rc;
> }
> +EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_switch_port_decoders_setup, "CXL");
>
> int __wrap_devm_cxl_endpoint_decoders_setup(struct cxl_port *port)
> {
> @@ -256,8 +246,8 @@ void __wrap_cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device
> }
> EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dport_init_ras_reporting, "CXL");
>
> -struct cxl_dport *redirect_cxl_add_dport_by_dev(struct cxl_port *port,
> - struct device *dport_dev)
> +struct cxl_dport *__wrap_cxl_add_dport_by_dev(struct cxl_port *port,
> + struct device *dport_dev)
> {
> int index;
> struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
> @@ -266,11 +256,12 @@ struct cxl_dport *redirect_cxl_add_dport_by_dev(struct cxl_port *port,
> if (ops && ops->is_mock_port(port->uport_dev))
> dport = ops->cxl_add_dport_by_dev(port, dport_dev);
> else
> - dport = __cxl_add_dport_by_dev(port, dport_dev);
> + dport = cxl_add_dport_by_dev(port, dport_dev);
> put_cxl_mock_ops(index);
>
> return dport;
> }
> +EXPORT_SYMBOL_NS_GPL(__wrap_cxl_add_dport_by_dev, "CXL");
>
> MODULE_LICENSE("GPL v2");
> MODULE_DESCRIPTION("cxl_test: emulation module");
next prev parent reply other threads:[~2026-01-14 21:46 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-14 18:20 [PATCH v14 00/34] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-01-14 18:20 ` [PATCH v14 01/34] PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Terry Bowman
2026-01-22 18:58 ` Bjorn Helgaas
2026-01-22 19:43 ` Bowman, Terry
2026-01-14 18:20 ` [PATCH v14 02/34] PCI: Update CXL DVSEC definitions Terry Bowman
2026-01-14 18:53 ` Jonathan Cameron
2026-01-19 23:44 ` dan.j.williams
2026-01-22 18:37 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 03/34] PCI: Introduce pcie_is_cxl() Terry Bowman
2026-01-21 1:19 ` dan.j.williams
2026-01-22 18:39 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 04/34] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2026-01-14 18:20 ` [PATCH v14 05/34] cxl/pci: Remove unnecessary CXL RCH " Terry Bowman
2026-01-14 18:20 ` [PATCH v14 06/34] PCI: Replace cxl_error_is_native() with pcie_aer_is_native() Terry Bowman
2026-01-14 18:55 ` Jonathan Cameron
2026-01-14 20:16 ` Dave Jiang
2026-01-14 20:15 ` Dave Jiang
2026-01-22 18:23 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 07/34] cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c Terry Bowman
2026-01-14 20:51 ` Dave Jiang
2026-01-14 18:20 ` [PATCH v14 08/34] cxl/pci: Move CXL driver's RCH error handling into core/ras_rch.c Terry Bowman
2026-01-14 20:35 ` Dave Jiang
2026-01-14 18:20 ` [PATCH v14 09/34] PCI/AER: Export pci_aer_unmask_internal_errors() Terry Bowman
2026-01-14 19:01 ` Jonathan Cameron
2026-01-14 19:09 ` Kuppuswamy Sathyanarayanan
2026-01-14 20:40 ` Dave Jiang
2026-01-20 2:09 ` dan.j.williams
2026-01-22 10:31 ` Lukas Wunner
2026-01-22 16:48 ` dan.j.williams
2026-01-22 18:51 ` Lukas Wunner
2026-01-22 18:49 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 10/34] PCI/AER: Update is_internal_error() to be non-static is_aer_internal_error() Terry Bowman
2026-01-14 19:08 ` Jonathan Cameron
2026-01-15 20:42 ` dan.j.williams
2026-01-22 13:34 ` Lukas Wunner
2026-01-22 19:09 ` dan.j.williams
2026-01-22 19:32 ` Lukas Wunner
2026-01-22 21:32 ` dan.j.williams
2026-01-23 12:22 ` Jonathan Cameron
2026-01-20 2:20 ` dan.j.williams
2026-01-20 15:15 ` Bowman, Terry
2026-01-20 16:53 ` dan.j.williams
2026-01-22 18:48 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 11/34] PCI/AER: Move CXL RCH error handling to aer_cxl_rch.c Terry Bowman
2026-01-22 17:23 ` Markus Elfring
2026-01-22 20:05 ` Bowman, Terry
2026-01-22 18:53 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 12/34] PCI/AER: Use guard() in cxl_rch_handle_error_iter() Terry Bowman
2026-01-14 19:11 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 13/34] PCI/AER: Replace PCIEAER_CXL symbol with CXL_RAS Terry Bowman
2026-01-14 19:12 ` Jonathan Cameron
2026-01-14 20:49 ` Dave Jiang
2026-01-14 20:50 ` Dave Jiang
2026-01-22 18:24 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 14/34] PCI/AER: Report CXL or PCIe bus type in AER trace logging Terry Bowman
2026-01-14 19:45 ` Jonathan Cameron
2026-01-15 15:55 ` Mauro Carvalho Chehab
2026-01-14 20:56 ` Dave Jiang
2026-01-14 18:20 ` [PATCH v14 15/34] PCI/AER: Update struct aer_err_info with kernel-doc formatting Terry Bowman
2026-01-14 19:48 ` Jonathan Cameron
2026-01-15 20:56 ` dan.j.williams
2026-01-14 21:06 ` Dave Jiang
2026-01-22 18:29 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 16/34] cxl/mem: Clarify @host for devm_cxl_add_nvdimm() Terry Bowman
2026-01-14 19:49 ` Jonathan Cameron
2026-01-14 21:08 ` Dave Jiang
2026-01-16 3:07 ` dan.j.williams
2026-01-16 16:22 ` Dave Jiang
2026-01-14 18:20 ` [PATCH v14 17/34] cxl: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2026-01-14 18:20 ` [PATCH v14 18/34] cxl/port: Remove "enumerate dports" helpers Terry Bowman
2026-01-14 19:50 ` Jonathan Cameron
2026-01-14 21:23 ` Dave Jiang
2026-01-16 3:15 ` dan.j.williams
2026-01-14 21:24 ` Dave Jiang
2026-01-16 3:21 ` dan.j.williams
2026-01-14 18:20 ` [PATCH v14 19/34] cxl/port: Fix devm resource leaks around with dport management Terry Bowman
2026-01-14 21:26 ` Dave Jiang
2026-01-15 14:46 ` Jonathan Cameron
2026-01-16 4:45 ` dan.j.williams
2026-01-16 15:01 ` Jonathan Cameron
2026-01-16 16:16 ` Jonathan Cameron
2026-01-19 23:02 ` dan.j.williams
2026-01-20 12:25 ` Jonathan Cameron
2026-01-19 2:48 ` dan.j.williams
2026-01-14 18:20 ` [PATCH v14 20/34] cxl/port: Move dport operations to a driver event Terry Bowman
2026-01-14 21:45 ` Dave Jiang [this message]
2026-01-15 14:56 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 21/34] cxl/port: Move dport RAS reporting to a port resource Terry Bowman
2026-01-14 21:47 ` Dave Jiang
2026-01-15 15:02 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 22/34] cxl: Update CXL Endpoint tracing Terry Bowman
2026-01-14 18:20 ` [PATCH v14 23/34] cxl: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2026-01-14 21:53 ` Dave Jiang
2026-01-15 15:17 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 24/34] cxl/port: Move endpoint component register management to cxl_port Terry Bowman
2026-01-14 21:55 ` Dave Jiang
2026-01-15 15:28 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 25/34] cxl/port: Map Port component registers before switchport init Terry Bowman
2026-01-14 21:59 ` Dave Jiang
2026-01-15 15:30 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 26/34] cxl: Change CXL handlers to use guard() instead of scoped_guard() Terry Bowman
2026-01-23 10:05 ` Markus Elfring
2026-01-14 18:20 ` [PATCH v14 27/34] PCI/ERR: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2026-01-14 18:58 ` Kuppuswamy Sathyanarayanan
2026-01-14 19:20 ` Bowman, Terry
2026-01-14 19:45 ` Kuppuswamy Sathyanarayanan
2026-01-14 18:20 ` [PATCH v14 28/34] PCI/AER: Move AER driver's CXL VH handling to pcie/aer_cxl_vh.c Terry Bowman
2026-01-15 15:40 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 29/34] cxl/port: Unify endpoint and switch port lookup Terry Bowman
2026-01-14 23:04 ` Dave Jiang
2026-01-15 15:44 ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 30/34] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2026-01-14 23:18 ` Dave Jiang
2026-01-16 14:42 ` Bowman, Terry
2026-01-15 16:01 ` Jonathan Cameron
2026-01-15 17:29 ` Bowman, Terry
2026-01-22 18:32 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 31/34] PCI: Introduce CXL Port protocol error handlers Terry Bowman
2026-01-14 23:37 ` Dave Jiang
2026-01-15 16:12 ` Jonathan Cameron
2026-01-22 18:27 ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 32/34] cxl: Update Endpoint uncorrectable protocol error handling Terry Bowman
2026-01-14 22:07 ` dan.j.williams
2026-01-15 15:26 ` Bowman, Terry
2026-01-15 15:27 ` Bowman, Terry
2026-01-14 18:20 ` [PATCH v14 33/34] cxl: Update Endpoint correctable " Terry Bowman
2026-01-14 18:20 ` [PATCH v14 34/34] cxl: Enable CXL protocol errors during CXL Port probe Terry Bowman
2026-01-15 16:18 ` Jonathan Cameron
2026-01-15 19:41 ` Bowman, Terry
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