Re: [PATCH v14 21/34] cxl/port: Move dport RAS reporting to a port resource

[Dave Jiang <dave.jiang@intel.com>]

On 1/14/26 11:20 AM, Terry Bowman wrote:
> From: Dan Williams <dan.j.williams@intel.com>
> 
> Towards the end goal of making all CXL RAS capability handling uniform
> across upstream host bridges, upstream switch ports, and upstream endpoint
> ports, move dport RAS setup to cxl_endpoint_port_probe(). Rename the RAS
> setup helper to devm_cxl_dport_ras_setup() for symmetry with
> devm_cxl_switch_port_decoders_setup().
> 
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> Reviewed-by: Terry Bowman <terry.bowman@amd.com>

missing sign off tag

Reviewed-by: Dave Jiang <dave.jiang@intel.com>

> 
> ---
> 
> Changes in v13 -> v14:
> - New patch
> ---
>  drivers/cxl/core/ras.c        | 12 ++++++------
>  drivers/cxl/cxlpci.h          |  8 ++++----
>  drivers/cxl/mem.c             |  2 --
>  drivers/cxl/port.c            | 12 ++++++++++++
>  tools/testing/cxl/Kbuild      |  2 +-
>  tools/testing/cxl/test/mock.c |  6 +++---
>  6 files changed, 26 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
> index 72908f3ced77..d71fcac31cf2 100644
> --- a/drivers/cxl/core/ras.c
> +++ b/drivers/cxl/core/ras.c
> @@ -139,17 +139,17 @@ static void cxl_dport_map_ras(struct cxl_dport *dport)
>  }
>  
>  /**
> - * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport
> + * devm_cxl_dport_ras_setup - Setup CXL RAS report on this dport
>   * @dport: the cxl_dport that needs to be initialized
> - * @host: host device for devm operations
>   */
> -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)
> +void devm_cxl_dport_ras_setup(struct cxl_dport *dport)
>  {
> -	dport->reg_map.host = host;
> +	dport->reg_map.host = &dport->port->dev;
>  	cxl_dport_map_ras(dport);
>  
>  	if (dport->rch) {
> -		struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport->dport_dev);
> +		struct pci_host_bridge *host_bridge =
> +			to_pci_host_bridge(dport->dport_dev);
>  
>  		if (!host_bridge->native_aer)
>  			return;
> @@ -158,7 +158,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)
>  		cxl_disable_rch_root_ints(dport);
>  	}
>  }
> -EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL");
> +EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_ras_setup, "CXL");
>  
>  void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)
>  {
> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index 6f9c78886fd9..e41bb93d583a 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -81,7 +81,7 @@ void read_cdat_data(struct cxl_port *port);
>  void cxl_cor_error_detected(struct pci_dev *pdev);
>  pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
>  				    pci_channel_state_t state);
> -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host);
> +void devm_cxl_dport_ras_setup(struct cxl_dport *dport);
>  #else
>  static inline void cxl_cor_error_detected(struct pci_dev *pdev) { }
>  
> @@ -90,9 +90,9 @@ static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
>  {
>  	return PCI_ERS_RESULT_NONE;
>  }
> -
> -static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport,
> -						struct device *host) { }
> +static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport)
> +{
> +}
>  #endif
>  
>  #endif /* __CXL_PCI_H__ */
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index c2ee7f7f6320..e25c33f8c6cf 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -166,8 +166,6 @@ static int cxl_mem_probe(struct device *dev)
>  	else
>  		endpoint_parent = &parent_port->dev;
>  
> -	cxl_dport_init_ras_reporting(dport, dev);
> -
>  	scoped_guard(device, endpoint_parent) {
>  		if (!endpoint_parent->driver) {
>  			dev_err(dev, "CXL port topology %s not enabled\n",
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index 2770bc8520d3..8f8fc98c1428 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -75,6 +75,7 @@ static int cxl_switch_port_probe(struct cxl_port *port)
>  static int cxl_endpoint_port_probe(struct cxl_port *port)
>  {
>  	struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
> +	struct cxl_dport *dport = port->parent_dport;
>  	int rc;
>  
>  	/* Cache the data early to ensure is_visible() works */
> @@ -90,6 +91,17 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
>  	if (rc)
>  		return rc;
>  
> +	/*
> +	 * With VH (CXL Virtual Host) topology the cxl_port::add_dport() method
> +	 * handles RAS setup for downstream ports. With RCH (CXL Restricted CXL
> +	 * Host) topologies the downstream port is enumerated early by platform
> +	 * firmware, but the RCRB (root complex register block) is not mapped
> +	 * until after the cxl_pci driver attaches to the RCIeP (root complex
> +	 * integrated endpoint).
> +	 */
> +	if (dport->rch)
> +		devm_cxl_dport_ras_setup(dport);
> +
>  	/*
>  	 * Now that all endpoint decoders are successfully enumerated, try to
>  	 * assemble regions from committed decoders
> diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild
> index 25516728535e..7250bedf0448 100644
> --- a/tools/testing/cxl/Kbuild
> +++ b/tools/testing/cxl/Kbuild
> @@ -8,7 +8,7 @@ ldflags-y += --wrap=cxl_await_media_ready
>  ldflags-y += --wrap=cxl_add_rch_dport
>  ldflags-y += --wrap=cxl_rcd_component_reg_phys
>  ldflags-y += --wrap=cxl_endpoint_parse_cdat
> -ldflags-y += --wrap=cxl_dport_init_ras_reporting
> +ldflags-y += --wrap=devm_cxl_dport_ras_setup
>  ldflags-y += --wrap=devm_cxl_endpoint_decoders_setup
>  ldflags-y += --wrap=hmat_get_extended_linear_cache_size
>  ldflags-y += --wrap=cxl_add_dport_by_dev
> diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c
> index 10140a4c5fac..8883357ee50d 100644
> --- a/tools/testing/cxl/test/mock.c
> +++ b/tools/testing/cxl/test/mock.c
> @@ -234,17 +234,17 @@ void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port)
>  }
>  EXPORT_SYMBOL_NS_GPL(__wrap_cxl_endpoint_parse_cdat, "CXL");
>  
> -void __wrap_cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)
> +void __wrap_devm_cxl_dport_ras_setup(struct cxl_dport *dport)
>  {
>  	int index;
>  	struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
>  
>  	if (!ops || !ops->is_mock_port(dport->dport_dev))
> -		cxl_dport_init_ras_reporting(dport, host);
> +		devm_cxl_dport_ras_setup(dport);
>  
>  	put_cxl_mock_ops(index);
>  }
> -EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dport_init_ras_reporting, "CXL");
> +EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_dport_ras_setup, "CXL");
>  
>  struct cxl_dport *__wrap_cxl_add_dport_by_dev(struct cxl_port *port,
>  					      struct device *dport_dev)