[PATCH v14 33/34] cxl: Update Endpoint correctable protocol error handling

[Terry Bowman <terry.bowman@amd.com>]

The CXL drivers must support handling Endpoint CXL and PCI correctable
(CE) protocol errors. Update the driver to support both.

Introduce cxl_pci_cor_error_detected() to handle PCI correctable errors,
replacing cxl_cor_error_detected(). Implement this new function to call
the existing CXL correctable handler, cxl_port_cor_error_detected().

Update cxl_port_cor_error_detected() for correct Endpoint handling.
Take the CXL memory device lock, check for a valid driver, and handle
Restricted CXL Device (RCD) if needed.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>

---

Changes in v13->v14:
- New commit
- Change cxl_cor_error_detected() parameter to &pdev->dev device from
  memdev device. (Terry)
- Updated commit message (Terry)
---
 drivers/cxl/core/ras.c | 52 ++++++++++++++++++++++++++----------------
 drivers/cxl/cxlpci.h   |  6 +++--
 drivers/cxl/pci.c      |  2 +-
 3 files changed, 37 insertions(+), 23 deletions(-)

diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index dc6e02d64821..427009a8a78a 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -267,8 +267,10 @@ void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base)
 	void __iomem *addr;
 	u32 status;
 
-	if (!ras_base)
+	if (!ras_base) {
+		dev_warn_once(dev, "CXL RAS register block is not mapped");
 		return;
+	}
 
 	addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
 	status = readl(addr);
@@ -345,7 +347,30 @@ pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ra
 
 static void cxl_port_cor_error_detected(struct device *dev)
 {
-	cxl_handle_cor_ras(dev, 0, cxl_get_ras_base(dev));
+	struct pci_dev *pdev = to_pci_dev(dev);
+	struct cxl_port *port __free(put_cxl_port) = get_cxl_port(pdev);
+	u64 serial = 0;
+
+	if (is_cxl_endpoint(port)) {
+		struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
+		struct cxl_dev_state *cxlds = cxlmd->cxlds;
+
+		guard(device)(&cxlmd->dev);
+
+		if (!dev->driver) {
+			dev_warn(&pdev->dev,
+				 "%s: memdev disabled, abort error handling\n",
+				 dev_name(dev));
+			return;
+		}
+
+		if (cxlds->rcd)
+			cxl_handle_rdport_errors(cxlds);
+
+		serial = cxlds->serial;
+	}
+
+	cxl_handle_cor_ras(dev, serial, cxl_get_ras_base(dev));
 }
 
 static pci_ers_result_t cxl_port_error_detected(struct device *dev)
@@ -376,28 +401,15 @@ static pci_ers_result_t cxl_port_error_detected(struct device *dev)
 	return cxl_handle_ras(dev, serial, cxl_get_ras_base(dev));
 }
 
-void cxl_cor_error_detected(struct pci_dev *pdev)
+void cxl_pci_cor_error_detected(struct pci_dev *pdev)
 {
-	struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
-	struct cxl_memdev *cxlmd = cxlds->cxlmd;
-	struct device *dev = &cxlds->cxlmd->dev;
-
-	guard(device)(dev);
-
-	if (!dev->driver) {
-		dev_warn(&pdev->dev,
-			 "%s: memdev disabled, abort error handling\n",
-			 dev_name(dev));
-		return;
-	}
+	struct cxl_port *port __free(put_cxl_port) = get_cxl_port(pdev);
 
-	if (cxlds->rcd)
-		cxl_handle_rdport_errors(cxlds);
+	guard(device)(&port->dev);
 
-	cxl_handle_cor_ras(&cxlmd->dev, cxlds->serial,
-			   cxlmd->endpoint->regs.ras);
+	cxl_port_cor_error_detected(&pdev->dev);
 }
-EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL");
+EXPORT_SYMBOL_NS_GPL(cxl_pci_cor_error_detected, "CXL");
 
 pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
 					pci_channel_state_t error)
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index f218b343e179..3d70f9b4a193 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -78,7 +78,7 @@ struct cxl_dev_state;
 void read_cdat_data(struct cxl_port *port);
 
 #ifdef CONFIG_CXL_RAS
-void cxl_cor_error_detected(struct pci_dev *pdev);
+void cxl_pci_cor_error_detected(struct pci_dev *pdev);
 pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
 					pci_channel_state_t error);
 void devm_cxl_dport_ras_setup(struct cxl_dport *dport);
@@ -90,7 +90,9 @@ int __cxl_await_media_ready(struct cxl_dev_state *cxlds);
 resource_size_t __cxl_rcd_component_reg_phys(struct device *dev,
 					     struct cxl_dport *dport);
 #else
-static inline void cxl_cor_error_detected(struct pci_dev *pdev) { }
+static inline void cxl_pci_cor_error_detected(struct pci_dev *pdev)
+{
+}
 static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
 						      pci_channel_state_t state)
 {
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index ff741adc7c7f..328b4ea8dbc5 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -1055,7 +1055,7 @@ static const struct pci_error_handlers pci_error_handlers = {
 	.error_detected	= cxl_pci_error_detected,
 	.slot_reset	= cxl_slot_reset,
 	.resume		= cxl_error_resume,
-	.cor_error_detected	= cxl_cor_error_detected,
+	.cor_error_detected	= cxl_pci_cor_error_detected,
 	.reset_done	= cxl_reset_done,
 };
 
-- 
2.34.1