From: Neeraj Kumar <s.neeraj@samsung.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev,
linux-kernel@vger.kernel.org, gost.dev@samsung.com,
a.manzanares@samsung.com, vishak.g@samsung.com,
neeraj.kernel@gmail.com, cpgs@samsung.com
Subject: Re: [PATCH V2 01/20] nvdimm/label: Introduce NDD_CXL_LABEL flag to set cxl label format
Date: Thu, 4 Sep 2025 18:54:07 +0530 [thread overview]
Message-ID: <1983025922.01757055603347.JavaMail.epsvc@epcpadp1new> (raw)
In-Reply-To: <7ff8b51b-7263-4d9c-99f8-1b507cf46262@intel.com>
[-- Attachment #1: Type: text/plain, Size: 3478 bytes --]
On 15/08/25 11:06AM, Dave Jiang wrote:
>
>
>On 8/13/25 6:12 AM, Jonathan Cameron wrote:
>> On Wed, 30 Jul 2025 17:41:50 +0530
>> Neeraj Kumar <s.neeraj@samsung.com> wrote:
>>
>>> Prior to LSA 2.1 version, LSA contain only namespace labels. LSA 2.1
>>> introduced in CXL 2.0 Spec, which contain region label along with
>>> namespace label.
>>>
>>> NDD_LABELING flag is used for namespace. Introduced NDD_CXL_LABEL
>>> flag for region label. Based on these flags nvdimm driver performs
>>> operation on namespace label or region label.
>>>
>>> NDD_CXL_LABEL will be utilized by cxl driver to enable LSA2.1 region
>>> label support
>>>
>>> Accordingly updated label index version
>>>
>>> Signed-off-by: Neeraj Kumar <s.neeraj@samsung.com>
>> Hi Neeraj,
>>
>> A few comments inline.
>>
>>> diff --git a/drivers/nvdimm/label.c b/drivers/nvdimm/label.c
>>> index 04f4a049599a..7a011ee02d79 100644
>>> --- a/drivers/nvdimm/label.c
>>> +++ b/drivers/nvdimm/label.c
>>> @@ -688,11 +688,25 @@ static int nd_label_write_index(struct nvdimm_drvdata *ndd, int index, u32 seq,
>>> - (unsigned long) to_namespace_index(ndd, 0);
>>> nsindex->labeloff = __cpu_to_le64(offset);
>>> nsindex->nslot = __cpu_to_le32(nslot);
>>> - nsindex->major = __cpu_to_le16(1);
>>> - if (sizeof_namespace_label(ndd) < 256)
>>> +
>>> + /* Set LSA Label Index Version */
>>> + if (ndd->cxl) {
>>> + /* CXL r3.2 Spec: Table 9-9 Label Index Block Layout */
>>> + nsindex->major = __cpu_to_le16(2);
>>> nsindex->minor = __cpu_to_le16(1);
>>> - else
>>> - nsindex->minor = __cpu_to_le16(2);
>>> + } else {
>>> + nsindex->major = __cpu_to_le16(1);
>>> + /*
>>> + * NVDIMM Namespace Specification
>>> + * Table 2: Namespace Label Index Block Fields
>>> + */
>>> + if (sizeof_namespace_label(ndd) < 256)
>>> + nsindex->minor = __cpu_to_le16(1);
>>> + else
>>> + /* UEFI Specification 2.7: Label Index Block Definitions */
>>
>> Odd comment alignment. Either put it on the else so
>> else /* UEFI 2.7: Label Index Block Defintions */
>>
>> or indent it an extra tab
>>
>> else
>> /* UEFI 2.7: Label Index Block Definitions */
>>
>>> + nsindex->minor = __cpu_to_le16(2);
>>> + }
>>> +
>>> nsindex->checksum = __cpu_to_le64(0);
>>> if (flags & ND_NSINDEX_INIT) {
>>> unsigned long *free = (unsigned long *) nsindex->free;
>>
>>> diff --git a/include/linux/libnvdimm.h b/include/linux/libnvdimm.h
>>> index e772aae71843..0a55900842c8 100644
>>> --- a/include/linux/libnvdimm.h
>>> +++ b/include/linux/libnvdimm.h
>>> @@ -44,6 +44,9 @@ enum {
>>> /* dimm provider wants synchronous registration by __nvdimm_create() */
>>> NDD_REGISTER_SYNC = 8,
>>>
>>> + /* dimm supports region labels (LSA Format 2.1) */
>>> + NDD_CXL_LABEL = 9,
>>
>> This enum is 'curious'. It combined flags from a bunch of different
>> flags fields and some stuff that are nothing to do with flags.
>>
>> Anyhow, putting that aside I'd either rename it to something like
>> NDD_REGION_LABELING (similar to NDD_LABELING that is there for namespace labels
>> or just have it a meaning it is LSA Format 2.1 and drop the fact htat
>> also means region labels are supported.
>
>I agree. I had a conversation with Dan about it where I mentioned calling it CXL to describe LSA 2.1 just doesn't seem quite right. He also offered up something like NDD_REGION_LABELING instead of NDD_CXL_LABEL. So +1 to this comment.
>
>DJ
Sure Dave, I will rename it to NDD_REGION_LABELING in next patch-set
Regards,
Neeraj
[-- Attachment #2: Type: text/plain, Size: 0 bytes --]
next prev parent reply other threads:[~2025-09-05 7:00 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250730121221epcas5p3ffb9e643af6b8ae07cfccf0bdee90e37@epcas5p3.samsung.com>
2025-07-30 12:11 ` [PATCH V2 00/20] Add CXL LSA 2.1 format support in nvdimm and cxl pmem Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 01/20] nvdimm/label: Introduce NDD_CXL_LABEL flag to set cxl label format Neeraj Kumar
2025-08-13 13:12 ` Jonathan Cameron
2025-08-15 18:06 ` Dave Jiang
2025-09-04 13:24 ` Neeraj Kumar [this message]
2025-09-04 13:20 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 02/20] nvdimm/label: Prep patch to accommodate cxl lsa 2.1 support Neeraj Kumar
2025-08-13 13:23 ` Jonathan Cameron
2025-09-04 13:27 ` Neeraj Kumar
2025-08-15 22:02 ` Dave Jiang
2025-09-04 13:31 ` Neeraj Kumar
2025-08-18 21:48 ` Dave Jiang
2025-09-04 13:33 ` Neeraj Kumar
2025-08-19 15:38 ` Ira Weiny
2025-09-04 13:42 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 03/20] nvdimm/namespace_label: Add namespace label changes as per CXL LSA v2.1 Neeraj Kumar
2025-07-31 13:12 ` kernel test robot
2025-08-13 13:27 ` Jonathan Cameron
2025-09-04 13:40 ` Neeraj Kumar
2025-08-19 15:57 ` Ira Weiny
2025-09-04 13:51 ` Neeraj Kumar
2025-08-19 19:36 ` Ira Weiny
2025-09-05 5:34 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 04/20] nvdimm/label: CXL labels skip the need for 'interleave-set cookie' Neeraj Kumar
2025-08-13 13:44 ` Jonathan Cameron
2025-09-04 13:54 ` Neeraj Kumar
2025-08-15 21:02 ` Dave Jiang
2025-09-04 14:01 ` Neeraj Kumar
2025-08-19 16:04 ` Ira Weiny
2025-09-04 14:02 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 05/20] nvdimm/region_label: Add region label updation routine Neeraj Kumar
2025-07-31 15:07 ` kernel test robot
2025-08-13 14:48 ` Jonathan Cameron
2025-09-04 14:06 ` Neeraj Kumar
2025-08-15 21:55 ` Dave Jiang
2025-09-04 14:12 ` Neeraj Kumar
2025-09-10 14:03 ` Jonathan Cameron
2025-08-15 23:12 ` Dave Jiang
2025-09-04 14:13 ` Neeraj Kumar
2025-08-19 18:16 ` Ira Weiny
2025-09-04 14:18 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 06/20] nvdimm/region_label: Add region label deletion routine Neeraj Kumar
2025-08-13 14:53 ` Jonathan Cameron
2025-09-04 14:20 ` Neeraj Kumar
2025-08-15 22:22 ` Dave Jiang
2025-09-04 14:23 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 07/20] nvdimm/namespace_label: Update namespace init_labels and its region_uuid Neeraj Kumar
2025-08-13 14:58 ` Jonathan Cameron
2025-09-04 14:24 ` Neeraj Kumar
2025-08-19 18:56 ` Ira Weiny
2025-09-04 14:28 ` Neeraj Kumar
2025-09-05 20:08 ` Ira Weiny
2025-09-08 5:36 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 08/20] nvdimm/label: Include region label in slot validation Neeraj Kumar
2025-08-13 15:07 ` Jonathan Cameron
2025-09-04 14:30 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 09/20] nvdimm/namespace_label: Skip region label during ns label DPA reservation Neeraj Kumar
2025-08-13 15:09 ` Jonathan Cameron
2025-09-04 14:31 ` Neeraj Kumar
2025-07-30 12:11 ` [PATCH V2 10/20] nvdimm/region_label: Preserve cxl region information from region label Neeraj Kumar
2025-08-13 15:11 ` Jonathan Cameron
2025-09-04 14:33 ` Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 11/20] nvdimm/region_label: Export routine to fetch region information Neeraj Kumar
2025-08-13 15:13 ` Jonathan Cameron
2025-07-30 12:12 ` [PATCH V2 12/20] nvdimm/namespace_label: Skip region label during namespace creation Neeraj Kumar
2025-08-13 15:55 ` Jonathan Cameron
2025-09-04 14:34 ` Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 13/20] cxl/mem: Refactor cxl pmem region auto-assembling Neeraj Kumar
2025-08-20 16:41 ` Dave Jiang
2025-09-04 14:39 ` Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 14/20] cxl/region: Add devm_cxl_pmem_add_region() for pmem region creation Neeraj Kumar
2025-08-20 0:30 ` Dave Jiang
2025-09-04 14:55 ` Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 15/20] cxl: Add a routine to find cxl root decoder on cxl bus using cxl port Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 16/20] cxl/mem: Preserve cxl root decoder during mem probe Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 17/20] cxl/pmem: Preserve region information into nd_set Neeraj Kumar
2025-07-30 12:12 ` [PATCH V2 18/20] cxl/pmem: Add support of cxl lsa 2.1 support in cxl pmem Neeraj Kumar
2025-07-31 1:36 ` kernel test robot
2025-07-30 12:12 ` [PATCH V2 19/20] cxl/pmem_region: Prep patch to accommodate pmem_region attributes Neeraj Kumar
2025-07-31 1:57 ` kernel test robot
2025-07-31 2:17 ` kernel test robot
2025-07-30 12:12 ` [PATCH V2 20/20] cxl/pmem_region: Add sysfs attribute cxl region label updation/deletion Neeraj Kumar
2025-07-31 10:36 ` kernel test robot
2025-08-07 9:02 ` [PATCH V2 00/20] Add CXL LSA 2.1 format support in nvdimm and cxl pmem Neeraj Kumar
2025-08-12 21:46 ` Dave Jiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1983025922.01757055603347.JavaMail.epsvc@epcpadp1new \
--to=s.neeraj@samsung.com \
--cc=Jonathan.Cameron@huawei.com \
--cc=a.manzanares@samsung.com \
--cc=cpgs@samsung.com \
--cc=dave.jiang@intel.com \
--cc=gost.dev@samsung.com \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=neeraj.kernel@gmail.com \
--cc=nvdimm@lists.linux.dev \
--cc=vishak.g@samsung.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox