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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: linuxarm@huawei.com, qemu-devel@nongnu.org,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Marcel Apfelbaum" <marcel@redhat.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	"Igor Mammedov" <imammedo@redhat.com>,
	"Markus Armbruster" <armbru@redhat.com>
Cc: linux-cxl@vger.kernel.org,
	"Ben Widawsky" <ben.widawsky@intel.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Shameerali Kolothum Thodi"
	<shameerali.kolothum.thodi@huawei.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Peter Xu" <peterx@redhat.com>,
	"David Hildenbrand" <david@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Saransh Gupta1" <saransh@ibm.com>,
	"Shreyas Shah" <shreyas.shah@elastics.cloud>,
	"Chris Browy" <cbrowy@avery-design.com>,
	"Samarth Saxena" <samarths@cadence.com>,
	"Dan Williams" <dan.j.williams@intel.com>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>
Subject: [PATCH v8 21/46] hw/cxl/device: Implement get/set Label Storage Area (LSA)
Date: Fri, 18 Mar 2022 15:06:10 +0000	[thread overview]
Message-ID: <20220318150635.24600-22-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220318150635.24600-1-Jonathan.Cameron@huawei.com>

From: Ben Widawsky <ben.widawsky@intel.com>

Implement get and set handlers for the Label Storage Area
used to hold data describing persistent memory configuration
so that it can be ensured it is seen in the same configuration
after reboot.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 hw/cxl/cxl-mailbox-utils.c  | 60 +++++++++++++++++++++++++++++++++++++
 hw/mem/cxl_type3.c          | 56 +++++++++++++++++++++++++++++++++-
 include/hw/cxl/cxl_device.h |  5 ++++
 3 files changed, 120 insertions(+), 1 deletion(-)

diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 771b1cfe90..acb73c7a68 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -57,6 +57,8 @@ enum {
         #define MEMORY_DEVICE 0x0
     CCLS        = 0x41,
         #define GET_PARTITION_INFO     0x0
+        #define GET_LSA       0x2
+        #define SET_LSA       0x3
 };
 
 /* 8.2.8.4.5.1 Command Return Codes */
@@ -326,7 +328,62 @@ static ret_code cmd_ccls_get_partition_info(struct cxl_cmd *cmd,
     return CXL_MBOX_SUCCESS;
 }
 
+static ret_code cmd_ccls_get_lsa(struct cxl_cmd *cmd,
+                                 CXLDeviceState *cxl_dstate,
+                                 uint16_t *len)
+{
+    struct {
+        uint32_t offset;
+        uint32_t length;
+    } QEMU_PACKED *get_lsa;
+    CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
+    CXLType3Class *cvc = CXL_TYPE3_DEV_GET_CLASS(ct3d);
+    uint32_t offset, length;
+
+    get_lsa = (void *)cmd->payload;
+    offset = get_lsa->offset;
+    length = get_lsa->length;
+
+    if (offset + length > cvc->get_lsa_size(ct3d)) {
+        *len = 0;
+        return CXL_MBOX_INVALID_INPUT;
+    }
+
+    *len = cvc->get_lsa(ct3d, get_lsa, length, offset);
+    return CXL_MBOX_SUCCESS;
+}
+
+static ret_code cmd_ccls_set_lsa(struct cxl_cmd *cmd,
+                                 CXLDeviceState *cxl_dstate,
+                                 uint16_t *len)
+{
+    struct set_lsa_pl {
+        uint32_t offset;
+        uint32_t rsvd;
+        uint8_t data[];
+    } QEMU_PACKED;
+    struct set_lsa_pl *set_lsa_payload = (void *)cmd->payload;
+    CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
+    CXLType3Class *cvc = CXL_TYPE3_DEV_GET_CLASS(ct3d);
+    const size_t hdr_len = offsetof(struct set_lsa_pl, data);
+    uint16_t plen = *len;
+
+    *len = 0;
+    if (!plen) {
+        return CXL_MBOX_SUCCESS;
+    }
+
+    if (set_lsa_payload->offset + plen > cvc->get_lsa_size(ct3d) + hdr_len) {
+        return CXL_MBOX_INVALID_INPUT;
+    }
+    plen -= hdr_len;
+
+    cvc->set_lsa(ct3d, set_lsa_payload->data, plen, set_lsa_payload->offset);
+    return CXL_MBOX_SUCCESS;
+}
+
 #define IMMEDIATE_CONFIG_CHANGE (1 << 1)
+#define IMMEDIATE_DATA_CHANGE (1 << 2)
 #define IMMEDIATE_POLICY_CHANGE (1 << 3)
 #define IMMEDIATE_LOG_CHANGE (1 << 4)
 
@@ -349,6 +406,9 @@ static struct cxl_cmd cxl_cmd_set[256][256] = {
         cmd_identify_memory_device, 0, 0 },
     [CCLS][GET_PARTITION_INFO] = { "CCLS_GET_PARTITION_INFO",
         cmd_ccls_get_partition_info, 0, 0 },
+    [CCLS][GET_LSA] = { "CCLS_GET_LSA", cmd_ccls_get_lsa, 0, 0 },
+    [CCLS][SET_LSA] = { "CCLS_SET_LSA", cmd_ccls_set_lsa,
+        ~0, IMMEDIATE_CONFIG_CHANGE | IMMEDIATE_DATA_CHANGE },
 };
 
 void cxl_process_mailbox(CXLDeviceState *cxl_dstate)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 7cd3041eb3..244eb5dc91 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -8,6 +8,7 @@
 #include "qapi/error.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
+#include "qemu/pmem.h"
 #include "qemu/range.h"
 #include "qemu/rcu.h"
 #include "sysemu/hostmem.h"
@@ -115,6 +116,11 @@ static void cxl_setup_memory(CXLType3Dev *ct3d, Error **errp)
     memory_region_set_enabled(mr, true);
     host_memory_backend_set_mapped(ct3d->hostmem, true);
     ct3d->cxl_dstate.pmem_size = ct3d->hostmem->size;
+
+    if (!ct3d->lsa) {
+        error_setg(errp, "lsa property must be set");
+        return;
+    }
 }
 
 
@@ -167,12 +173,58 @@ static Property ct3_props[] = {
     DEFINE_PROP_SIZE("size", CXLType3Dev, size, -1),
     DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND,
                      HostMemoryBackend *),
+    DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND,
+                     HostMemoryBackend *),
     DEFINE_PROP_END_OF_LIST(),
 };
 
 static uint64_t get_lsa_size(CXLType3Dev *ct3d)
 {
-    return 0;
+    MemoryRegion *mr;
+
+    mr = host_memory_backend_get_memory(ct3d->lsa);
+    return memory_region_size(mr);
+}
+
+static void validate_lsa_access(MemoryRegion *mr, uint64_t size,
+                                uint64_t offset)
+{
+    assert(offset + size <= memory_region_size(mr));
+    assert(offset + size > offset);
+}
+
+static uint64_t get_lsa(CXLType3Dev *ct3d, void *buf, uint64_t size,
+                    uint64_t offset)
+{
+    MemoryRegion *mr;
+    void *lsa;
+
+    mr = host_memory_backend_get_memory(ct3d->lsa);
+    validate_lsa_access(mr, size, offset);
+
+    lsa = memory_region_get_ram_ptr(mr) + offset;
+    memcpy(buf, lsa, size);
+
+    return size;
+}
+
+static void set_lsa(CXLType3Dev *ct3d, const void *buf, uint64_t size,
+                    uint64_t offset)
+{
+    MemoryRegion *mr;
+    void *lsa;
+
+    mr = host_memory_backend_get_memory(ct3d->lsa);
+    validate_lsa_access(mr, size, offset);
+
+    lsa = memory_region_get_ram_ptr(mr) + offset;
+    memcpy(lsa, buf, size);
+    memory_region_set_dirty(mr, offset, size);
+
+    /*
+     * Just like the PMEM, if the guest is not allowed to exit gracefully, label
+     * updates will get lost.
+     */
 }
 
 static void ct3_class_init(ObjectClass *oc, void *data)
@@ -193,6 +245,8 @@ static void ct3_class_init(ObjectClass *oc, void *data)
     device_class_set_props(dc, ct3_props);
 
     cvc->get_lsa_size = get_lsa_size;
+    cvc->get_lsa = get_lsa;
+    cvc->set_lsa = set_lsa;
 }
 
 static const TypeInfo ct3d_info = {
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index cf4c110f7e..288cc11772 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -255,6 +255,11 @@ struct CXLType3Class {
 
     /* public */
     uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
+
+    uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size,
+                        uint64_t offset);
+    void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size,
+                    uint64_t offset);
 };
 
 #endif
-- 
2.32.0


  parent reply	other threads:[~2022-03-18 15:17 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-18 15:05 [PATCH v8 00/46] CXl 2.0 emulation Support Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 01/46] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron
2022-03-27 13:32   ` Adam Manzanares
2022-03-18 15:05 ` [PATCH v8 02/46] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron
2022-03-25 13:45   ` Jonathan Cameron
2022-03-28 14:28   ` Adam Manzanares
2022-03-30 16:55     ` Jonathan Cameron
2022-03-31 12:20   ` Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 03/46] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 04/46] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron
2022-03-29 18:13   ` Adam Manzanares
2022-03-29 19:53     ` Davidlohr Bueso
2022-03-30 12:15       ` Jonathan Cameron
2022-03-31 21:42         ` Adam Manzanares
2022-03-30 17:48     ` Jonathan Cameron
2022-03-31 22:13       ` Adam Manzanares
2022-04-01 13:30         ` Jonathan Cameron
2022-04-04 15:15           ` Adam Manzanares
2022-04-05  9:10             ` Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 05/46] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 06/46] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 07/46] hw/cxl/device: Add memory device utilities Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 08/46] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 09/46] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 10/46] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 11/46] hw/pxb: Use a type for realizing expanders Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 12/46] hw/pci/cxl: Create a CXL bus type Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 13/46] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 14/46] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 15/46] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 16/46] hw/cxl/rp: Add a root port Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 17/46] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron
2022-03-19  8:32   ` Mark Cave-Ayland
2022-03-23 18:18     ` Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 18/46] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 19/46] hw/cxl/device: Add some trivial commands Jonathan Cameron
2022-03-18 16:56   ` Alison Schofield
2022-03-23 15:57     ` Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 20/46] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron
2022-03-18 15:06 ` Jonathan Cameron [this message]
2022-03-18 15:06 ` [PATCH v8 22/46] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 23/46] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron
2022-03-19  8:35   ` Mark Cave-Ayland
2022-03-23 18:37     ` Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 24/46] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 25/46] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 26/46] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 27/46] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron
2022-03-28 12:50   ` Markus Armbruster
2022-03-31 12:12     ` Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 28/46] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 29/46] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 30/46] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 31/46] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 32/46] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron
2022-03-19  8:53   ` Mark Cave-Ayland
2022-03-23 15:43     ` Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 33/46] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 34/46] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 35/46] i386/pc: Enable CXL fixed memory windows Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 36/46] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 37/46] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 38/46] tests/acpi: Add tables " Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 39/46] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 40/46] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 41/46] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 42/46] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 43/46] pci-bridge/cxl_upstream: Add a CXL switch upstream port Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 44/46] pci-bridge/cxl_downstream: Add a CXL switch downstream port Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 45/46] cxl/cxl-host: Support interleave decoding with one level of switches Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 46/46] docs/cxl: Add switch documentation Jonathan Cameron

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