From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Markus Armbruster <armbru@redhat.com>
Cc: linuxarm@huawei.com, qemu-devel@nongnu.org,
"Alex Bennée" <alex.bennee@linaro.org>,
"Marcel Apfelbaum" <marcel@redhat.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Igor Mammedov" <imammedo@redhat.com>,
linux-cxl@vger.kernel.org,
"Ben Widawsky" <ben.widawsky@intel.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Shameerali Kolothum Thodi"
<shameerali.kolothum.thodi@huawei.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Peter Xu" <peterx@redhat.com>,
"David Hildenbrand" <david@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Saransh Gupta1" <saransh@ibm.com>,
"Shreyas Shah" <shreyas.shah@elastics.cloud>,
"Chris Browy" <cbrowy@avery-design.com>,
"Samarth Saxena" <samarths@cadence.com>,
"Dan Williams" <dan.j.williams@intel.com>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>
Subject: Re: [PATCH v8 27/46] hw/cxl/host: Add support for CXL Fixed Memory Windows.
Date: Thu, 31 Mar 2022 13:12:03 +0100 [thread overview]
Message-ID: <20220331131203.000079cd@huawei.com> (raw)
In-Reply-To: <87lewu8cmo.fsf@pond.sub.org>
On Mon, 28 Mar 2022 14:50:23 +0200
Markus Armbruster <armbru@redhat.com> wrote:
> Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
>
> > From: Jonathan Cameron <jonathan.cameron@huawei.com>
> >
> > The concept of these is introduced in [1] in terms of the
> > description the CEDT ACPI table. The principal is more general.
> > Unlike once traffic hits the CXL root bridges, the host system
> > memory address routing is implementation defined and effectively
> > static once observable by standard / generic system software.
> > Each CXL Fixed Memory Windows (CFMW) is a region of PA space
> > which has fixed system dependent routing configured so that
> > accesses can be routed to the CXL devices below a set of target
> > root bridges. The accesses may be interleaved across multiple
> > root bridges.
> >
> > For QEMU we could have fully specified these regions in terms
> > of a base PA + size, but as the absolute address does not matter
> > it is simpler to let individual platforms place the memory regions.
> >
> > ExampleS:
> > -cxl-fixed-memory-window targets.0=cxl.0,size=128G
> > -cxl-fixed-memory-window targets.0=cxl.1,size=128G
> > -cxl-fixed-memory-window targets.0=cxl0,targets.1=cxl.1,size=256G,interleave-granularity=2k
> >
> > Specifies
> > * 2x 128G regions not interleaved across root bridges, one for each of
> > the root bridges with ids cxl.0 and cxl.1
> > * 256G region interleaved across root bridges with ids cxl.0 and cxl.1
> > with a 2k interleave granularity.
> >
> > When system software enumerates the devices below a given root bridge
> > it can then decide which CFMW to use. If non interleave is desired
> > (or possible) it can use the appropriate CFMW for the root bridge in
> > question. If there are suitable devices to interleave across the
> > two root bridges then it may use the 3rd CFMS.
> >
> > A number of other designs were considered but the following constraints
> > made it hard to adapt existing QEMU approaches to this particular problem.
> > 1) The size must be known before a specific architecture / board brings
> > up it's PA memory map. We need to set up an appropriate region.
> > 2) Using links to the host bridges provides a clean command line interface
> > but these links cannot be established until command line devices have
> > been added.
> >
> > Hence the two step process used here of first establishing the size,
> > interleave-ways and granularity + caching the ids of the host bridges
> > and then, once available finding the actual host bridges so they can
> > be used later to support interleave decoding.
> >
> > [1] CXL 2.0 ECN: CEDT CFMWS & QTG DSM (computeexpresslink.org / specifications)
> >
> > Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Agree with everything you've raised. Thanks!
Jonathan
>
> [...]
>
> > diff --git a/qapi/machine.json b/qapi/machine.json
> > index 42fc68403d..e4e64096ca 100644
> > --- a/qapi/machine.json
> > +++ b/qapi/machine.json
> > @@ -504,6 +504,24 @@
> > 'dst': 'uint16',
> > 'val': 'uint8' }}
> >
> > +##
> > +# @CXLFixedMemoryWindowOptions:
> > +#
> > +# Create a CXL Fixed Memory Window (for OptsVisitor)
>
> Please drop "(for OptsVisitor)". It's no longer true.
>
Done
> Aside: I'd ask to drop it even if it was true, because it's about an
> implementation detail. Such details don't belong in doc comments, which
> become QMP *user* documentation. I know we have the same parenthesis
> elsewhere. It should be dropped there as well, but that's not this
> series' problem.
>
> > +#
> > +# @size: Size in bytes of the Fixed Memory Window
>
> I'm not a native speaker, but "Size of the fixed memory window in bytes"
> sounds better to me.
Done.
>
> Are arbitrary sizes accepted?
Good point - no. Multiple of 256MiB. Added
"Must be a multiple of 256MiB."
For interleave-granularity I've listed the possible values out as
"Accepted values [256, 512, 1k, 2k, 4k, 8k, 16k]"
>
> > +# @interleave-granularity: Number of contiguous bytes for which
> > +# accesses will go to a given interleave target.
> > +# @targets: Target root bridge IDs
>
> What kind of IDs are these? Hmm, the CLI help text below suggest qdev
> IDs (the ones in -device id=...). Correct?
Yes. I've added "from -device ...,id=<ID> for each root bridge."
That leaves room for other root bridge implementations than pxb-cxl
in future without having to update this text.
>
> > +#
> > +# Since 6.3
>
> 7.1 most likely.
Updated.
>
> > +##
> > +{ 'struct': 'CXLFixedMemoryWindowOptions',
> > + 'data': {
> > + 'size': 'size',
> > + '*interleave-granularity': 'size',
> > + 'targets': ['str'] }}
> > +
> > ##
> > # @X86CPURegister32:
> > #
> > diff --git a/qemu-options.hx b/qemu-options.hx
> > index 58f2f76775..764f57606d 100644
> > --- a/qemu-options.hx
> > +++ b/qemu-options.hx
> > @@ -467,6 +467,44 @@ SRST
> > -numa hmat-cache,node-id=1,size=10K,level=1,associativity=direct,policy=write-back,line=8
> > ERST
> >
> > +DEF("cxl-fixed-memory-window", HAS_ARG, QEMU_OPTION_cxl_fixed_memory_window,
> > + "-cxl-fixed-memory-window targets.0=firsttarget,targets.1=secondtarget,size=size[,interleave-granularity=granularity]\n",
> > + QEMU_ARCH_ALL)
> > +SRST
> > +``-cxl-fixed-memory-window targets.0=firsttarget,targets.1=secondtarget,size=size[,interleave-granularity=granularity]``
> > + Define a CXL Fixed Memory Window (CFMW).
> > +
> > + Described in the CXL 2.0 ECN: CEDT CFMWS & QTG _DSM.
> > +
> > + They are regions of Host Physical Addresses (HPA) on a system which
> > + may be interleaved across one or more CXL host bridges. The system
> > + software will assign particular devices into these windows and
> > + configure the downstream Host-managed Device Memory (HDM) decoders
> > + in root ports, switch ports and devices appropriately to meet the
> > + interleave requirements before enabling the memory devices.
> > +
> > + ``targets.X=firsttarget`` provides the mapping to CXL host bridges
> > + which may be identified by the id provied in the -device entry.
> > + Multiple entries are needed to specify all the targets when
> > + the fixed memory window represents interleaved memory. X is the
> > + target index from 0.
> > +
> > + ``size=size`` sets the size of the CFMW. This must be a multiple of
> > + 256MiB. The region will be aligned to 256MiB but the location is
> > + platform and configuration dependent.
> > +
> > + ``interleave-granularity=granularity`` sets the granularity of
> > + interleave. Default 256KiB. Only 256KiB, 512KiB, 1024KiB, 2048KiB
> > + 4096KiB, 8192KiB and 16384KiB granularities supported.
> > +
> > + Example:
> > +
> > + ::
> > +
> > + -cxl-fixed-memory-window -targets.0=cxl.0,-targets.1=cxl.1,size=128G,interleave-granularity=512k
> > +
> > +ERST
> > +
> > DEF("add-fd", HAS_ARG, QEMU_OPTION_add_fd,
> > "-add-fd fd=fd,set=set[,opaque=opaque]\n"
> > " Add 'fd' to fd 'set'\n", QEMU_ARCH_ALL)
> > diff --git a/softmmu/vl.c b/softmmu/vl.c
> > index 0b81f61535..dab1eb3380 100644
> > --- a/softmmu/vl.c
> > +++ b/softmmu/vl.c
> > @@ -92,6 +92,7 @@
> > #include "qemu/config-file.h"
> > #include "qemu/qemu-options.h"
> > #include "qemu/main-loop.h"
> > +#include "hw/cxl/cxl.h"
> > #ifdef CONFIG_VIRTFS
> > #include "fsdev/qemu-fsdev.h"
> > #endif
> > @@ -117,6 +118,7 @@
> > #include "qapi/qapi-events-run-state.h"
> > #include "qapi/qapi-visit-block-core.h"
> > #include "qapi/qapi-visit-compat.h"
> > +#include "qapi/qapi-visit-machine.h"
> > #include "qapi/qapi-visit-ui.h"
> > #include "qapi/qapi-commands-block-core.h"
> > #include "qapi/qapi-commands-migration.h"
> > @@ -140,6 +142,11 @@ typedef struct BlockdevOptionsQueueEntry {
> >
> > typedef QSIMPLEQ_HEAD(, BlockdevOptionsQueueEntry) BlockdevOptionsQueue;
> >
> > +typedef struct CXLFMWOptionQueueEntry {
> > + CXLFixedMemoryWindowOptions *opts;
> > + QSIMPLEQ_ENTRY(CXLFMWOptionQueueEntry) entry;
> > +} CXLFMWOptionQueueEntry;
> > +
> > typedef struct ObjectOption {
> > ObjectOptions *opts;
> > QTAILQ_ENTRY(ObjectOption) next;
> > @@ -166,6 +173,8 @@ static int snapshot;
> > static bool preconfig_requested;
> > static QemuPluginList plugin_list = QTAILQ_HEAD_INITIALIZER(plugin_list);
> > static BlockdevOptionsQueue bdo_queue = QSIMPLEQ_HEAD_INITIALIZER(bdo_queue);
> > +static QSIMPLEQ_HEAD(, CXLFMWOptionQueueEntry) CXLFMW_opts =
> > + QSIMPLEQ_HEAD_INITIALIZER(CXLFMW_opts);
> > static bool nographic = false;
> > static int mem_prealloc; /* force preallocation of physical target memory */
> > static ram_addr_t ram_size;
> > @@ -1149,6 +1158,23 @@ static void parse_display(const char *p)
> > }
> > }
> >
> > +static void parse_cxl_fixed_memory_window(const char *optarg)
> > +{
> > + CXLFMWOptionQueueEntry *cfmws_entry;
> > + Visitor *v;
> > +
> > + v = qobject_input_visitor_new_str(optarg, "cxl-fixed-memory-window",
> > + &error_fatal);
> > + cfmws_entry = g_new(CXLFMWOptionQueueEntry, 1);
> > + visit_type_CXLFixedMemoryWindowOptions(v, NULL, &cfmws_entry->opts,
> > + &error_fatal);
> > + if (!cfmws_entry->opts) {
> > + exit(1);
> > + }
> > + visit_free(v);
>
> If you loc_save() here like we do for QEMU_OPTION_blockdev, and ...
>
> > + QSIMPLEQ_INSERT_TAIL(&CXLFMW_opts, cfmws_entry, entry);
> > +}
> > +
> > static inline bool nonempty_str(const char *str)
> > {
> > return str && *str;
> > @@ -2020,6 +2046,19 @@ static void qemu_create_late_backends(void)
> > qemu_semihosting_console_init();
> > }
> >
> > +static void cxl_set_opts(void)
> > +{
> > + while (!QSIMPLEQ_EMPTY(&CXLFMW_opts)) {
> > + CXLFMWOptionQueueEntry *cfmws_entry = QSIMPLEQ_FIRST(&CXLFMW_opts);
> > +
> > + QSIMPLEQ_REMOVE_HEAD(&CXLFMW_opts, entry);
>
> ... loc_pop() here, like we do in configure_blockdev(), then the error
> messages from cxl_fixed_memory_window_options_set() will point to the
> offending option, which is nice. Give it a try, please.
Nice :)
>
> > + cxl_fixed_memory_window_options_set(current_machine, cfmws_entry->opts,
>
> Line is a bit long. Name the function cxl_fixed_memory_window_config()?
Done
>
> > + &error_fatal);
> > + qapi_free_CXLFixedMemoryWindowOptions(cfmws_entry->opts);
> > + g_free(cfmws_entry);
> > + }
> > +}
> > +
> > static bool have_custom_ram_size(void)
> > {
> > QemuOpts *opts = qemu_find_opts_singleton("memory");
> > @@ -2745,6 +2784,7 @@ void qmp_x_exit_preconfig(Error **errp)
> >
> > qemu_init_board();
> > qemu_create_cli_devices();
> > + cxl_fixed_memory_window_link_targets(errp);
> > qemu_machine_creation_done();
> >
> > if (loadvm) {
> > @@ -2925,6 +2965,9 @@ void qemu_init(int argc, char **argv, char **envp)
> > exit(1);
> > }
> > break;
> > + case QEMU_OPTION_cxl_fixed_memory_window:
> > + parse_cxl_fixed_memory_window(optarg);
> > + break;
> > case QEMU_OPTION_display:
> > parse_display(optarg);
> > break;
> > @@ -3762,6 +3805,7 @@ void qemu_init(int argc, char **argv, char **envp)
> >
> > qemu_resolve_machine_memdev();
> > parse_numa_opts(current_machine);
> > + cxl_set_opts();
> >
> > if (vmstate_dump_file) {
> > /* dump and exit */
>
next prev parent reply other threads:[~2022-03-31 12:12 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-18 15:05 [PATCH v8 00/46] CXl 2.0 emulation Support Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 01/46] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron
2022-03-27 13:32 ` Adam Manzanares
2022-03-18 15:05 ` [PATCH v8 02/46] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron
2022-03-25 13:45 ` Jonathan Cameron
2022-03-28 14:28 ` Adam Manzanares
2022-03-30 16:55 ` Jonathan Cameron
2022-03-31 12:20 ` Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 03/46] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 04/46] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron
2022-03-29 18:13 ` Adam Manzanares
2022-03-29 19:53 ` Davidlohr Bueso
2022-03-30 12:15 ` Jonathan Cameron
2022-03-31 21:42 ` Adam Manzanares
2022-03-30 17:48 ` Jonathan Cameron
2022-03-31 22:13 ` Adam Manzanares
2022-04-01 13:30 ` Jonathan Cameron
2022-04-04 15:15 ` Adam Manzanares
2022-04-05 9:10 ` Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 05/46] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 06/46] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 07/46] hw/cxl/device: Add memory device utilities Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 08/46] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 09/46] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 10/46] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 11/46] hw/pxb: Use a type for realizing expanders Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 12/46] hw/pci/cxl: Create a CXL bus type Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 13/46] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 14/46] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 15/46] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 16/46] hw/cxl/rp: Add a root port Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 17/46] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron
2022-03-19 8:32 ` Mark Cave-Ayland
2022-03-23 18:18 ` Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 18/46] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 19/46] hw/cxl/device: Add some trivial commands Jonathan Cameron
2022-03-18 16:56 ` Alison Schofield
2022-03-23 15:57 ` Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 20/46] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 21/46] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 22/46] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 23/46] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron
2022-03-19 8:35 ` Mark Cave-Ayland
2022-03-23 18:37 ` Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 24/46] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 25/46] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 26/46] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 27/46] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron
2022-03-28 12:50 ` Markus Armbruster
2022-03-31 12:12 ` Jonathan Cameron [this message]
2022-03-18 15:06 ` [PATCH v8 28/46] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 29/46] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 30/46] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 31/46] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 32/46] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron
2022-03-19 8:53 ` Mark Cave-Ayland
2022-03-23 15:43 ` Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 33/46] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 34/46] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 35/46] i386/pc: Enable CXL fixed memory windows Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 36/46] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 37/46] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 38/46] tests/acpi: Add tables " Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 39/46] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 40/46] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 41/46] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 42/46] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 43/46] pci-bridge/cxl_upstream: Add a CXL switch upstream port Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 44/46] pci-bridge/cxl_downstream: Add a CXL switch downstream port Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 45/46] cxl/cxl-host: Support interleave decoding with one level of switches Jonathan Cameron
2022-03-18 15:06 ` [PATCH v8 46/46] docs/cxl: Add switch documentation Jonathan Cameron
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