From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <ben.widawsky@intel.com>,
<ira.weiny@intel.com>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>
Subject: Re: [PATCH 11/14] cxl/pci: Drop @info argument to cxl_hdm_decode_init()
Date: Wed, 18 May 2022 17:45:02 +0100 [thread overview]
Message-ID: <20220518174502.0000240e@Huawei.com> (raw)
In-Reply-To: <165237931557.3832067.5196055352152981142.stgit@dwillia2-desk3.amr.corp.intel.com>
On Thu, 12 May 2022 11:15:15 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> Now that nothing external to cxl_hdm_decode_init() considers
> 'struct cxl_endpoint_dvec_info' move it internal to
> cxl_hdm_decode_init().
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Makes sense.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/pci.c | 15 +++++++--------
> drivers/cxl/cxlpci.h | 4 +---
> drivers/cxl/mem.c | 3 +--
> tools/testing/cxl/test/mock.c | 9 +++------
> 4 files changed, 12 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 6146764ac68e..8f14d846713c 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -226,14 +226,13 @@ static bool __cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
> /**
> * cxl_hdm_decode_init() - Setup HDM decoding for the endpoint
> * @cxlds: Device state
> - * @info: DVSEC Range cached enumeration
> *
> * Try to enable the endpoint's HDM Decoder Capability
> */
> -int cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
> - struct cxl_endpoint_dvsec_info *info)
> +int cxl_hdm_decode_init(struct cxl_dev_state *cxlds)
> {
> struct pci_dev *pdev = to_pci_dev(cxlds->dev);
> + struct cxl_endpoint_dvsec_info info = { 0 };
> int hdm_count, rc, i, ranges = 0;
> struct device *dev = &pdev->dev;
> int d = cxlds->cxl_dvsec;
> @@ -273,8 +272,8 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
> return rc;
> }
>
> - info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl);
> - if (!info->mem_enabled)
> + info.mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl);
> + if (!info.mem_enabled)
> return 0;
>
> for (i = 0; i < hdm_count; i++) {
> @@ -314,7 +313,7 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
>
> base |= temp & CXL_DVSEC_MEM_BASE_LOW_MASK;
>
> - info->dvsec_range[i] = (struct range) {
> + info.dvsec_range[i] = (struct range) {
> .start = base,
> .end = base + size - 1
> };
> @@ -322,13 +321,13 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
> ranges++;
> }
>
> - info->ranges = ranges;
> + info.ranges = ranges;
>
> /*
> * If DVSEC ranges are being used instead of HDM decoder registers there
> * is no use in trying to manage those.
> */
> - if (!__cxl_hdm_decode_init(cxlds, info)) {
> + if (!__cxl_hdm_decode_init(cxlds, &info)) {
> dev_err(dev,
> "Legacy range registers configuration prevents HDM operation.\n");
> return -EBUSY;
> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index 202fdaa8d293..53cd34f8813c 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -73,7 +73,5 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
>
> int devm_cxl_port_enumerate_dports(struct cxl_port *port);
> struct cxl_dev_state;
> -struct cxl_endpoint_dvsec_info;
> -int cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
> - struct cxl_endpoint_dvsec_info *info);
> +int cxl_hdm_decode_init(struct cxl_dev_state *cxlds);
> #endif /* __CXL_PCI_H__ */
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 2a5dc92d566f..8ce89d128e36 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -54,7 +54,6 @@ static void enable_suspend(void *data)
> static int cxl_mem_probe(struct device *dev)
> {
> struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
> - struct cxl_endpoint_dvsec_info info = { 0 };
> struct cxl_dev_state *cxlds = cxlmd->cxlds;
> struct cxl_port *parent_port;
> int rc;
> @@ -95,7 +94,7 @@ static int cxl_mem_probe(struct device *dev)
> if (rc)
> return rc;
>
> - rc = cxl_hdm_decode_init(cxlds, &info);
> + rc = cxl_hdm_decode_init(cxlds);
> if (rc)
> return rc;
>
> diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c
> index ddf0e7dd9249..45ffbb8f519a 100644
> --- a/tools/testing/cxl/test/mock.c
> +++ b/tools/testing/cxl/test/mock.c
> @@ -208,16 +208,13 @@ int __wrap_cxl_await_media_ready(struct cxl_dev_state *cxlds)
> }
> EXPORT_SYMBOL_NS_GPL(__wrap_cxl_await_media_ready, CXL);
>
> -int __wrap_cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
> - struct cxl_endpoint_dvsec_info *info)
> +bool __wrap_cxl_hdm_decode_init(struct cxl_dev_state *cxlds)
> {
> int rc = 0, index;
> struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
>
> - if (ops && ops->is_mock_dev(cxlds->dev))
> - info->mem_enabled = 1;
> - else
> - rc = cxl_hdm_decode_init(cxlds, info);
> + if (!ops || !ops->is_mock_dev(cxlds->dev))
> + rc = cxl_hdm_decode_init(cxlds);
> put_cxl_mock_ops(index);
>
> return rc;
>
next prev parent reply other threads:[~2022-05-18 16:45 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-12 18:14 [PATCH 00/14] cxl: Fix "mem_enable" handling Dan Williams
2022-05-12 18:14 ` [PATCH 01/14] cxl/mem: Drop mem_enabled check from wait_for_media() Dan Williams
2022-05-18 17:21 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 02/14] cxl/pci: Consolidate wait_for_media() and wait_for_media_ready() Dan Williams
2022-05-18 17:22 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 03/14] cxl/pci: Drop wait_for_valid() from cxl_await_media_ready() Dan Williams
2022-05-18 17:22 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 04/14] cxl/mem: Fix cxl_mem_probe() error exit Dan Williams
2022-05-18 17:23 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 05/14] cxl/mem: Validate port connectivity before dvsec ranges Dan Williams
2022-05-18 16:13 ` Jonathan Cameron
2022-05-18 16:41 ` Dan Williams
2022-05-18 17:21 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 06/14] cxl/pci: Move cxl_await_media_ready() to the core Dan Williams
2022-05-18 16:21 ` Jonathan Cameron
2022-05-18 16:37 ` Dan Williams
2022-05-18 17:20 ` Jonathan Cameron
2022-05-18 18:22 ` Dan Williams
2022-05-12 18:14 ` [PATCH 07/14] cxl/mem: Consolidate CXL DVSEC Range enumeration in " Dan Williams
2022-05-18 16:31 ` Jonathan Cameron
2022-05-18 16:52 ` Dan Williams
2022-05-18 17:24 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 08/14] cxl/mem: Skip range enumeration if mem_enable clear Dan Williams
2022-05-18 17:25 ` Jonathan Cameron
2022-05-12 18:15 ` [PATCH 09/14] cxl/mem: Fix CXL DVSEC Range Sizing Dan Williams
2022-05-18 16:40 ` Jonathan Cameron
2022-05-18 17:06 ` Dan Williams
2022-05-12 18:15 ` [PATCH 10/14] cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init() Dan Williams
2022-05-12 18:15 ` [PATCH 11/14] cxl/pci: Drop @info argument to cxl_hdm_decode_init() Dan Williams
2022-05-18 16:45 ` Jonathan Cameron [this message]
2022-05-12 18:15 ` [PATCH 12/14] cxl/port: Move endpoint HDM Decoder Capability init to port driver Dan Williams
2022-05-18 16:50 ` Jonathan Cameron
2022-05-12 18:15 ` [PATCH 13/14] cxl/port: Reuse 'struct cxl_hdm' context for hdm init Dan Williams
2022-05-18 16:50 ` Jonathan Cameron
2022-05-12 18:15 ` [PATCH 14/14] cxl/port: Enable HDM Capability after validating DVSEC Ranges Dan Williams
2022-05-16 18:41 ` Ariel.Sibley
2022-05-16 18:52 ` Dan Williams
2022-05-16 19:31 ` Ariel.Sibley
2022-05-16 20:07 ` Dan Williams
2022-05-18 0:38 ` [PATCH v2 " Dan Williams
2022-05-18 2:07 ` Ariel.Sibley
2022-05-18 2:44 ` Dan Williams
2022-05-18 15:33 ` Jonathan Cameron
2022-05-18 17:17 ` Jonathan Cameron
2022-05-18 18:00 ` Dan Williams
2022-05-18 0:50 ` [PATCH 00/14] cxl: Fix "mem_enable" handling Ira Weiny
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