From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>,
Ben Widawsky <ben.widawsky@intel.com>,
"Weiny, Ira" <ira.weiny@intel.com>,
"Schofield, Alison" <alison.schofield@intel.com>,
Vishal L Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 06/14] cxl/pci: Move cxl_await_media_ready() to the core
Date: Wed, 18 May 2022 18:20:50 +0100 [thread overview]
Message-ID: <20220518182050.00000963@Huawei.com> (raw)
In-Reply-To: <CAPcyv4jkY4txmuxhTk5oebf6yhbCzrJM5okdssz9HJrnqsgXYg@mail.gmail.com>
On Wed, 18 May 2022 09:37:24 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> On Wed, May 18, 2022 at 9:21 AM Jonathan Cameron
> <Jonathan.Cameron@huawei.com> wrote:
> >
> > On Thu, 12 May 2022 11:14:49 -0700
> > Dan Williams <dan.j.williams@intel.com> wrote:
> >
> > > Allow cxl_await_media_ready() to be mocked for testing purposes rather
> > > than carrying the maintenance burden of an indirect function call in the
> > > mainline driver.
> > >
> > > With the move cxl_await_media_ready() can no longer reuse the mailbox
> > > timeout override, so add a media_ready_timeout module parameter to the
> > > core to backfill.
> > >
> > > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> > > ---
> > > drivers/cxl/core/pci.c | 48 +++++++++++++++++++++++++++++++++++++++++
> > > drivers/cxl/cxlmem.h | 3 +--
> > > drivers/cxl/mem.c | 2 +-
> > > drivers/cxl/pci.c | 45 +-------------------------------------
> > > tools/testing/cxl/Kbuild | 1 +
> > > tools/testing/cxl/test/mem.c | 7 ------
> > > tools/testing/cxl/test/mock.c | 15 +++++++++++++
> > > 7 files changed, 67 insertions(+), 54 deletions(-)
> > >
> > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> > > index c9a494d6976a..603945f49174 100644
> > > --- a/drivers/cxl/core/pci.c
> > > +++ b/drivers/cxl/core/pci.c
> > > @@ -1,8 +1,11 @@
> > > // SPDX-License-Identifier: GPL-2.0-only
> > > /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
> > > +#include <linux/io-64-nonatomic-lo-hi.h>
> >
> > Curiously I see the pending branch no longer has this include
> > (which makes sense!)
>
> It never had it before since there were no readq calls in core/pci.c
> until this point.
I meant the cxl/pending tree seems to have a subtle difference
from what you have emailed out here in that the unnecessary extra
include isn't there. Editorial change I guess :)
>
> > Otherwise looks fine to me.
>
> Thanks!
Was thinking I'd give RB for the series, but as a few outstanding
bits and bobs I'll do it per patch.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
next prev parent reply other threads:[~2022-05-18 17:21 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-12 18:14 [PATCH 00/14] cxl: Fix "mem_enable" handling Dan Williams
2022-05-12 18:14 ` [PATCH 01/14] cxl/mem: Drop mem_enabled check from wait_for_media() Dan Williams
2022-05-18 17:21 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 02/14] cxl/pci: Consolidate wait_for_media() and wait_for_media_ready() Dan Williams
2022-05-18 17:22 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 03/14] cxl/pci: Drop wait_for_valid() from cxl_await_media_ready() Dan Williams
2022-05-18 17:22 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 04/14] cxl/mem: Fix cxl_mem_probe() error exit Dan Williams
2022-05-18 17:23 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 05/14] cxl/mem: Validate port connectivity before dvsec ranges Dan Williams
2022-05-18 16:13 ` Jonathan Cameron
2022-05-18 16:41 ` Dan Williams
2022-05-18 17:21 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 06/14] cxl/pci: Move cxl_await_media_ready() to the core Dan Williams
2022-05-18 16:21 ` Jonathan Cameron
2022-05-18 16:37 ` Dan Williams
2022-05-18 17:20 ` Jonathan Cameron [this message]
2022-05-18 18:22 ` Dan Williams
2022-05-12 18:14 ` [PATCH 07/14] cxl/mem: Consolidate CXL DVSEC Range enumeration in " Dan Williams
2022-05-18 16:31 ` Jonathan Cameron
2022-05-18 16:52 ` Dan Williams
2022-05-18 17:24 ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 08/14] cxl/mem: Skip range enumeration if mem_enable clear Dan Williams
2022-05-18 17:25 ` Jonathan Cameron
2022-05-12 18:15 ` [PATCH 09/14] cxl/mem: Fix CXL DVSEC Range Sizing Dan Williams
2022-05-18 16:40 ` Jonathan Cameron
2022-05-18 17:06 ` Dan Williams
2022-05-12 18:15 ` [PATCH 10/14] cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init() Dan Williams
2022-05-12 18:15 ` [PATCH 11/14] cxl/pci: Drop @info argument to cxl_hdm_decode_init() Dan Williams
2022-05-18 16:45 ` Jonathan Cameron
2022-05-12 18:15 ` [PATCH 12/14] cxl/port: Move endpoint HDM Decoder Capability init to port driver Dan Williams
2022-05-18 16:50 ` Jonathan Cameron
2022-05-12 18:15 ` [PATCH 13/14] cxl/port: Reuse 'struct cxl_hdm' context for hdm init Dan Williams
2022-05-18 16:50 ` Jonathan Cameron
2022-05-12 18:15 ` [PATCH 14/14] cxl/port: Enable HDM Capability after validating DVSEC Ranges Dan Williams
2022-05-16 18:41 ` Ariel.Sibley
2022-05-16 18:52 ` Dan Williams
2022-05-16 19:31 ` Ariel.Sibley
2022-05-16 20:07 ` Dan Williams
2022-05-18 0:38 ` [PATCH v2 " Dan Williams
2022-05-18 2:07 ` Ariel.Sibley
2022-05-18 2:44 ` Dan Williams
2022-05-18 15:33 ` Jonathan Cameron
2022-05-18 17:17 ` Jonathan Cameron
2022-05-18 18:00 ` Dan Williams
2022-05-18 0:50 ` [PATCH 00/14] cxl: Fix "mem_enable" handling Ira Weiny
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