From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, kernel test robot <lkp@intel.com>,
<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
<ira.weiny@intel.com>, <dave.jiang@intel.com>
Subject: Re: [PATCH 3/4] cxl/region: Fix port setup uninitialized variable warnings
Date: Wed, 3 Aug 2022 16:28:24 +0100 [thread overview]
Message-ID: <20220803162824.00005081@huawei.com> (raw)
In-Reply-To: <165951147487.967013.929590444907251028.stgit@dwillia2-xfh.jf.intel.com>
On Wed, 03 Aug 2022 00:24:34 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> 0day robot reports:
>
> drivers/cxl/core/region.c:1068 cxl_port_setup_targets() error: uninitialized symbol 'eiw'.
> drivers/cxl/core/region.c:1068 cxl_port_setup_targets() error: uninitialized symbol 'peig'.
> drivers/cxl/core/region.c:1068 cxl_port_setup_targets() error: uninitialized symbol 'peiw'.
>
> ...which are all valid reports. Add debug statement to consume the,
> albeit unexpected, errors.
>
> Fixes: 27b3f8d13830 ("cxl/region: Program target lists")
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/region.c | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index a073f16355ca..5c931b6eb4e7 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1059,8 +1059,21 @@ static int cxl_port_setup_targets(struct cxl_port *port,
> parent_iw = parent_cxld->interleave_ways;
> }
>
> - granularity_to_cxl(parent_ig, &peig);
> - ways_to_cxl(parent_iw, &peiw);
> + rc = granularity_to_cxl(parent_ig, &peig);
> + if (rc) {
> + dev_dbg(&cxlr->dev, "%s:%s: invalid parent granularity: %d\n",
> + dev_name(parent_port->uport),
> + dev_name(&parent_port->dev), parent_ig);
> + return rc;
> + }
> +
> + rc = ways_to_cxl(parent_iw, &peiw);
> + if (rc) {
> + dev_dbg(&cxlr->dev, "%s:%s: invalid parent interleave: %d\n",
> + dev_name(parent_port->uport),
> + dev_name(&parent_port->dev), parent_iw);
> + return rc;
> + }
>
> iw = cxl_rr->nr_targets;
> ways_to_cxl(iw, &eiw);
>
next prev parent reply other threads:[~2022-08-03 15:28 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-03 7:24 [PATCH 0/4] cxl/region: Endpoint decoder fixes Dan Williams
2022-08-03 7:24 ` [PATCH 1/4] cxl/region: Fix decoder interleave programming Dan Williams
2022-08-03 15:24 ` Jonathan Cameron
2022-08-03 7:24 ` [PATCH 2/4] cxl/region: Move HPA setup to cxl_region_attach() Dan Williams
2022-08-03 15:25 ` Jonathan Cameron
2022-08-03 7:24 ` [PATCH 3/4] cxl/region: Fix port setup uninitialized variable warnings Dan Williams
2022-08-03 15:28 ` Jonathan Cameron [this message]
2022-08-03 21:22 ` Ira Weiny
2022-08-04 20:26 ` Dan Williams
2022-08-03 7:24 ` [PATCH 4/4] cxl/region: Fix region commit uninitialized variable warning Dan Williams
2022-08-03 15:41 ` Jonathan Cameron
2022-08-03 21:49 ` Ira Weiny
2022-08-03 22:07 ` Ira Weiny
2022-08-04 20:33 ` Dan Williams
2022-08-04 20:30 ` Dan Williams
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