Re: [PATCH 3/4] cxl/region: Fix port setup uninitialized variable warnings

[Ira Weiny <ira.weiny@intel.com>]

On Wed, Aug 03, 2022 at 12:24:34AM -0700, Dan Williams wrote:
> 0day robot reports:
> 
> drivers/cxl/core/region.c:1068 cxl_port_setup_targets() error: uninitialized symbol 'eiw'.
> drivers/cxl/core/region.c:1068 cxl_port_setup_targets() error: uninitialized symbol 'peig'.
> drivers/cxl/core/region.c:1068 cxl_port_setup_targets() error: uninitialized symbol 'peiw'.
> 
> ...which are all valid reports. Add debug statement to consume the,
> albeit unexpected, errors.
> 
> Fixes: 27b3f8d13830 ("cxl/region: Program target lists")
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
>  drivers/cxl/core/region.c |   17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index a073f16355ca..5c931b6eb4e7 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1059,8 +1059,21 @@ static int cxl_port_setup_targets(struct cxl_port *port,
>  		parent_iw = parent_cxld->interleave_ways;
>  	}
>  
> -	granularity_to_cxl(parent_ig, &peig);
> -	ways_to_cxl(parent_iw, &peiw);
> +	rc = granularity_to_cxl(parent_ig, &peig);
> +	if (rc) {
> +		dev_dbg(&cxlr->dev, "%s:%s: invalid parent granularity: %d\n",
> +			dev_name(parent_port->uport),
> +			dev_name(&parent_port->dev), parent_ig);
> +		return rc;
> +	}
> +
> +	rc = ways_to_cxl(parent_iw, &peiw);
> +	if (rc) {
> +		dev_dbg(&cxlr->dev, "%s:%s: invalid parent interleave: %d\n",
> +			dev_name(parent_port->uport),
> +			dev_name(&parent_port->dev), parent_iw);
> +		return rc;
> +	}
>  
>  	iw = cxl_rr->nr_targets;
>  	ways_to_cxl(iw, &eiw);

Do you need to do something here to fix the potential uninitialized use of eiw?

Ira

>