From: Robert Richter <rrichter@amd.com>
To: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
Robert Richter <rrichter@amd.com>
Subject: [PATCH v2 03/12] cxl: Unify debug messages when calling devm_cxl_add_port()
Date: Tue, 18 Oct 2022 15:23:31 +0200 [thread overview]
Message-ID: <20221018132341.76259-4-rrichter@amd.com> (raw)
In-Reply-To: <20221018132341.76259-1-rrichter@amd.com>
CXL ports are added in a couple of code paths using devm_cxl_add_
port(). Debug messages are individually generated, but are incomplete
and inconsistent. Change this by moving its generation to devm_cxl_
add_port(). This unifies the messages and reduces code duplication.
Also, generate messages on failure. Use a __devm_cxl_add_port()
wrapper to keep the readability of the error exits.
Signed-off-by: Robert Richter <rrichter@amd.com>
---
drivers/cxl/acpi.c | 2 --
drivers/cxl/core/port.c | 51 +++++++++++++++++++++++++++++++----------
2 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index fb649683dd3a..767a91f44221 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -220,7 +220,6 @@ static int add_host_bridge_uport(struct device *match, void *arg)
port = devm_cxl_add_port(host, match, dport->component_reg_phys, dport);
if (IS_ERR(port))
return PTR_ERR(port);
- dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev));
return 0;
}
@@ -466,7 +465,6 @@ static int cxl_acpi_probe(struct platform_device *pdev)
root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
if (IS_ERR(root_port))
return PTR_ERR(root_port);
- dev_dbg(host, "add: %s\n", dev_name(&root_port->dev));
rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
add_host_bridge_dport);
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index bffde862de0b..9bfd01b4e5b5 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -655,16 +655,10 @@ static struct cxl_port *cxl_port_alloc(struct device *uport,
return ERR_PTR(rc);
}
-/**
- * devm_cxl_add_port - register a cxl_port in CXL memory decode hierarchy
- * @host: host device for devm operations
- * @uport: "physical" device implementing this upstream port
- * @component_reg_phys: (optional) for configurable cxl_port instances
- * @parent_dport: next hop up in the CXL memory decode hierarchy
- */
-struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
- resource_size_t component_reg_phys,
- struct cxl_dport *parent_dport)
+static struct cxl_port *__devm_cxl_add_port(struct device *host,
+ struct device *uport,
+ resource_size_t component_reg_phys,
+ struct cxl_dport *parent_dport)
{
struct cxl_port *port;
struct device *dev;
@@ -702,6 +696,41 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
put_device(dev);
return ERR_PTR(rc);
}
+
+/**
+ * devm_cxl_add_port - register a cxl_port in CXL memory decode hierarchy
+ * @host: host device for devm operations
+ * @uport: "physical" device implementing this upstream port
+ * @component_reg_phys: (optional) for configurable cxl_port instances
+ * @parent_dport: next hop up in the CXL memory decode hierarchy
+ */
+struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
+ resource_size_t component_reg_phys,
+ struct cxl_dport *parent_dport)
+{
+ struct cxl_port *port, *parent_port;
+
+ port = __devm_cxl_add_port(host, uport, component_reg_phys,
+ parent_dport);
+
+ parent_port = parent_dport ? parent_dport->port : NULL;
+ if (IS_ERR(port)) {
+ dev_dbg(uport, "Failed to add %s%s%s%s: %ld\n",
+ dev_name(&port->dev),
+ parent_port ? " to " : "",
+ parent_port ? dev_name(&parent_port->dev) : "",
+ parent_port ? "" : " (root port)",
+ PTR_ERR(port));
+ } else {
+ dev_dbg(uport, "%s added%s%s%s\n",
+ dev_name(&port->dev),
+ parent_port ? " to " : "",
+ parent_port ? dev_name(&parent_port->dev) : "",
+ parent_port ? "" : " (root port)");
+ }
+
+ return port;
+}
EXPORT_SYMBOL_NS_GPL(devm_cxl_add_port, CXL);
struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port)
@@ -1140,8 +1169,6 @@ int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd,
if (IS_ERR(endpoint))
return PTR_ERR(endpoint);
- dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev));
-
rc = cxl_endpoint_autoremove(cxlmd, endpoint);
if (rc)
return rc;
--
2.30.2
next prev parent reply other threads:[~2022-10-18 13:24 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-18 13:23 [PATCH v2 00/12] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-10-18 13:23 ` [PATCH v2 01/12] cxl/core: Remove duplicate declaration of devm_cxl_iomap_block() Robert Richter
2022-10-20 23:56 ` Dan Williams
2022-10-21 8:54 ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 02/12] cxl/core: Check physical address before mapping it in devm_cxl_iomap_block() Robert Richter
2022-10-21 0:01 ` Dan Williams
2022-10-18 13:23 ` Robert Richter [this message]
2022-10-21 0:20 ` [PATCH v2 03/12] cxl: Unify debug messages when calling devm_cxl_add_port() Dan Williams
2022-10-21 8:57 ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 04/12] cxl: Unify debug messages when calling devm_cxl_add_dport() Robert Richter
2022-10-21 0:32 ` Dan Williams
2022-10-21 9:00 ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 05/12] cxl/acpi: Improve debug messages in cxl_acpi_probe() Robert Richter
2022-10-21 1:00 ` Dan Williams
2022-11-14 20:11 ` [PATCH] tools/testing/cxl: Add bridge mocking support Dan Williams
2022-11-15 10:33 ` Robert Richter
2022-11-15 18:11 ` Dan Williams
2022-12-02 16:59 ` Jonathan Cameron
2022-10-18 13:23 ` [PATCH v2 06/12] cxl/acpi: Extract component registers of restricted hosts from RCRB Robert Richter
2022-10-18 13:31 ` Rafael J. Wysocki
2022-10-18 18:41 ` Robert Richter
2022-10-18 18:57 ` Rafael J. Wysocki
2022-10-19 10:46 ` Robert Richter
2022-10-21 5:17 ` Dan Williams
2022-10-24 21:04 ` Robert Richter
2022-10-24 21:24 ` Dan Williams
2022-10-24 22:37 ` Dan Williams
[not found] ` <63cd195a-f5d0-b016-d833-b3a9c86ff6ee@intel.com>
2022-10-24 23:50 ` Robert Richter
2022-10-24 23:57 ` Dan Williams
2022-10-18 13:23 ` [PATCH v2 07/12] cxl: Remove dev_is_cxl_root_child() check in devm_cxl_enumerate_ports() Robert Richter
2022-10-21 5:38 ` Dan Williams
2022-10-21 6:32 ` Verma, Vishal L
2022-11-09 14:33 ` Robert Richter
2022-10-18 13:23 ` [PATCH v2 08/12] cxl: Factor out code in devm_cxl_enumerate_ports() to find_port_attach_ep() Robert Richter
2022-10-18 13:23 ` [PATCH v2 09/12] cxl: Extend devm_cxl_enumerate_ports() to support restricted devices (RCDs) Robert Richter
2022-10-18 13:23 ` [PATCH v2 10/12] cxl: Do not ignore PCI config read errors in match_add_dports() Robert Richter
2022-10-18 13:23 ` [PATCH v2 11/12] cxl: Factor out code in match_add_dports() to pci_dev_add_dport() Robert Richter
2022-10-18 13:23 ` [PATCH v2 12/12] cxl: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Robert Richter
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